JPS63294084A - Data input and output system for picture frame memory - Google Patents

Abstract

PURPOSE:To easily process picture information between adjacent picture elements by providing a mode discriminating means and a field discriminating means and inputting and outputting the picture data of an interlace scanning system or a non-interlace scanning system. CONSTITUTION:An FF4 latches a scanning mode switching signal EX at the timing of a frame start signal FS and controls the change over of switches S1-S3 by a Q output. A field counter 5 is reset by the input of the signal FS, a vertical blanking signal V is inputted to a CK terminal, thereby, 1 or 0 is Q outputted according to a first and second field periods. Thereby, at the time of interlace scanning a picture memory 1, a row address is designated from a first row, only odd number rows are sequentially designated in the first field, only even number rows are sequentially designated in the second field. At the time of non-interlace scanning the memory 1, the row address is designated from 0 the row and the address is designated sequentially for every row. Thereby, the picture information between the adjacent picture elements can be easily processed.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to data in an image frame memory that enables input/output of video signals (image data) in either an interlaced scanning method or a non-interlaced scanning method. Regarding input/output methods.

[Conventional technology]

Most commercially available television cameras obtain image signals (video signals) by performing interlaced scanning of the object to be imaged using the so-called NTSC method, and as a result, the video signal of one frame (one screen) is consists of signals for two fields.

FIG. 6 is an explanatory diagram for explaining the image scanning method using the interlace method. That is, in order to transmit area (two-dimensional) information with a single signal, a television performs scanning, and normally a large number of horizontal scanning lines (HL) are used as shown in the figure.

H2, H3,...). Scanning is performed from the ST1 point (or ST2 point) at the upper left corner of the screen,
Ends at the EDI point (or ED2 point) in the lower right corner.

This completes the scanning of one field, and two fields constitute one screen (one frame).

The number of scanning lines in each field is the same, but the scanning positions are interpolated with each other to increase screen resolution without lengthening the field period.

FIG. 4 is an explanatory diagram for explaining the signal format of a television signal based on the interlaced scanning method. In the figure, one frame period consists of a first field period and a second field period, and each field contains 262 fields.
．． 5 horizontal scanning periods (Hl, H3, H5,...
) and a corresponding horizontal blanking signal H exists,
Similarly, within the second field, there are 262.5 horizontal scanning periods (H2, H4.

H6, . . .) and a corresponding horizontal blanking signal exists.

However, in conventional technical fields such as image measurement and inspection, it is difficult to use high-definition image data scanned from the video signal data of two fields that make up one frame as one frame of image data. Instead, it is common to use coarsely scanned, low-resolution image data consisting of video signal data for one field, and discard the remaining data for one field.

[Problem that the invention seeks to solve]

However, in recent years, the stability of camera operation has increased, and even higher resolution image measurement and inspection are required. There is a growing demand for processing that For example, as shown in FIG. 5, the two-dimensional local memory 8 is used to extract 6 x 3 adjacent pixel data centered on the pixel of interest, and this is sent to the local arithmetic circuit 9 to perform appropriate calculations to create the pixel data of interest. When it is required to process interlaced image data, there is a problem that it is difficult to handle the interlaced image data as it is. In other words, in the interlaced scanning method, as mentioned above, two pixels adjacent to each other in the vertical direction in one frame, if one belongs to the first field, the other belongs to the second field, and the time series When viewed as a standard video signal, the video signal corresponding to one pixel and the video signal corresponding to the other pixel differ by the time required to scan one field, so the adjacent pixels This means that it will be difficult to process the information as such.

In FIG. 5, 6 is an imaging device, 7 is an A/D converter, and 8 is a shift register 81 to 86 and a delay circuit 84.
．． 85 represents a two-dimensional local memory, and 9 represents a local arithmetic circuit.

Therefore, an object of the present invention is to enable input/output of image data of either interlaced scanning method or non-interlaced scanning method, thereby providing flexibility and facilitating image information processing between adjacent pixels.

[Means for solving problems]

1st. For an image frame memory having a capacity for at least one frame consisting of a second field, mode determining means determines whether the mode is an interlace mode or a non-interlace mode, and whether the image frame memory is a first field period or a second field period in the interlace mode. Based on these mode discrimination results and field discrimination results, only the addresses of the odd (even) rows of the memory are sequentially specified during the first field period in the interlaced mode, and in the same mode During the second field period of , only the addresses of even (odd) rows of the memory are specified in order, while
In the non-interlaced mode, an address specifying means for sequentially specifying the row address of the memory from the beginning is provided, so that image data of either the interlace scanning method or the non-interlace scanning method can be input/output.

[Effect]

During interlaced access, of the signals for one frame to be input/output, only odd row (or even row) addresses are sequentially specified for the first field signal, and the second field signal is For non-interlaced accesses, only even-numbered (or odd-numbered) row addresses are specified sequentially, while for non-interlaced accesses, row addresses are specified sequentially from the beginning regardless of whether they are odd or even. Both types of interlaced scanning also allow input and output of video signals (image data) to provide flexibility and facilitate image information processing between adjacent pixels.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes an image memory, that is, a memory that can store one frame's worth of video signals in the form of pixel data, and has the same number of rows as the number of horizontal scanning lines over one frame period, and Assume that the number of columns is the same as the number of pixels. Reference numeral 2 denotes a horizontal address counter, which is reset every time the horizontal blanking signal H in the television signal is seen at the reset terminal R, and is incremented every time the horizontal clock signal CL is input to the input terminal CK. A counter outputs a horizontal address for storing (or reading) an image signal (pixel data) to the image memory 1. 3 is a vertical address counter, which is reset by inputting a vertical blanking signal V in a television signal to a reset terminal R via a switch S1 when performing interlaced scanning of the image memory 1; Each time the horizontal blanking signal H is input to the terminal CK, it is counted, and the vertical storage address is output to the image memory 1 via the switch S3 located on the solid line side. On the other hand, when performing non-interlace scanning on the image memory 1, the frame start signal FS in the television signal is reset by being input to the reset terminal R via the switch s1 located on the broken line side, and the horizontal blanking signal It is counted by inputting H to the terminal CK to create a vertical address,
The signal is output to the image memory 1 via switches s2 and s3 located on the side of the broken line. Note that the output QO of the least significant digit of the vertical address counter 3 supplies the direct output of the least significant digit (bo) of the row address to the image memory 1 via the switch S2 located at the dashed line position. 5 is a field counter, and a terminal R resets the frame start signal FS.
The signal is reset by being input to the vertical blanking signal Vt-CK terminal, and the signal is reset by being input to the vertical blanking signal Vt-CK terminal.
When in the first field period, for example, "1" is outputted, and when in the second field period, "0" is outputted as the Q output.The output of the field counter 5 is the Q output of the switch S2.
The address of the least significant digit bo is input to the image memory 1 via .

4 is the scanning mode switching signal EX and the frame start signal FS.
A flip-flop latches at the timing of , and the Q output of the flip-flop 4 controls the switching of the switches 81 to S3. That is, when the scanning mode switching signal EX is significant (logic "1": non-interlaced mode), switches 81 to S3 are switched to the dashed line position, that is, downward; when it is meaningless (logic "0"): (in interlace mode), the position is switched to the solid line position, that is, upward.

By doing this, when interlace scanning the image memory 1, the row address specification starts from the first line, sequentially specifying only odd numbered lines in the first field, and only even numbered lines in the second field. When the image memory 1 is sequentially specified and the image memory 1 is scanned in a non-interlaced manner, the line address specification starts from the zeroth line, and the address specification can be carried out sequentially for each line.

That is, when performing interlaced scanning on the image memory 1, the read/write signal RW is set to either one, the scanning mode switching signal EX is set to logic "0'", and the output Q of the flip-flop 4 at that time is used to switch the switches 81 to 81.
Switch S3 to the solid line position as shown. For this,
The row addressing signals supplied to the image memory 1 are
When the output image signals ID and OD are in the first field period, starting from the first row, 3, 5, 7, . ...
. . . becomes a signal specifying the row address of an odd numbered row, and when the output image signals ID and OD move to the second field period, starting from the zero row, 2° 4.6... ...
... is a signal that specifies the row address of even-numbered rows, and output image signals ID and OD using the interlace scanning method.
input to and output from the image memory 1. In other words, in the first (second) field, the lowest digit bo of the row address is '1''(''(]''
), for example, the 6th from the lowest. Second
Focusing on the th digit b2゜bl, this is determined by the output of the counter 6 as (o, o)t(o, 1), (1, o), (
1゜1), the lower 3 bits are 00.
1 (000), 011' (010), 101 (100)
, 111 (110), i.e. 1 (2).

3(4), 5(6), 7(8), etc., and only odd numbered rows (even numbered rows) are addressed.

On the other hand, when performing non-interlace scanning on the image memory 1, the scanning mode switching signal EX is set to logic "1", and the switch 81
~S3 is switched to the broken line position (lower position). Accordingly, the row addressing signal supplied to the image memory 1 is
1.2 in sequence starting from the zero row over one frame period.
, 3, 4°...... signals specifying the row address.
It becomes possible to input the output image signals ID and OD to the image memory 1 and output them from there.

FIG. 2 shows examples of signal waveforms input to each section in FIG. 1.

In the figure, F indicates a frame signal, V' indicates an enlarged waveform of the vertical blanking signal V, and since the other details are the same as in FIG. 4 and need no further explanation, they will be omitted.

〔Effect of the invention〕

According to the present invention, it is possible to easily convert a video signal in which one screen (one frame) is made up of two fields using an interlaced scanning method into a video signal using a non-interlaced scanning method. By incorporating this method, even for high-definition screens, image information processing based on simultaneous illumination of adjacent pixels in a predetermined range using conventional two-dimensional local memory becomes easier. This provides the advantage of being able to respond flexibly to various situations.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a waveform diagram showing input signals of each part in Fig. 1, and Fig. 3 is a diagram for explaining a general image scanning method using the interlace method. 4 is an explanatory diagram for explaining the signal format of a television signal using the interlaced scanning method as shown in FIG. 3, and FIG. 5 is a block diagram showing an example of a conventional image information processing circuit between adjacent pixels. It is. Description of symbols 1... Image memory, 2... Horizontal address counter, 6... Vertical address counter, 4...00. Flip-flop, 5...
・Field counter, 6... Imaging device, 7.
...A/D converter, 8...Two-dimensional local memory, 81-85...Shift register, 84.
85...Delay circuit, 9...Local arithmetic circuit, H...Horizontal blanking signal, ■...
Vertical blanking signal.薯2 Figure i A fmIv1 Mei 3 Figure 4 Figure 11111111 @ 5 Figure

Claims (1)

[Scope of Claims] A mode determining means for determining whether an image frame memory having a capacity of at least one frame consisting of first and second fields is in an interlace mode or a non-interlace mode; Field discrimination means for discriminating whether it is a 1-field period or a 2nd field period, and based on these mode discrimination results and field discrimination results, only addresses of odd (even) rows of the memory during the 1st field period in interlace mode. During the second field period in the same mode, only the addresses of the even (odd) rows of the memory are specified in order, while in the non-interlaced mode, the row addresses of the memory are specified in order from the beginning. 1. A data input/output method for an image frame memory, comprising: address designating means for specifying the address;