JPS63293874A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance the soft error resistance as well as to achieve a high integration by forming charge storage regions through a dielectric film on the side surfaces and the bottoms of the grooves provided in a substrate, and forming a field-effect transistor on the charge storage regions in the vertical direction. CONSTITUTION:Thin grooves are formed in a P-type silicon substrate 1 of a high impurity concentration, and after forming a dielectric film 6 on the surface of the grooves, the grooves are filled with N<+> polysilicon 7 becoming charge storage regions. Then, an insulating film 8 is formed on the polysilicon 7, further N<+> polysilicon 3 becoming a word line is formed on the film 8, and an insulating film 9 is formed. Then, thin grooves passing through the polysilicon 3 is formed, and a gate oxide film 4 is formed. Then, thin grooves are formed till they reach the polysilicon 7, and P-type polysilicon 5 becoming a channel region and N<+> polysilicon 2 becoming a bit line is formed.

Description

[Detailed description of the invention] Industrial applications The present invention relates to semiconductor memory.

Conventional technology As a memory cell for highly integrated semiconductor memory, so-called "one-transistor type" memory, which is composed of one transistor and one capacitor, is widely used because it has few components and the cell area can be easily miniaturized. There is.

In recent years, higher integration and larger capacity of semiconductor memories have been pursued, and miniaturization of elements has been required. In a one-transistor type memory cell, a decrease in memory cell capacity must be avoided as much as possible in order to maintain ease of information determination. For this reason, in the conventional technology, a groove is dug in a semiconductor substrate and the side surfaces of the groove are used as a capacitor part, thereby reducing the planar area of the capacitor part and miniaturizing the element. For example, in the configuration shown in FIG. 3, a groove is dug in the semiconductor substrate 11 and the plate electrode 17 is embedded in the groove, and a capacitive portion is formed on the side surface of the groove. 12 is a pit line, 13 is one region, 14 is a word line, 16 is a dielectric film, 16 is an isolation region, 18 is a gate oxide film, and 19 is a charge storage region.

Problems to be Solved by the Invention However, in the conventional configuration described above, the trench serving as the capacitor portion and the transistor are located at different locations, and a separation region is required between the memory cells, making it difficult to achieve high integration. Ta.

In addition, α particles that enter the capacitor generate electron-hole pairs along the trajectory, but the holes move to the substrate 11 and only the electrons remain in the capacitor, resulting in a change in the stored information. There is.

An object of the present invention is to provide a semiconductor memory that is more highly integrated and has higher resistance to soft errors caused by alpha rays than the conventional method.

Means for Solving the Problems The memory cell of the semiconductor memory of the present invention includes a dielectric film formed in a trench provided in a semiconductor substrate on the side and bottom surfaces of the trench, and a charge storage region on the dielectric film. A field effect transistor is formed in the vertical direction on the charge storage region.

By adopting this configuration, the field effect transistor above the charge storage region is used as a switching element, and a capacitor portion is formed between the semiconductor substrate and the charge storage region via a dielectric film.

Example Hereinafter, the present invention will be explained in detail using the drawings.

An example of the structure of a semiconductor memory according to the present invention is shown in FIG. FIG. 1 & is a plan view, FIG. 1 is a sectional view taken along the line Mumm', and FIG. 1 C is a sectional view taken along the line B--B/. Is 1 a high impurity concentration? Area is silicon substrate, 2 is n+ polysilicon for pit line, 3 is n+ polysilicon for word line, 4 is
6 is a gate oxide film, 6 is a P-type polysilicon channel region, 6 is a dielectric film, 7 is an n+ polysilicon charge storage region, and 8 is an insulating film. A field effect transistor is formed between pit line 2 and charge storage region 7 using word line 3 as a gate electrode. A capacitor portion is formed between the substrate 1 and the charge storage region 7 with a dielectric film 6 interposed therebetween.

FIGS. 2a, 2b, and 2c are process cross-sectional views for explaining the manufacturing method of this embodiment.

First, as shown in FIG. 2a, a narrow groove is formed in the P-substrate or P+ epitaxial layer 1 by dry etching, a dielectric film 6 is formed on the surface of the groove, and the groove is covered with an n+ polyethylene film which will become a charge storage region. Fill with silicon 7. Next, as shown in FIG. 2, an insulating film, for example, 5i02
B, and furthermore, on the insulating film 8, an n+
After forming polysilicon 3, an insulating film 9 is formed on the entire surface. Subsequently, as shown in FIG. 2, a narrow groove is formed until the polysilicon 3 penetrates through it, and then a gate oxide film 4 is formed. Then, as shown in Figure 1, after forming a narrow groove until it reaches the polysilicon 7, the narrow groove is filled with n+ polysilicon, P-type polysilicon that will become the channel region, silicon s, and n+ polysilicon in this order. N+ polysilicon 2 is formed to form a line.

Actual implementation! In the memory cell No. 1, the capacitive part is formed through the dielectric film 6 in the narrow groove to increase the memory cell capacity, and the transistor is formed on the capacitive part, and no isolation region is required. Compared to the conventional example shown in FIG. 3, the planar area of the memory cell can be reduced to about one-third.

Furthermore, since the information storage section is located within the charge storage region T surrounded by the dielectric film 6, even if electrons and holes are generated due to the incidence of α particles, they are recombined within the charge storage region 7. Since it disappears, it does not change the accumulated charge. That is, a memory cell with high soft error resistance can be obtained.

The embodiments shown above are specific examples of the semiconductor memory of the present invention, and are not limited thereto.

In this embodiment, a case has been described in which an n-channel field effect transistor is used, but a case in which a p-channel field effect transistor is used can also be manufactured through similar steps. Further, the shape of the transistor or capacitor portion of the memory cell may be any shape. It is also possible to use polysilicon for the substrate, which is included in the present invention.0 Effects of the Invention As explained in detail above, according to the present invention, a capacitive portion and a capacitive portion are formed in a groove provided in a semiconductor substrate. By forming field effect transistors in the vertical direction, it is possible to obtain a highly integrated semiconductor memory with high soft error resistance, which is highly effective.

[Brief explanation of the drawing]

FIG. 1a is a plan view of a semiconductor memory according to an embodiment of the present invention, and FIGS.
Sectional view along line BB', Figure 2a. b and c are process cross-sectional views for explaining the method of manufacturing the memory of the same embodiment, and FIG. 3 is a cross-sectional view of a conventional semiconductor memory. 1... Board, 2... Bit line, 3...
...Word line, 4...Gate oxide film, 6.
...Channel region, 6...Dielectric film,
7...Charge storage region, 8.9...Insulating film. Name of agent: Patent attorney Toshio Nakao and one other name
2 Figure

Claims (1)

[Claims] In a trench provided in a semiconductor substrate, a dielectric film serving as a storage capacitor is formed on the side and bottom surfaces of the trench, a charge storage region is formed on the dielectric film, and a charge storage region is formed on the charge storage region in the vertical direction. A semiconductor memory comprising a field effect transistor formed.