JPS63288577A - Mosaic image device - Google Patents

Abstract

PURPOSE:To execute the display of respectively different mosaic shapes with the images of respective areas by respectively displaying the same image in numerous rectangle areas whose horizontal direction is stipulated by a prescribed dot width and vertical direction is stipulated by a prescribed line width. CONSTITUTION:Primary color signals R, G and B decoded by a decoder 1 and converted by an A/D converting circuit 2 are latched in a latch circuit 3 and written to a line memory 4. In a latch clock generating circuit 5, based on a dot width selecting signal to select the number of dots to the horizontal direction of a mosaic display pattern and a dot clock inverting QA, the latch clock of a frequency in correspondence with the number of dots is generated and given to the latch circuit 3. In a line memory control circuit 6, based on a line width selecting signal to select the number of lines to the vertical direction of the mosaic display pattern and a horizontal blanking signal, depending on the number of lines, a writing and a reading are controlled so that data for one line can be repeatedly read from the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a mosaic video device that is installed in television receivers, computer televisions, and the like, and is capable of expressing a special mosaic-like image.

<Prior art> In recent years, while efforts have been made to improve the performance of AV (audio-visual) equipment, the use of simply enjoying images (image-wise) is expanding, and video devices capable of special image expression are becoming more and more popular. desired.

<Object of the Invention> The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide a mosaic video device capable of expressing a special mosaic-like video.

<Structure of the Invention> In order to achieve the above-mentioned object, the present invention includes a latch circuit that latches an A/D converted video signal in response to a latch clock, an output of this latch circuit that is aged, Based on the single line memory to be read out, a dot width selection signal for selecting the number of dots in the horizontal direction of the mosaic display pattern, and the dot clock, a latch clock having a period corresponding to the number of dots is generated and applied to the latch circuit. L line data is repeatedly read from the line memory over the number of lines based on a latch clock generation circuit to be applied, a line width selection signal for selecting the number of lines in the vertical direction of the mosaic display pattern, and a horizontal blanking signal. and a line memory control circuit that controls writing and reading so that the data is read out from the line memory, and is configured to display a mosaic pattern based on the data read from the line memory.

According to the above configuration, since the same data is held in the latch circuit over a predetermined number of dots in the horizontal direction corresponding to the dot width selection signal, the same data is stored in the line memory over the predetermined number of dots. Furthermore, data for one line of the line memory is repeatedly read over a predetermined number of lines in the vertical direction corresponding to the line width selection signal. The same image is displayed in a large number of rectangular (mosaic-like) areas each defined by the number of lines and the number of dots, and different images are displayed in each area.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention,
The mosaic video device of this embodiment is installed in a computer.

In the mosaic video device of the present invention, as shown in FIG.
a3(X)..., horizontal X dot, vertical Y dot)
(Y line) rectangular areas A I , A 2 , A 3
A mosaic-like display is performed by repeatedly displaying .... For this purpose, the same data is written in the line memory over the X dots in the horizontal direction, and then IH (H The configuration is such that data corresponding to a horizontal scanning period) is repeatedly read out over the Y line in the vertical direction.

That is, as shown in FIG. 1, this mosaic video device receives 4-bit primary color signals R, G,
Latch circuit 3 that latches B in response to a latch clock
and the output of this latch circuit 3 is written, and
A latch clock having a period corresponding to the number of dots is generated based on the single line memory 4 to be read out, the dot width selection signal for selecting the number of dots X in the horizontal direction of the mosaic display pattern, and the dot clock QA. a latch clock generation circuit 5 which supplies the latch circuit 3 with the latch clock;
Line width selection signal and wood blanking signal HBL for selecting the number of lines Y in the vertical direction of the mosaic display pattern
A line memory control circuit 6 is provided which controls readout based on the number of lines so that data for one line is repeatedly read out from the line memory 4 over the number of lines.

The latch clock generation circuit 5 generates an integer multiple (2 times, 4 times) of the period based on the dot clock QA.

Based on the 3-bit dot width selection signal, the dot clock QA and the corresponding one of the outputs of the frequency divider circuit 7 are used. The first selector 8 selectively outputs the clock as a latch clock.

The line memory control circuit 6 includes a down counter 9 that counts the horizontal blanking signal shown in FIG. 3(B) and provides 5-bit outputs Ql-Q5 shown in FIG. 3(C) to (G). , the horizontal blanking signal and the horizontal blanking signal shown in FIG. ~(L
) as shown in 2H, 4H, 8H, 16H, 32H
Each OR gate 10-14 becomes low level at each time.
Write enable signal ~V
Second selector 1 selectively outputs to line memory 4 as E
5 and IH by delaying the horizontal blanking signal for a predetermined time.
Line memory 4 as the same cycle-do enable signal RE.
A delay circuit 16 is provided. In addition, Figure 3 (
A) is a vertical blanking signal.

In this mosaic video device, the latch clock generation circuit 5 generates a latch clock with a period corresponding to the X dots in the horizontal direction of the mosaic display and latches the data written to the line memory 4. Data is written to the line memory 4, and this data is read out every dot clock QA.
The configuration is such that 8 minutes of data is repeatedly read out over the Y line.

The number of dots in the horizontal direction of this mosaic display pattern
The 3-bit dot width selection signal and line width selection signal for selecting the number of lines Y in the vertical direction, respectively, are selected by the viewer, and a mosaic display of a desired size is thereby performed.

Next, the operation of the mosaic video device having the above configuration will be explained.

First, the horizontal mosaic display will be explained based on the time charts of FIGS. 4 and 5. Figure 4 (
A) is the dot clock QA, and FIG. 4(B) is the 12-bit video data given to the latch circuit 3, that is,
The A/D converted primary color signal, FIG. 4(C) is the latch clock output from the latch clock generation circuit 5 based on the dot width selection signal, and FIG. 4(D) is the output of the latch circuit 3, 4(E) shows the write clock to the line memory 4, FIG. 5(A) shows the read clock of the line memory 4, and FIG. 5(B) shows the output data of the line memory 4.

In this example, a mosaic display of four dots in the horizontal direction is selected by the dot width selection signal, and the latch clock generator circuit 5 outputs the latch clock signal shown in FIG. 4(C), which is obtained by dividing the dot clock I by four. is applied to the latch circuit 3. Therefore, in the latch circuit 3, as shown in FIG.
) as shown in 4 dots. , d-
, da... are held, and this data is stored in the line memory 4.
will be written to. By reading out the line memory 4 using the read clock shown in FIG. 5(A) which is a delayed version of the dot clock QA, the same data d is obtained across four dots, as shown in FIG. 5(B). , d4. d
,... will be read out.

Next, vertical mosaic display will be explained based on the time chart of FIG. 6(A) shows the horizontal blanking signal, FIG. 6(B) shows the write enable signal WE output from the line memory control circuit 6 based on the line width selection signal, and FIG. 6(C) shows the line memory FIG. 6(D) shows the data written to the line memory 4 under the read enable signal τ, and FIG. 6(E) shows the data read from the line memory 4.

This example shows a case where a mosaic display of 4 vertical lines (4 dots) is selected, and the line memory control circuit 6 outputs a 4H period write enable signal WE shown in FIG. 6(B). Ru.

Therefore, data is written to the line memory 4 every 4H. By reading out the IH same period from this line memory 4 according to the glue enable signal RE in FIG. 6(D), as shown in FIG. 6(E),
The same data will be read repeatedly over 4H.

In this way, the same video signal is output from the line memory 4 over four dots in the horizontal direction and four lines in the vertical direction, so a large number of rectangles defined by 4 dots x 4 lines are output. The same image will be displayed in a (mosaic-like) area, and the images in each area will be different from each other.

In this embodiment, it is also possible to select a normal display, that is, one dot in the horizontal direction and one line in the vertical direction, instead of the mosaic display, by using the dot width selection signal and the line width selection signal.

<Effects of the Invention> As described above, according to the present invention, the same image can be displayed in a large number of rectangular areas defined by a predetermined dot width in the horizontal direction and a predetermined line width in the vertical direction. Moreover, the images in each area can be displayed in a mosaic pattern that differs from each other, allowing the user to enjoy the images intuitively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing a mosaic display, FIG. 3 is a signal waveform diagram of each part of the line memory control circuit 6, and FIGS. 4 and 5 are horizontal directions. FIG. 6 is a time chart for explaining mosaic display in the vertical direction. 3...Latch circuit, 4...Line memory, 5...
Latch clock generation circuit, 6... line memory control circuit.

Claims (1)

[Claims] (1) A latch circuit that latches an A/D converted video signal in response to a latch clock, a single line memory into which the output of this latch circuit is written and read, and a horizontal direction of a mosaic display pattern. a latch clock generation circuit that generates a latch clock with a cycle corresponding to the number of dots based on a dot width selection signal for selecting the number of dots and a dot clock, and supplies the generated latch clock to the latch circuit; and the number of lines in the vertical direction of the mosaic display pattern. writing so that data for one line is repeatedly read from the line memory over the number of lines based on a line width selection signal and a horizontal blanking signal that select
and a line memory control circuit that controls reading, and based on the data read from the line memory,
A mosaic video device characterized by displaying a mosaic pattern.