JPS63285769A - Time compressing circuit - Google Patents

Abstract

PURPOSE:To automatically decide a time compression ratio with a small memory capacity, by successively changing the compression ratio to higher ones and, at the same time, reading out a memory signal as the signal of an aimed compression ratio in accordance with the time of recording sound signals. CONSTITUTION:A CPU 12 impresses compression ratio selecting signals upon a memory controlling circuit 14 and sound data are written in a memory at a compression ratio of 1/320. When the recording time exceeds five and ten seconds, the compression ratio is changed to 1/640 and 1/1280, respectively. The memory controlling circuit 14 impresses sampling clocks corresponding to the compression ratio upon an A/D converter 18 and the cut-off frequency of a pre-filter 16 is set at a band meeting a sampling theorem. The sound data written in the memory 20 are subjected to band limitation at an LPF 21 and analog conversion at a D/A converter 22 and clocks are supplied to the data from the memory controlling circuit 14. Then the data are recorded on a disk 10 after a time-compressed base band component is fetched.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a time compression circuit that compresses the time axis of a signal.

[Conventional technology]

One of the devices in which a time compression circuit is used is a still/video recording device capable of recording audio. A still video recording device compresses audio signals of approximately 5 seconds, approximately 10 seconds, and approximately 20 seconds at a compression rate of 1/320.1/640.1/1280, respectively, and records them on a still video disc. The time compression circuit basically prepares a memory with a capacity that can accommodate recordable compression in one trunk of the disk, and adjusts the ratio between the sampling clock and the successive speed when writing to the memory. It was realized by this. Therefore,
In principle, the compression ratio must be determined in advance.

Compression circuits are also known that can determine the compression ratio a posteriori, that is, depending on the length of the audio signal to be recorded. However, in that circuit, even if the lowest compression rate among multiple compression rates is selected after the fact, the amount of signal corresponding to the maximum recordable time is compressed at the lowest compression rate so that satisfactory compression is possible. For example, in the case of the above still video, the maximum compression rate is 20 seconds, and at the lowest compression rate it is 5 seconds, so
Storage capacity for the trunk is required.

[Problem that the invention seeks to solve]

However, in the conventional example where the compression ratio is set in advance, the compression ratio is set to 1.
/320 (approximately 5 seconds) or 1/640 (approximately 10 seconds), it is impossible to record on one track even if the recordable time is slightly exceeded. Either the data can be rewritten, or it can be recorded across two or more tracks with the same compression ratio.

Recording across two or more tracks is extremely inefficient and is not a preferred method.

Furthermore, the above-mentioned conventional example in which the compression ratio can be selected after the fact requires a large amount of memory capacity and is therefore not efficient.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a time-domain pressure circuit that can flexibly select a compression ratio depending on the length of a signal to be processed with a minimum memory capacity.

[Means for solving problems]

A time compression circuit according to the present invention is a circuit capable of time-base compressing an input signal at a plurality of compression ratios, and includes a memory means and an input signal initially written into the memory means at a sampling rate corresponding to a predetermined compression ratio. , when the signal for the processing unit time at that compression rate is written to the memory means, sequentially,
A memory writing means for changing the sampling rate to a sampling rate corresponding to a higher compression ratio, and a storage signal of the memory means,
and readout control means for reading out a signal of a target compression ratio.

[Effect]

The write control means allows the memory means to store an amount of data corresponding to the processing unit time, even if the signal requires the maximum compression rate. Then, after storing it in the memory means, the optimum compression ratio is determined, and when reading continuously, the readout control means performs sub-sampling or the like.
The memory capacity for reading data stored in the memory means to achieve the optimum compression ratio needs to be slightly larger than the processing unit time, and therefore automatic determination of the compression ratio can be realized with a small memory capacity.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of the configuration of an embodiment applied to a still/video recording device capable of recording audio.

10 is a disc to be recorded. The CPU 12 applies a compression ratio selection signal to the memory control circuit 14, and the memory control circuit 14 applies a sampling clock corresponding to the compression ratio of the selection signal to the A/D converter 18, and adjusts the cutoff frequency of the prefilter 16. is a band that satisfies the sampling theorem. For example, 15 is about 28.64
This is an oscillation circuit that generates a clock of MHz (8fs). At the initial stage of audio signal input, the CPU 12:
Minimum compression rate of 1/32 that allows recording of the widest frequency band
Select 0. As a result, the cutoff frequency of prefilter 16 is approximately 10 KHz, and the sampling clock to A/D converter 18 is approximately 22.4 KHz. In addition,
When the compression ratio is 1/320.1/640.1/1280,
The clock frequencies to the A/D converter 18 are approximately 22°4 KHz, 11.2 KHz, and 5.6 KHz, respectively.
The cutoff frequency of the prefilter 16 is approximately 1
0 KHz, about 5 KHz and about 2.5 KHz.

From this initial setting state, audio data is sequentially written into the memory 20 according to the address signal from the memory control circuit 14. The compression rate remains the same until about 5 seconds worth of audio data, which is the shortest recordable time, is written into the memory 20. When approximately 5 seconds worth of audio data is written to the memory 20, the CPU 12 changes the compression ratio to 1/640. According to this change, the frequency of the sampling clock supplied to the A/D converter 18 is approximately 11.2 KHz;
The cutoff frequency of prefilter 16 is changed to approximately 5KHz. The recordable time for one track at a compression rate of 1/640 is approximately 10 seconds, but since approximately 5 seconds have already been written to the memory 20 at a compression rate of 1/320, the remaining time is approximately 5 seconds (that is, the total (approx. 10 seconds), the compression ratio is 1/
Writing to the memory 20 is performed at 640.

If the total input signal exceeds the recordable time for one track (approximately 10 seconds) at a compression rate of 1/640, the compression rate will be reduced to 1/1.
280, and the cutoff frequency of the prefilter 16 is changed to approximately 2.5 KHz, and the frequency of the sampling clock to the SA/D converter 18 is accordingly changed to approximately 5.6 KHz. The output of the A/D converter 18 is written to the memory 20 with a clock of approximately 5°6 KHz.

At this compression rate of 1/1280, the recordable time per track is approximately 20 seconds, but at the compression rate of 1/320, it is already approximately 5 seconds, and at the compression rate of 1/640, it is approximately 5 seconds, for a total of approximately 10 seconds. has been written into the memory 20, so there is enough room to write the remaining time into the memory 20 for about 10 seconds.

Of course, once the input of the audio signal ends, the writing operation ends at that stage.

To summarize, first, the memory 20 in the state with the lowest compression ratio is
If there is an input that exceeds the recordable time at the compression rate, the compression rate is increased sequentially and writing to the memory 20 is allowed until the corresponding recordable time is reached. do.

A flowchart of the above writing operation to the memory 20 is shown in FIG. T indicates the recordable time corresponding to the set compression rate; 1. indicates the total writing time to the memory 20.

Next, the audio data will be read from the memory 20.

In synchronization with the rotation of the disk 10, the memory control B circuit 14 outputs an address signal, and the memory 20 outputs audio data. The audio data is band-limited by a digital low pass filter (LPF) 21 as necessary. The output of the LPF 21 is converted into an analog signal by the D/A converter 22, and its clock is 2 fsc (approximately 7.16
MHz) and is supplied from the memory control circuit 14.

This clock frequency is 22.4KHz, 11.2KH
z, 320 times and 640 times of 5.6 KHz, respectively.
This corresponds to 1280 times.

The interpolation filter 24 extracts the time-axis compressed baseband component from the output of the D/A converter 22 and supplies it to the adder 26 . The power 7 off frequency of the interpolation filter 24 is approximately 3
It is MHz.

The adder 26 adds the flag and control code from the CPU 40, and its output is sent to the pre-emphasis circuit 2.
8. The signal is applied to the magnetic head 34 via the FM modulator 30 and the recording amplifier 32, and is recorded on the disk 10 - thus the audio signal is recorded.

When writing to the memory 20 takes less than 5 seconds in total, sampling in the A/D converter 18 is performed at approximately 22.4 kHz, and since the clock of the D/A converter 22 is approximately 7.16 MHz, 1 The compression ratio is /320. The input audio signal band-limited to approximately 10 KHz by the prefilter 16 is
At a time axis compression ratio of 1/320, the band is limited to approximately 3.2 KHz, which satisfies the sampling theorem.

Therefore, the interpolation filter 24 may have a simple pass characteristic.

When writing to the memory 20 exceeds 5 seconds in total and is less than 10 seconds, that is, sampling in the A/D converter 18 is performed at approximately 22.4 KHz for the first 5 seconds, and at approximately 11 KHz for the remaining time.
．． In the case of 21 KHz, the clock of the D/A converter 22 is approximately 7.16 MHz, so the first 5 seconds are 1/
The compression ratio is 320, and then the compression ratio is 1/640.

In order to record this audio data on one track, it is necessary to compress all data at a compression rate of 1/640. To do this, for the first 5 seconds, it is necessary to subsample every 2 points to make the sampling period about 11.2 KI (z), which is half of about 22.4 KHz.
However, for the first 5 seconds of data, the cutoff frequency of the prefilter 16 is about 10 KHz, so if the time axis is compressed to 1/640, it will be about 6.4 MI (corresponding to the band limit of z).

To prevent this, the band is limited by the LPF 44.

That is, the LPF 44 has an original sampling clock of about 2
4fsc (approximately 14°32
MHz) clock is supplied, and this clock realizes a low pass characteristic with a cutoff frequency of about 3 MHz. As a result, the sampling theorem is satisfied.

Subsampling of one point out of every two points for the first 5 seconds can be easily realized by address manipulation of the memory 20.

As a result of the above, the same audio data as compressed at the compression rate of 17640 from the beginning can be obtained.

When writing to the memory 20 exceeds 10 seconds in total, that is, the first 5 seconds are sampled at about 22.4 KHz, the next 5 seconds are sampled at about 11.2 KHz, and the remaining 5 seconds are sampled at about 11.2 KHz.
．． When sampled at 6KHz, D/A converter 2
Since the clock to 2 is approximately 7.16 MHz, this corresponds to a compression ratio of 1/320.1/640.1/1280, respectively. To record this audio data on one track,
It is necessary to compress everything with a compression ratio of 1/1280. To do this, subsampling is performed at one point every four points for the first five seconds, and one point every two points for the next five seconds, thereby increasing the effective sampling frequency to approximately 5.6 points.
kHz, but the cut-off frequency of the prefilter 16 is about 10 KHz and about 5 KHz, respectively.
KHz, which corresponds to approximately 12.8 MHz and approximately 6.4 MHz, respectively, when converted at a time axis compression rate of 171,280. Therefore, if subsampling is performed as is, aliasing distortion will occur. In order to prevent this, the memory control circuit 14 provides the LPF 21 with frequencies of 8fsc (about 28.64 MHz), which is 1280 times the sampling clock frequency of about 22.4 KHz during writing, which is about 11.2 KHz, and 4 fsc (about 14.2 KHz). 32 MHz) to make the LPF 21 have low bass characteristics with a cutoff frequency of about 3 MHz. LPF2
1, the sampling theorem is satisfied and sample sampling becomes possible.

In this way, the first 5 seconds are sampled at 1 in 4 points, and the next 5 seconds are sampled at 1 in 2 points, and the audio data is read from the memory 20. Compression rate from 1/128
The same time compressed data as compressed with 0 is obtained.

FIG. 4 shows an operational flowchart when reading data from the memory 20. However, the total reading time t from the memory 20 is converted into the writing time, and the successive reading time TI
The same is true.

It has been explained that the LPF 21 has a pass characteristic when the total time is less than 5 seconds, but of course it may be limited to about 3.2 MHz on the band side. In that case, the original sampling clock frequency is about 22.2 MHz. Approximately 7.16M which is 320 times that of 4KHz
Hz (2f sc) from the memory control circuit 42 to the LPF
21.

For example, the compression ratio is 1/320.1/640.1/128
In the case of consecutive numbers that are multiples of 2, such as 0, if the consecutive numbers are n, then in the present invention, the memory capacity is [1+ (n-1)/2)/2'', which is the originally required capacity of the memory 20. The same function can be achieved. 1/320.1
/640, 1/1280 is n-3, (1+
(3-1) /2) /23-Otori = 1
/ becomes 2, 1/320.1/640.1/128
If it is 0.1/2560, n=4, and the amount of memory required is (1+ (4-1)/2)/2'-1-5/16. The larger n is, the greater the effect of saving memory amount is. .

In the embodiment of FIG. 1, the sampling theorem is satisfied by the LPF 21, but by changing the frequency of the clock to the D/A converter 22, the same effect as the LPF 21 can be achieved. In this case, the LPF 21 is unnecessary. An example of this modification is shown in FIG. 2, and an operational flowchart for reading from the memory 20 is shown in FIG. Interpolation filter 2
The cutoff frequency of No. 4 is approximately 3.2 MHz.

When writing to the memory 20 takes less than 5 seconds in total, approximately 22.4 MI (clock of z is applied to the D/A converter 22,
It operates in the same way as in FIG.

If the total writing time to the memory 20 exceeds 5 seconds and is within 10 seconds, the D/A converter 22
Then, a clock of about 14.32 MHz is applied for the first 5 seconds, and a clock of about 7.16 MHz is applied for the rest. In synchronization with this clock, an address signal is applied to the memory 20 and data is read out.The baseband component of the signal output from the D/A converter 22 has a band of approximately 6.4 M for the first 5 seconds.
Hz, and the remaining bands differ by about 3°2 MHz, but the interpolation filter 24 creates a uniform band signal with a cutoff of about 3.2 MHz.

When writing to the memory 20 exceeds 10 seconds in total, the frequency is approximately 28.64 MHz for the first 5 seconds, and approximately 1 MHz for the next 5 seconds.
A clock of 4.32 MHz and a clock of approximately 7.16 MHz are applied to the D/A converter 22. When an address signal is applied to the memory 20 in synchronization with this clock and data is read out, the output of the memory 20 becomes a signal with a compression rate of 1/1280. The band of the baseband component of the output No. 48 of the D/A converter 22 is different as described above, but the interpolation filter 24 makes it a uniform band signal.

〔Effect of the invention〕

As can be easily understood from the above explanation, according to the present invention, there is no need to set the compression ratio in advance (the time compression ratio is automatically selected according to the time of the audio signal to be recorded). can do.

Moreover, 1. This can be achieved with the lowest memory capacity.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of one embodiment of the present invention, FIG. 2 is a block diagram of the configuration of another embodiment of the present invention, and FIGS.
The figure is an operation flowchart of the circuit in Figure 1, and Figure 5 is the operation flowchart of the circuit in Figure 2.
3 is an operation flowchart of the circuit shown in the figure. 10--Disk 12--CPU 14--Memory control circuit 15-Oscillation circuit 20-Old 34-Magnetic head Diagram 3 Procedure Neif original (method/self-produced) July 1986! 5th day

Claims (1)

[Claims] A circuit that can time-base compress an input signal at a plurality of compression ratios, comprising a memory means, an input signal initially written to the memory means at a sampling rate corresponding to a predetermined compression ratio, and a processing unit time at that compression ratio. memory writing means that sequentially changes the sampling rate to a sampling rate corresponding to a higher compression ratio when a signal corresponding to the number of minutes is written to the memory means; and a readout control that reads out the stored signal of the memory means as a signal of the desired compression ratio. A time compression circuit comprising means.