JPS63285087A - Catv decoder - Google Patents

Abstract

PURPOSE:To discriminate the presence of a scramble surely with simple circuit constitution by detecting a specific bit of a data pulse obtained from the demodulation of a carrier audio signal. CONSTITUTION:When a data pulse pd is sent from the sender side, that is, a scramble is applied to a CATV signal, the output of the most siginificant digit goes to 'high'. Thus, when the output is received, the output of the 1st inverter 341 goes to 'low', the output of a 2nd inverter 343 goes to 'high' and a MPU detects that the CATV signal received at present is scrambled. Then since an integration circuit 342 is provided between both inverters 341 and 343, even if a start pulse in the data pulse sent for each field is missing tentatively, the output of the 2nd inverter 343 keeps the high level. Thus, the detection is executed correctly.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial application field The present invention is directed to the reception of CATV (cable television) broadcasting.
This relates to a CATV decoder provided on the machine side.

(b) Conventional technology TV (Prevision) One of the paid CATV broadcasting systems that scrambles and transmits subtitles so that only specific subscribers can receive the broadcast is known as Japanese Patent Application Laid-Open No. 58-5167.
There is a system shown in Publication No. 8 (HO4N 7/16). That is, in this method, each horizontal and vertical blanking period in the carrier video signal that has been changed to AM is scrambled by compressing it by a predetermined level compared to the video signal δ period, and the horizontal blanking period is An FM wave type carrier audio signal is ASKR modulated using a timing pulse indicating the synchronization signal position of the sync signal and a data pulse indicating the compression ratio, type of TV program, etc. within the blanking period, and the ASK modulation modulated audio signal and the above The compressed video signal is transmitted to the receiving side.

Therefore, in order to descramble the carrier video signal scrambled as described above on the receiving side, that is, to expand the amplitude of the synchronous signal part, it is first necessary to determine whether or not the received carrier video signal is scrambled. be.

Conventionally, determination of the presence or absence of scrambling has been made by detecting the timing pulse from the ASK demodulated output of the carrier audio signal using a method such as PLL synchronous detection.

C) Problems to be Solved by the Invention However, with the above method, the V in the PLL circuit is reduced due to the influence of noise, continuous loss of timing pulses, etc.
If the oscillation frequency of the CO shifts, the timing pulse cannot be detected accurately, resulting in a malfunction in determining the presence or absence of scrambling. Moreover, there is also the disadvantage that the number of constituent circuits increases, leading to high costs.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to make it possible to reliably determine the presence or absence of a simple circuit with a simple circuit configuration.

(d) Means for Solving Problems In the present invention, the presence or absence of scrambling is determined by detecting a specific bit/bit of a data pulse reproduced from a carrier audio signal.

(e) Effects According to the above configuration, the presence or absence of scrambling is determined regardless of noise or missing timing pulses.

Kube Example An embodiment of the present invention shown in the drawings will be described below.

FIG. 4(a) shows the CATV received by this embodiment.
The figure (b) shows the carrier audio signal ASK-modulated with the above-mentioned timing pulse and data pulse, and the figure (c) shows the ASK-demodulated demodulated squid No. 18 signal. FIG. 3(d) shows an enlarged view of a part of the period of the demodulated output signal.

That is, the compression of the video signal (a) is performed using the horizontal and vertical blanking periods (HB) (
The timing pulses (Ps) are pulses with a width of 2 μsec, one pulse corresponding to each horizontal synchronizing pulse (Ps) position outside the VB period. In addition, the data pulse (Pd) is
20 μsec from the timing pulse (Pt, ) only for the 22nd to 38th H of each field.

It is possible to arrange one pulse at a time at a separate location, and when this pulse exists, it represents "1", and when it does not exist, it represents 401+. That is, this data pulse (Pd) is 17-bit data with each pulse (always present) in the 22nd H period and the 38th H period as a start bit and a stop bit, and the first 8
The bits (23rd to 30th H) are program data representing the program content of the TV program, and the latter 7 bits (31st to 37th H) are H.
This is scrambled data representing the compression ratio (dB) of the B period and the VB period.

Figure 2 shows the general configuration of the entire CATV decoder. (1) shows the CATV decoder input via a coaxial cable.
A multi-f[signal input terminal, (2) is a TV signal including a carrier video signal and a carrier audio signal from the multiplexed signal, and F which will be described later.
A signal separation circuit that separates the SK signal, (3) is the above TV
The RF amplifier that amplifies the signal, (4) converts its output signal to P
The first microphone receives the output of the first local oscillator (8) whose frequency is controlled by the LL control circuit (11) and converts it into an IF signal, (5) is an IF amplifier, and (6) converts the output signal to A.
FT circuit (second local oscillator (12) controlled by
9) is a second mixer that converts the output signal into a 3-channel TVfδ signal, (7) is a gain switch circuit that expands the amplitude of the HB period and VB period in the TV signal, and (10) is a These are output terminals and constitute a CATV converter (13).

On the other hand, (14) is an ASK demodulation circuit that performs ASK demodulation of the carrier audio signal extracted by the ink carrier type from among the three channels of TV signals obtained at the output end of the gain switch circuit (7), and (15) is the ASK demodulation circuit. Obtain the pulse train signal reproduced by
This is a descramble control circuit that controls the gain switching timing and gain increase amount (dB) of the gain switch circuit (7).

In addition, (16) is a local oscillator (
(17) is a mixer that converts the output signal to 10.7 MHz (No. 8), and (18) is an FSX detector that demodulates the output signal using FSK and reproduces so-called subscriber data indicating whether or not descrambling is possible for each subscriber. The circuit (19) is an MPU to which the subscriber data and data from the descrambling control circuit (15), or the tuning signal from the keyboard (20) or the remote control signal receiving circuit (21) are input; This MPU (19) controls the PLL circuit (11) in response to the channel selection signal.
At the same time, the HATA (13) is tuned to each CATV channel, and both of the above data are obtained to determine whether or not to descramble each program.

FIG. 1 shows details of the descramble control circuit (15), and (22) shows the ASK demodulation circuit (14).
(23) is a first gate circuit for allowing only the timing pulse (Pt) in the pulse train M to pass; 24) is the first counter that is reset by the output pulse of this gate circuit, (25) is the second gate circuit that supplies/cuts off the 4 MHz clock pulse to this counter, and (26) is the first counter (24). ) and the output pulses of the shaping circuit (22) to open and close the first and second gate circuits (23) and (25); <27) is a first counter (24);
a second counter, reset by the previous output C (occurred at count 240), counting said clock, (
28) is reset by the output of this second counter (occurs at count 40), and R3-FF (slip-FF) is set by the output C of the first counter (24).
flop).

Further, (29) is a VB period detection circuit that detects a vertical blanking (VB) period depending on the presence or absence of a timing pulse from the first gate circuit W (23), and (30) is a VB period detection circuit that detects a vertical blanking (VB) period depending on the presence or absence of a timing pulse from the first gate circuit W (23). The third period will be open
The gate circuit (31) is a D-FF for delaying the output of this gate circuit by a small amount and extracting it as a descrambled pulse, and this D-FF has 4 M)! To divide the frequency of the z clock, the output pulse of the frequency divider circuit (32) is given as a clock.

On the other hand, (32) is for extracting the data pulse (Pd) in the pulse train from the waveform shaping circuit (22);
Count output B (count 6) of the first counter (24)
4 to 128), the fourth gate circuit is opened by 〈33), which stores the extracted data pulse, and (34) receives the output of a specific bit of the data pulse in this register. A scrambling presence/absence discriminating circuit (35) for discriminating whether the scrambled CATV signal is scrambled or not decodes the data in the register, and also outputs the output of the discriminating circuit (34) and the second
This is a data decoding/control circuit that obtains subscriber data from the MPL (19) in the figure and a descrambling pulse from the D-FF (31) to perform ff1 (J go) of the gain switch circuit (7). .

FIG. 3 shows details of the scrambling presence/absence determination circuit (34) and data explanation/control circuit (35), which are essential parts of the present invention, together with their peripheral circuits. In the same figure, (3
31) is set by the data pulse (Pd) from the fourth gate circuit (32) in FIG.
R S -FF is reset by the timing pulse (Pt) from 23〉, (332) is a 17-bit I shift register whose Q output is the serial input, (33
3) is control 1 from the VB period detection circuit (29) in FIG.
Only during the 22H to 38H period opened by No. 8, the output of the second counter (27) in FIG. 1 is transferred to the shift register (
332) as a clock, and these constitute the data register <33) in FIG.

(351) is data into which scrambled data of the 17-bit data stored in the shift register (332) (excluding lower 7 bits indicating scramble information such as compression ratio) is input. Decoders (352) and (353) have first and second decode outputs (p+) (Dn) corresponding to each compression ratio of this decoder as D inputs, and a D− that uses a first timing signal ('r+), which will be described later, as a clock. FF, (354) and (355) use their respective Q outputs as D inputs, and the second timing color code (described later) is D -FF, (356) uses each Q as a clock.
The OR gates (357) and (358) whose output is manually operated are the first gate whose output and one input are each operated manually, and whose other input is the disk clamp pulse from D・FF (31) in Fig. 1. 2 Nant gates, and these constitute the decoding/control circuit (niece) in Fig. 1, and from its output terminals (359) (360) to the 1 IX
A gain switching function is given to the gain switch circuit (7) of J.

On the other hand, (341) is a first inverter that receives the output of the most significant digit of the shift register (332); (342)
is an integrating circuit consisting of a resistor and a capacitor, and (343) is a second inverter that receives the integrated output as input, and these constitute a scrambling/non-scramble determining circuit (34).The output thereof is connected to a terminal (344). is applied to M P U (19) in FIG.
It is inverted by the inverter <345) and the NOR gate (346
), and the output of this NOR gate is given as each reset signal of D −F F (354>(355)). At that time, the NOR gate (3
Descramble control No. 7 from the MPU (19) is inputted as the other input of 46).

One embodiment of the present invention is configured as described above, and the following is as follows.
The operation will be explained with reference to the time chart of FIG.

First, in Figure 1, when the power is turned on and channel +y
At the time of J exchange, the first counter (24) goes to the initial position (not shown).
Therefore, in this initial state, the gate control circuit (26)
The first gate circuit (23) is opened by the output of
The gate circuit (25) is closed.

When the first timing pulse (Pt) in the pulse train signal (FIG. 5(a) (corresponding to FIG. 4(c)) arrives at the waveform shaping circuit (22) from the rejected state, the pulse after waveform shaping is through the first gate circuit (23) and the first counter (
24). At the same time, the waveform-shaped timing pulse (Pt) sets the gate control circuit (26), thereby opening the second gate circuit (25). Therefore, the first counter (24) counts up, and when the first counter (24) starts counting, the gate control circuit (26) responds to the count output A which becomes high immediately after that. First gate circuit (23
) is closed, so the counter (
24) will not be reset again.

In this way, the first counter (24) clocks 64
From the time when 128 pieces are counted until the time when 128 pieces are counted, the count output B (Fig. 5 (b)) becomes high, and this output causes the fourth gate circuit (36) to control the first counter (
24) Open for 16-32 μSaC after setting the glue.

The first counter (24) continues to count up after that, and when it counts 240 clocks, that is, 60 μsec from the reset time, later, when the count output C becomes high, the gate control circuit (26) is set. , thereby opening the first gate circuit (23) and closing the second gate circuit (25>) to return to the initial state.
The count output C resets the second counter (27).
At the same time, set RS -F F (28). After that, the counter (27) increases by 4 from the time of reset.
When 40 MHz clocks are counted, that is 10
μ! lec, later generates an output (d), and at that output RS
-F Reset F (28). Since such an operation is repeated every time the timing pulse (Pt) in the pulse train signal (a) arrives, the RS -F
From F(28), a pulse train signal having a width of 10 μsec as shown in (E) of the same figure is obtained.

On the other hand, the third gate circuit (30) includes a VB period detection circuit (
29) is forced to become C and C during the VB period, and is opened outside the VB period to output the pulse train signal (E).
is derived as is. Then, this third gate circuit (3
The output of 0) is taken out as a descrambled pulse (to) after a short delay of ￥f at D -F F(31),
It is given to the data decoding/1m control circuit (35).

On the other hand, as is clear from the above theory, the fourth gate circuit (32) operates 16 times after the falling edge of each timing pulse (Pt).
Since the gate is open for ~32 μsec, each data pulse (Pd) in the pulse train signal (a) is sent to the data register (33) through this gate. Then, this data pulse (Pd) is RS − in the data register (33).
F The shift register (332) is filled with the output pulse (D) (fifth section (c)) of the Z2 counter (27) (Fig. 11). At this time, the fifth data circuit (333) is connected to the data 22 to 22 of each field as described above.
Since it is only open during the 38H period, the 17B.
When the storage of the /t data for each field in the shift register (332) is completed, the most significant digit of this register (332) corresponds to the start bit.

Therefore, when the data pulse (Pd) is sent from the transmitting side, that is, when the CATV signal is scrambled, the output of the most significant digit is 4 high.
become. Therefore, when this output is input, the output of the first inverter (341) becomes "low" and the output of the second inverter (343) becomes "high", thereby causing the MPU (19) shown in FIG. ) detects that the cAiv signal currently being received is scrambled. At that time, an integrating circuit (
342), even if the start pulse in the data pulses sent for every field 2 is temporarily missing, the output of the second inverter (343) is “
The signal is held high, so that the above detection operation is performed correctly.

On the other hand, scrambled data among the data stored in the shift register (332) is sent to the decoder (351).
is deciphered. Here, the scramble data represents whether the amplitude compression ratio for the HB and VB periods is 6 dB or 10 dB, and also represents whether the compression ratio is changed from the Hth time after the end of the VB period. Therefore, for example, if the scramble data represents a compression ratio of 10 dB, the first
The dehood output (D,) is correspondingly "high" and the second decode output (D,) is "low", and the scrambled data indicating the 10 dB is decoded from the decoder <351>. The first timing signal (T,) becomes "high" only immediately after the decoding is performed, and at this timing, the first and second decode outputs (Dl) (D) are output from the D-FF (35
2) When the predetermined H-th period indicated by the scramble data is reached, the second timing signal (T,) from the decoder <351) becomes "high", and at this timing, Said D-FF (352) (
Each Q output of 353) is connected to the subsequent stage D
(355) respectively. At this time, the output of the second inverter (343) of the discrimination circuit (34) is "high" as described above, and its inverted output by the third inverter (345) is given as one input of the NOR gate (346). and the other input is the MPU shown in Figure 2.
(19) Gara's control number 16 is leaked. This control signal is based on the subscriber data described above, and is based on the subscriber data currently being received.
It becomes "low" only when the ATV signal should be "one receiver allowed" for the person in question. Therefore, when this control signal is "low", the output of the NOR gate (346) becomes "high", which causes ED -F F (35
4) Since the reset state of (355) is released,
The above-mentioned latching operation to D-FF (354) (355) is performed. Further, in order to generate the second timing signal (T, ), the output of the second counter (27) in FIG. 1 is also provided to the decoder (351).

In this way, the output indicating the 10 dB compression state is D・F
F (354) (355) are latched, and when their Q outputs become "high" and "low" respectively, the inputs of each one of the Nant gates (357) and (358) both become "high" 9, so This Nant gate <357) (35
The output terminals (359, 360) of 8) become "low". When both terminals (359, 360) are "low", the gain switch circuit (2g1) of
7) increases the amplification gain by 10 dB only during the high period and performs descrambling for the HB and VB periods.

Furthermore, when the aforementioned scrambled data represents a compression ratio of 6 dB, the first and second decode outputs (D,) (D
I)'s high and low are reversed, and Nandoge-1-(35
Since only the output terminal (359> of 7) becomes “low”,
Descrambling is performed by increasing the amplification gain by 6 dB. Further, the compression ratio represented by the scrambled data is 1
The same is true when switching from 0 dB to 6 dB, or conversely from 6 dB to 10 dB.

On the other hand, when the CATV signal is not scrambled, the data pulse (Pd) is not sent from the sender, so the output of the highest and lowest digits of the shift register (332) becomes "low", thereby causing the third Since the output of the inverter (345) becomes "high", the output of the NOR gate (346) is forced to become "low".

Therefore, D - F F (354) (355) is held in the reset state, which causes the Nant gate (35
7) Since each output terminal (359) (360) of (358) is always “high”, the gain switch circuit (7)
) does not perform any gain switching, so the CATV signal is normally received.

(G) Effects of the Invention As described above, according to the CATV datar of the present invention, the carrier audio signal is modulated and sent out, and the specific pitch of the data pulse indicating the content of scrambling with respect to the video signal! By detecting the presence or absence of scrambling, it is possible to reliably detect the presence or absence of scrambling with a very simple circuit configuration without any malfunctions, thereby making it possible to achieve accurate descramble operation and greatly contributing to lower costs.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the details of the descrambling control circuit in the CATV decoder according to the present invention, FIG. 2 is a block diagram showing a schematic configuration of the entire CATV decoder, and FIG. 3 is the descrambling control circuit described above. Bookmark diagram showing the internal configuration of the four circuits for determining the presence or absence of a scram in the circuit, No. 4
The figure is a No. 8 waveform diagram to explain scrambling.
The figure is an operation time chart. (15) : Descramble control circuit, <34) Niscrumple presence/absence determination circuit.

Claims (2)

[Claims] (1) A CATV that receives CATV broadcasting in which a video signal is scrambled and a carrier audio signal is modulated with data pulses indicating the contents of the scramble, etc.
CATV characterized in that the presence or absence of scrambling is determined in the decoder by detecting a specific bit of a data pulse obtained by demodulating the carrier audio signal.
decoder. (2) The CATV decoder according to claim 1, wherein the specific bit is a start bit of the data pulse.