JPS6328320B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a word speech recognition device based on a pattern matching method, and provides a new matching method for speech signals. A word speech recognition system based on the principle of pattern matching usually includes a speech input section 1, a feature extraction section 2, a recognition processing section 3, a registered pattern memory 4, and an input pattern memory 5 as shown in FIG. It has two operating modes: registration mode and recognition mode. In the registration mode, the word sounds to be recognized are registered in advance, and the features of the sound extracted by the feature extraction unit 2 from the registered sound signal which is the output of the sound input unit 1 including the microphone are extracted as a time series pattern. This pattern is stored in a registered pattern memory (or also referred to as a standard pattern memory) 4.
In the recognition mode, after a voice feature pattern similarly extracted from the input voice signal is stored in the input pattern memory 5, the degree of similarity between this input pattern and the registered pattern stored in the registered pattern memory 4 is recognized. The registered pattern with the maximum degree of similarity calculated by the processing unit 3 is fixed as the one that matches the input voice, and is outputted accordingly. The configuration of the recognition processing section 3, registered pattern memory 4, and input pattern memory 5 shown in FIG. 1 having such functions is realized by a computer system centered on a central processing unit (CPU). It is well known that physical quantities such as a frequency spectrum, a correlation function, the number of zero crossings, and an α parameter are used as a method for extracting the phonological features of speech from a speech waveform. Among these, the method of extracting the frequency spectrum of the voice using a large number of bandpass filters is becoming more and more widely used because it has a relatively simple configuration and can obtain a high recognition rate. FIG. 2 shows a specific example of a speech recognition device that analyzes the frequency spectrum using a filter. The audio input section 1 maintains the microphone 11, microphone amplifier 12, and the level of the input audio signal substantially constant regardless of the strength of the input audio.
It consists of AGC circuit 13. Connect to the output of this input section 1. M bandpass filters (hereinafter referred to as BPF)
) 21-1, 21-2, ... 21-M, and a low-pass filter (hereinafter abbreviated as LPF) 22-1, which is connected in series with each BPF and detects each output envelope.
22-2, . . . 22-M constitute a feature extraction unit 2, which performs frequency analysis on the voice band signal. Each filter component of the audio signal that has passed through the audio input section 1 has an appropriate time period (10 to 20 msec in most cases)
are sequentially sampled by the multiplexer 23. That is, LPF22-1, 22-2,...22-
The audio spectrum signal obtained in parallel at the output end of M becomes a serial signal train, which is sequentially converted into a digital code by an analog-to-digital converter 24 (hereinafter abbreviated as A-D converter), and then sent to the CPU.
The data is once taken into the buffer memory 33 via the I/O port 32 controlled by the I/O port 31 . This amount of data is, for example, if the number of filters M is 8, the maximum audio input time is 1.6 seconds, the sampling period is 10 msec, and A
When the number of bits of the -D converter 24 is 8, the maximum amount of data to be taken in is 1.6/0.01×8×8=10240 bits=1.28 KB (B: byte). Now, even if the audio signal is from the same speaker in the same language, it is normal for the time axis and signal amplitude to fluctuate each time it is uttered, and some kind of normalization is required for each. For normalization of amplitude
As mentioned above, the AGC circuit 13 is often used, but regarding the time axis, a method as shown in FIG. 3 is generally used in which the time from the start to the end of a word is divided equally. The audio detection circuit 25 detects the beginning and end of the audio signal based on data such as the level, frequency distribution, and number of zero crossings of the input signal. In Figure 3, when the sampling point number at the beginning of the input audio signal is 1 and the sampling point number at the end is l, find the integer closest to l/N (N is an integer) (this is set as n), and then calculate the input sampling point number. The time axis can be normalized by extracting N pieces of data every n pieces including the start end and rearranging them (FIG. 3b). For example, if N=32, in this case N×8×8=2048bits=256B data is stored in the registered pattern memory 40 in the registration mode and in the input pattern memory 50 in the recognition mode. . These memories are usually RAM, and the address of the registered pattern memory 40 stores the CPU program.
It is specified by the ROM 34 and the input control section 35. The number of registered patterns is determined by the specifications of the speech recognition system, that is, the number of registered speakers and the number of words that can be registered. Recognition processing in the recognition mode is similarly performed by pattern matching the contents of the input pattern memory 50, which stores the data of N sample points obtained from the data input to the buffer memory 33, and the contents of the registered pattern. It will be done.
Although various methods have been proposed for calculating the distance between the input pattern and the registered pattern, here, for convenience of explanation, the simplest method, the Thiebishev distance, will be explained. 8 registration patterns for certain word sounds
The Thievishev distance D between the time series [fij ^(R) ] of the filters [fij (R)] (i: filter numbers 1 to 8, j: sample points 1 to N) and the same filter time series [fij] of the input audio pattern is given by the following formula. defined. D= _N 〓 ^j=1 ₈ 〓 ⁱ⁼¹ ｜fij−fij ^(R) ｜ ...(1) That is, this is the input pattern fij and the registered pattern fij ^(R)
is the sum of the absolute values of the differences between each corresponding data,
The input pattern is considered to match the registered pattern for which the minimum value is obtained among the Tievisiev distances obtained for each registered pattern. For convenience of explanation, a memory area for temporarily storing these calculation results is shown as a recognition processing memory 36. In the conventional speech recognition system based on the principle of pattern matching explained above, the degree of similarity is calculated by the sum of the distance differences between the input pattern and the registered pattern at each corresponding time point, and the circuit configuration is simple. However, there are many calculation errors, and it is difficult to say that sufficient recognition performance can be obtained. In addition to such recognition processing, the present invention performs recognition processing with even higher accuracy by grasping the shape of the waveform as the peak position and number of peaks, and referring to this as auxiliary data when calculating the degree of similarity. FIG. 4 is a block diagram showing the configuration of the device of the present invention, which differs from the conventional device shown in FIG. 2 in that it has an appropriate cutoff frequency between the input section 1 and the multiplexer 23, A bypass path based on the LPF 26 that detects the line (envelope) is provided, and a peak detection circuit 27 that detects the maximum value of the audio is inserted between the A-D converter 24 and the I/O port 32. It is in. Note that most of the components in Figure 4 are the same as those in Figure 2, so
A detailed explanation of these points will be omitted. This peak detection circuit 27 detects the peak of the input audio signal waveform and transmits the detection signal to the CPU 31 via the I/O port 32.
From now on, the sampling point number of each peak position is stored in the buffer register 33 along with each filter output string. Therefore, in the embodiment of the present invention, the storage capacity of the buffer register is increased by an appropriate amount compared to the previously calculated case of the conventional device shown in FIG. 2 (1.28 KB). When all sampling data and peak positions (sampling point numbers) have been stored in the buffer register 33, the CPU 31 selects the starting and ending points of the audio signal from among all the sampling data to normalize the time axis.
At the same time as extracting N pieces of data to be divided equally, the normalized peak position obtained by dividing the sampling point number of each peak position by the terminal sampling point number and its number together with the N pieces of data. The input pattern memory 5
0 or each stored in the corresponding part of the registered pattern memory 40. Circuit 27 for detecting the peak position of the input audio signal
A specific example is shown in FIG. The signal envelope data detected by LPF26 is sent to multiplexer 2.
3. It is input as a digital code to the latch circuit 61 via the A-D converter 24 and is held there. In the case shown in the figure, the output of the A-D converter 24 is 8-bit parallel, and the latch circuit 61 is connected to the multiplexer 23.
The output of the A-D converter 24 is latched in synchronization with an appropriate frequency division of the timing pulse that samples the output of the LPF 26, and then the latch 62 with the same storage capacity cascades the held contents with an appropriate time difference.
Transfer to. Typically, analog multiplexers respond to clock pulses and sequentially switch inputs to their output terminals in accordance with a binary code applied at the same time as the clock pulse to select and designate one of a plurality of input terminals. The present invention also adopts this format, and the CPU 3
1 through I/O port 32. The sampling clock pulse 63 of the analog multiplexer 23 (which is the same as the convert command pulse of the A-D converter 24) and the CPU 3
1 to the input designation code 64 of the analog multiplexer 23 given through the I/O port 32, the output of the OR gate 66 is divided by K (K is 1
According to the output of the frequency divider circuit 67, which is constant at an appropriate integer above, the first latch 61 is then set to A-D.
The digital code conversion of the output of the LPF 26 applied to the output of the converter 24 is stored and held. Furthermore, in response to the output of a logical sum (AND) gate 69, which will be described later, of a circuit 68 that delays the output of the K frequency divider circuit by an appropriate time (T _D ), the second latch 62 delays the output of the first latch 6.
The contents held in 1 are stored and held in the same manner. Here, if the period of the clock pulse is (T _C ) and sampling is performed at equal time intervals, and the number of band division filters is (M+1), the sampling period (T _S ) is (M+1) T _C . Since the output cycle of the K frequency divider circuit 67 is KT _S =K(M+1)T _C , the delay time (T _D ) of the delay circuit 68 is naturally O
<T _D <K(M+1)T _C . As mentioned above, the sampling period ( _TS ) is specifically selected to be 10 to 20 msec. Note that the detection circuit 26 for detecting the amplitude envelope of the waveform is a band division filter 21-
1, 21-2,..., 21-M and the LPFs 22-1, 22-2,..., 22-M cascaded to each other in a relatively low frequency range can be substituted, and in this case, they are omitted. (M+1) in the above explanation
becomes M. Now, according to this configuration, the first latch 61
latches the data at the Jth sampling point (J is a multiple of K), the second latch 62 holds the (J-K)th sampling data. The 8-bit data of the latch 62 is converted into two's complement representation through the complement circuit 70, and then its upper L bits (L is an integer, 1≦L≦8)
An addition circuit 71 calculates the addition of the L bits and the upper L bits of the first latch 61. Complement circuit 7
In other words, the adder circuit 71 calculates the difference between the upper L bits of the stored contents of the first latch 61 and the second latch 62, and the positive or negative of the result is the most significant digit (MSB) of the adder circuit 71. 72.
When this MSB72 is 0, the result of subtraction is positive or 0.
It can be seen that the sample value sequence is increasing or there is no change, and when the MSB 72 is 1, the result of subtraction is negative, indicating that the sample value sequence is decreasing. The contents of MSB 72 are transferred and stored in 1-bit memory 74 in synchronization with latch signal 73 of second latch 62, and an exclusive OR between this and MSB 72 is calculated by NOR gate 75. With this configuration, when a change occurs in the difference between the sampling data sequentially input to the first and second latch circuits 61 and 62, the gate 75
outputs logic "1", and at this time the adder circuit 71
If the MSB72 of is logic "1", the change in the difference in the sampling data string is from positive to negative, that is, there is a maximum point, and the output AND which is the logical sum of these
This can be known from the output of gate 76. Further, if the output of the adder circuit 71 is 0 (zero), the OR gate 77 which is a coincidence circuit detects this and outputs the output of the latch pulse circuit 73 to the latches 62 and 74 via the inverter 78 and the AND gate 69. and stop data transfer to each. This makes it possible to avoid misjudging a temporary flat part of the waveform as an extreme value. Incidentally, a signal waveform diagram at each location in FIG. 5 is shown in FIG. 6. In this FIG. 6, A is the sampling clock pulse 63, and B is the OR gate 66.
Output, C is the frequency divider circuit 67 output, D is the complement circuit 70
In addition, E indicates the subtraction timing by the adder circuit 71, E indicates the delayed output of the delay circuit 68, and F indicates the output from the output AND gate 76, respectively. In the above configuration, performing sampling every K by the K frequency divider circuit 67 and omitting the lower (8-L) bits in the difference calculation of the sampling data both reduce the small peaks of the waveform. This is to avoid detection of this and ignore it, and the LPF obtained by selecting the cutoff frequency between 50 and 100Hz.
In combination with the effect of No. 26, this is effective for grasping the approximate shape of the waveform. It goes without saying that the waveform peak position detection circuit described above can be realized not only by such a configuration, but also by, for example, an appropriately programmed CPU system. Now, the peak position of the waveform detected in this way and its number are stored as audio data in the input pattern memory 50 or the registered pattern memory 40, but these data are used in the similarity judgment which is the recognition process calculation. The following describes how to do this. One method is to first perform distance calculations using sampling data as in the past, select some of the registered patterns with high similarity in order, and select patterns with the same number of peaks among them. When it is not possible to specify the peak interval, this method uses the sum of the absolute values of the differences between the corresponding peak intervals. Alternatively, there is a method in which registered patterns are limited to a certain extent in advance by comparing the number of peaks and peak intervals, and similarity is determined by distance calculation as in the conventional method. Although the merits and demerits of these methods cannot be definitively determined, experimental results show that the former method A has a higher recognition rate than the latter method B, as shown in the table below. However, the total calculation time is shorter in the latter case, so the selection of these methods is left to comprehensive judgment in system design. In addition, the experimental method in this table is as follows: (1) 5 adult males, number of trials 4 times for each word sound, (2) Number of registered words: 32 words, (3) Same sound tape for both methods A and B. Input depending on the recorder.

[Table] As explained above, the present invention detects the peak position and number of audio waveforms, calculates the similarity using sampling data, and uses information regarding these waveform peaks as judgment data for pattern recognition. It is possible to provide an extremely practical method that makes it possible to improve the recognition performance of the entire system.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the outline of a word speech recognition device based on the pattern matching principle, Fig. 2 is a block diagram showing its internal configuration, Fig. 3 a and b are waveform diagrams of speech signals, and Fig. 4 is FIG. 5 is a block diagram showing the configuration of the apparatus of the present invention, FIG. 5 is a block diagram showing the configuration of its main parts, and FIG. 6 is a timing chart for explaining the operation, where 1 is an input section and 2 is a feature extraction section. , 3 is a recognition processing unit, 4 is a registered pattern memory,
Reference numeral 5 indicates an input pattern memory, and reference numeral 27 indicates a peak detection circuit.

Claims (1)

[Claims] 1. Audio input means for converting audio into electrical signals;
a feature extraction means for extracting features of an input audio waveform;
a sampling means; a conversion means for converting the sampled audio characteristics into a digital code;
Start/end detection means for detecting the start/end of the audio signal;
An amplitude detection means for detecting the amplitude of the audio signal, a difference detection means for detecting a difference between sampling values by the sampling means of the amplitude detection means, and a change detection means for detecting a change in sign of the difference; A peak detecting means that responds to the differential code detecting means, a means for calculating and counting the number of peaks and peak intervals from the output of the peak detecting means, and a register that stores voice characteristics and peak information input in advance for registration. a pattern storage means, an input pattern storage means that stores the characteristics and peak information of the input voice each time a voice is input, and calculates the degree of similarity between the contents of these registered pattern storage means and the contents of the input pattern storage means. A word speech recognition device using a pattern matching method, comprising: recognition processing means that performs pattern recognition by comparing both peak information.