JPS63272239A - Data link control circuit - Google Patents

Abstract

PURPOSE:To quicken the transmission time of a frame addressed to a terminal equipment on other bus type LAN by storing all terminal addresses in advance onto a bus type LAN and applying collation processing to all terminal addresses and destination addresses of data in parallel so as to attain the real time processing. CONSTITUTION:The titled control circuit is connected directly to a bus type LAN (local area network) and is provided with a destination address extraction section extracting a destination address of a received data and with a table storing in advance all terminal addresses allocated in the bus type LAN. Then a string search device section 6 generates a match signal when the extracted destination address and all the terminal addresses are subjected to real time collation in parallel and at least one of the stored terminal address is coincident with the destination address. Moreover, a reception buffer processing the received data and storing it tentatively is provided, a data link control section 3 interrupts the reception processing in response to the production of the match signal and applies the transmission processing to other bus type LAN to the stored data in the reception buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data link 911110 circuit, and more particularly to a data link 911110 circuit.
The present invention relates to a data link flIIIlt1 circuit having a bridge configuration that connects N (local area networks) to each other.

11, there is a bridge method as one of the typical phase n connection methods for a LAN, and FIG. 2 shows the system configuration thereof. As an example of an N-phase n connection method using a bridge, C
3MA/CD (Carrier Sense Media Access/)
(Rigicon Detect) bus type LANs 21 and 22 and a token passing type ring type LAN 23 are used.

Bridge-configured nodes 24 and 25 perform various controls between these 1-ANs, and data transmission from the terminal 26 belonging to one bus-type LAN 21 to the other bus-type LAN 22 is performed via the ring-type LAN 23. As if it were <K
There is. Note that 27 indicates a terminal in the other bus type AN 22.

The major functions of the bridges 24 and 25 are a filtering function that determines whether or not to pass data frames from the bus-type LAN, and a frame that conforms to the ring-type LAN format from the data frames that are passed. There is an address mapping function to do this.

In order to implement the filtering function in the bridge, the data link control circuit of the bridge checks the destination address of the received frame and determines whether the received frame is addressed to the terminal on the bus-type LAN that received it. If the frame is not addressed to the terminal on the bus-type LAN that received it, the frame is transmitted to another bus-type LAN (not shown), and if it is addressed to the terminal on the bus-type LAN that received it,
A function is required to discard the frame and interrupt reception processing. In order to realize this function, an i-pull consisting of the terminal addresses of all the terminals connected to either or both of the bus-type LANs and means for searching for the i-pull are required.

Conventionally, such tables and search means have consisted of configuring tables in general-purpose storage elements and sequentially searching and collating them with a general-purpose microcomputer using search algorithms such as linear search, hash search, and binary search. It is taken. Therefore, the configuration of a conventional data link control circuit consists of a channel access section, a carrier detection signal, and received data.

Inputs receive zero check, collision signal, and transmit clock, outputs transmit data and transmit enable signal to channel access unit, generates and removes preamble for frame synchronization, sets frame boundaries, and identifies and means for detecting physical channel transmission errors, channel assignment and collision processing based on the C3MA/CD medium access method, and a microcomputer system for executing an algorithm for searching and collating a table consisting of terminal addresses. It has become.

In the configuration of the conventional data link &+ control circuit described above, after receiving a frame, the microcomputer sequentially searches the table before transferring it to the transmitter to another bus-type LAN or interrupting the reception process regarding the frame. , time is required for verification, and when transmitting a frame to a terminal on the other bus type IAN, this time is required for transmission IIi! ! The disadvantage is that the spread increases.

Purpose of the Invention The purpose of the present invention is to perform inspection and verification of destination addresses in real time in a short time, thereby reducing the time required to send a frame to a terminal on another bus-type LAN. The purpose is to provide a data link control circuit.

Structure of the Invention According to the present invention, when the terminal is directly connected to the bus-type LAN ([1-Cal Area Network) of -, and the received data is addressed to a terminal on the bus-type LAN of -, the data packet is transmitted. Without processing, the above-mentioned - bus type,
A data link control circuit that performs a filtering function to transmit and process the data packet if it is not addressed to a terminal on the AN, and includes a destination address extractor that extracts the destination address of the received data; Bus type LAN
has a table in which all the terminal addresses stored in the terminal address are stored in advance, and the destination address and all the terminal addresses are collated in parallel in real time to match at least one of the stored terminal addresses and the destination address. a string search device section that generates a match signal when the match signal matches, and a receive buffer that receives and processes the received data and temporarily stores it, and interrupts the receive process in response to the generation of the match signal. There is obtained a data link control circuit characterized in that it includes a data link control section which performs a process of transmitting data stored in the reception buffer to another bus type LAN if no signal is generated.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of a data link control circuit according to an embodiment of the present invention, and corresponds to nodes 24 and 25 in FIG. The channel access unit 2 is a C8MA/CD bus type L
A transceiver that is directly connected to AN1, the bridge side is connected via an isolation transformer, and is composed of a bus-type LAN transmission driver, reception receiver, collision detection circuit, transmission monitoring timer, etc., and the transceiver, link control unit 3, and synchronization. Pill-detector 4 and destination address (DA)
The transceiver side signal and data link controller unit 3. Synchronization bit detection section 4. It is composed of a serial interface section that performs signal level conversion with the DA extraction section side signal, decoding of Manchester encoded received data of transmission data into NRZ code, and carrier detection.

This channel access section 2 receives transmission data and a transmission enable signal from a data link controller section 3, and sends a carrier detection signal, reception data, reception clock, collision signal, and transmission clock to the data link controller section 3. It outputs a carrier detection signal, reception data, and reception clock to the synchronization bit detection section 4, and outputs reception data and reception clock to the DA oil extractor 5.

The data link controller section 3 is the channel access section 2
From the carrier detection signal, received data, received clock,!
The input signal and the transmission clock are input, the match signal is input from the string search device section 6, the transmission data and transmission enable signal are output to the channel access section 2, and the transmission enable signal is output to the synchronization bit detection section 4. Output.

This data link controller 5 section 3 generates and removes preambles for frame synchronization, sets frame boundaries, identifies and detects physical channel transmission errors, and performs C8MA.
/CD Performs channel allocation and collision processing based on the medium access method.

The synchronization bit detection unit 4 receives the carrier detection signal, received data, and reception clock from the channel access unit 2, receives the transmission enable signal from the link control unit 3, and performs OA.
A synchronization bit detection signal is output to the extraction unit 5. When this data link control circuit is not performing a transmission operation, this synchronization bit detection unit 4 detects the synchronization bit following the preamble on the received data when a carrier detection signal is input, and outputs a synchronization bit detection signal. do.

The DA oil extractor 5 receives data received from the channel access unit 2,
Indicates that the reception clock is input, the synchronization bit detection signal is input from the synchronization bit detection section 4, and the 16-pit parallel OAA force line and DA are output to the DAA force line to the string serve device section 6. Outputs a control signal. Further, following the synchronization bit on the received data, the 48-pit OA is latched into a 16-bit latch circuit three times, and the three times are outputted to the DAA line, and a DΔ read control signal is output.

String search device part 6 is DA oil extraction 5 to 16
A bit parallel OAA force line and an OA read control signal are input, and a match signal line is output to the data link controller section 3. This string search device section 6 stores the 48-bit long terminal addresses A1-80 of all the terminals connected to the bus FS1!1-ΔN1, and performs DΔ read control following the same rg+bit detection signal. The 16-bit length DA ratio output is wrapped three times according to the signal, and this is used as the 48-bit length destination address, and all the stored terminal addresses A1-80 are checked in parallel at the same time. If it matches any one of the terminal addresses, a map signal is output to the match signal line. For details of the string search device section 6,
Patent application No. 167213 filed by the applicant
Details are disclosed in the issue.

When one of the terminals accommodated in the C3MA/CD bus type LAN 1 transmits a preamble and the following frame onto the bus 1, the channel access FII 2 detects a carrier via the bus 1 and sends the carrier detection signal to the data link controller section 3. And output to the same 1111 bit detection section 4. Next, the channel access unit 2 receives the signal on the bus 1 from the N
Preamble decoded into RZ code and subsequent I
I bit is output onto the reception data line, and at the same time, a 1QHIlz clock is extracted from the signal on bus 1 and outputted onto the reception clock line.

When the data link controller 9 section 3 receives a carrier detection signal while it is not in the transmission operation, it starts the reception operation, samples the signal on the reception data line using the reception clock, and detects the preamble and the following synchronization bit. From then on, the received data signal is input to the receive buffer in the data link control section 3, regardless of the DA of that frame, until there is no more carrier detection signal.

When the carrier detection signal is input while the transmission enable signal is not input, the synchronization bit detection unit 4 starts a synchronization bit detection operation, samples the signal on the reception data line using the reception clock, and detects the preamble and the following synchronization bit. is detected and outputs a synchronous bit detection signal to the synchronous bit detection signal line.

The OA oil extractor 5 is initialized by this synchronization bit detection signal, and in synchronization with the reception clock, inputs the received data to a serial input 16-bit parallel conversion circuit whose output line is the OA output line. The OA oil extractor 5 outputs a DA read control signal to the OA read control signal line when 16 bits of received data are input and outputted to the 16 bit DA output line. By repeating this three times, the 48-bit DA following the synchronization bit is stored in the string search device section 6.
Output to.

The string search device section 6 is initialized by the synchronization bit detection signal from the synchronization bit detection section 4, and introduces the 16-bit DA output from the DA extraction section 5 three times in synchronization with the OA read i and II control signals. The string search device section 6 simultaneously compares the 48-bit DA thus inputted with all stored terminal addresses A1 to An. If DA matches one of the stored terminal addresses, a match signal is output; if DA does not match any of the stored terminal addresses, no match signal is output. If a match signal is input to the data link controller section 3, the data link controller section 3 assumes that the frame is addressed to a terminal accommodated on the bus 1, and interrupts the receiving operation. If the match signal is not input, the data link controller section 3 assumes that the frame needs to be sent to the other terminal on the bus side, and sends the received data to the data link controller section 3 until the carrier detection signal is no longer present. Input into receive buffer.

When the carrier detection signal disappears, the C of the received frame
RC (cyclic redundancy check)
k) Checking for errors. Check the frame length,
If both results are acceptable and the transmit buffer in the data link controller section on the other bus side is empty, the frame is transferred from the receive buffer in the data link controller section 3 to the send buffer. When either or both of the CRC error check and frame length check of the frame received are negative,
Or is it the transmission buffer in the data link controller section on the other bus side? When there is no space in the frame, the received frame is discarded and the reception process ends.

When a frame whose destination address is a broadcast address is received from the bus 1, the terminal address and the broadcast address never match, so the string search device section 6 does not output a match signal.

Therefore, if the format of the received frame is complete, no transmission error is detected, and the transmission buffer in the data link controller on the other bus side is empty, the frame is transmitted to the other bus side.

When the data link controller unit 3 is neither transmitting nor receiving, if the data link controller unit on the other bus side transfers a frame to the transmit buffer 1 in the data link controller unit 3, the data link controller unit 3 transmits the frame. Start operation. And C8MA/C
DW, a carrier detection signal is input from the channel access unit 2 according to the physical access system, but if there is no carrier detection signal, a transmission enable signal is output, followed by transmission data, and at the same time a collision signal is monitored. do.

The Bouyanel access unit 2 Manchester-encodes the transmission data inputted through NRZr:I6 and outputs the encoded data to the bus 1. Regarding the transmission operation, the data link controller section 3
performs all the transmission data link management in accordance with the C3M/CD specifications, and the synchronization bit detection 1154 stops its operation in response to the transmission enable signal, so that the DA oil extraction 5 and string search device section 6 are also not initialized and are in a stopped state.

Effects of the Invention As described above, according to the present invention, all terminal addresses on one bus-type LAN are stored in advance for destination address search and verification, and all terminal addresses and data destination addresses are stored in advance. Since the processing is performed in parallel, real-time processing is possible, and therefore, after receiving a data frame, data transfer processing to the data link control circuit of the other bus type LAN or reception regarding that frame is performed. This has the advantage of not requiring any time to sequentially search and collate the table in which terminal addresses are stored before interrupting the process. Therefore, when transmitting a data frame addressed to a terminal on the other bus-type LAN, the propagation delay does not increase accordingly, and there is an advantage that the data packet can be transferred to the other bus-type LAN with minimum delay.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a system diagram of a communication network to which the embodiment of the present invention is applied. Explanation of symbols of main parts 1...C3MA/CD bus 2...Channel access section 3...Data link controller 5 section 4...
...Periodic bit detection unit 5...DA extraction unit

Claims (1)

[Claims] If the terminal is directly connected to one bus-type LAN (local area network) and the received data is addressed to a terminal on the first bus-type LAN, no transmission processing is performed on the data packet, and a data link control circuit having a filtering function for transmitting the data packet if the data packet is not addressed to the terminal, the circuit includes a destination address extraction section for extracting the destination address of the received data, and a data link control circuit accommodated in the first bus-type LAN; has a table pre-stored with all the terminal addresses stored therein, and compares the destination address and all the terminal addresses in parallel in real time to find that at least one of the stored terminal addresses matches the destination address. A string search device section that sometimes generates a match signal, and a receive buffer that receives and processes the received data and temporarily stores the received data, interrupts the receive process in response to the generation of the match signal, and generates the match signal. A data link control circuit comprising: a data link control section that performs a process of transmitting data stored in the reception buffer to another bus-type LAN if the data is not available.