JPS63271958A - Formation of multilayer interconnection - Google Patents

Abstract

PURPOSE:To enable correct alignment of wiring material by a method wherein a contact hole and wiring groove are formed in an interlayer insulating film, a wiring material is deposited flat, and the entire surface is subjected to etching after which the wiring material is retained in the contact hole and wiring groove. CONSTITUTION:A silicon oxide film 3 formed on a silicon substrate 1 is subjected to etching for the formation of a contact hole 4, after which a resist pattern 5 is formed with an opening corresponding to a wiring region. The resist pattern 5 serves as a mask in a process of etching the silicon oxide film 3, which results in a wiring groove 6. Next, an alloy layer 7 of aluminum and silicon is formed flat on the silicon substrate 1. The entire surface of the alloy layer 7 is subjected to isotropic etching using plasma, after which the alloy layer 7 is retained only in the wiring groove 6. In this way, a wiring pattern may be subjected to a correct alignment prior to the depositing of wiring material.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for forming multilayer wiring that enables high-density multilayer wiring in the manufacturing process of semiconductor devices.

BACKGROUND OF THE INVENTION As a conventional method for forming multilayer wiring, the following methods are generally known.

First, as shown in FIG. 2(a), a silicon oxide film 43 is deposited as an interlayer insulating film on a substrate 41 on which a predetermined element region is formed and electrodes 42 are formed, and a silicon oxide film 43 is deposited as an interlayer insulating film. A first contact window 44 is opened at the position.

Next, as shown in the second figure, an aluminum-silicon alloy is deposited as a first wiring layer 46 and patterned into a desired shape by photolithography.

Subsequently, as shown in FIG. 2C, a silicon oxide film 46 is deposited as an interlayer insulating film, a second contact window 47 is opened, and a second contact window 47 is formed using the same pressure as the first wiring layer.
A wiring layer 48 is formed so that the first wiring layer and the second wiring layer are electrically connected.

Problems to be Solved by the Invention However, with the above method, it is not possible to fill the contact hole completely flatly with the wiring material.

This is because if complete planarization is performed, the wiring material reflects light, making it impossible to determine the position of the contact hole and making it impossible to align the substrate and mask in photolithography.

Therefore, in the above method, it is necessary to leave a step when depositing and forming wiring material to enable alignment.
This level difference causes problems such as remaining level difference in the wiring material during etching of the wiring material.

Means for Solving the Problems In order to solve the above problems, the present invention, after forming the contact hole, etches the interlayer insulating film in the area that will become the wiring part to form a vertical groove, and then deposits the wiring material by CVD. Alternatively, the wiring material is deposited flatly on the interlayer insulating film by bias sputtering and etched over the entire surface, thereby leaving the wiring material in the contact holes and vertical grooves.

Function: By forming vertical grooves in the interlayer insulating film in the region that will become the wiring portion, the method of the present invention enables alignment of the wiring pattern before depositing the wiring material.

Usually, a light-transmitting material such as a silicon oxide film is used for the interlayer insulating film. Since no photolithography is used after deposition, completely planar interconnect material deposition is possible.

EXAMPLE An example of the present invention will be described below with reference to the drawings. FIG. 1 is a process sectional view showing an embodiment of the present invention.

For the sake of simplicity, the semiconductor device is shown in Figure 1 (
Although not shown in →, a predetermined semiconductor device is a p-type (1
00) After forming on the silicon substrate 1, a silicon oxide film 3 with a thickness of 1.6 μm is formed as a first interlayer insulating film by low pressure CVD.
Deposit using method D. 2 is an n+ diffusion layer formed on the semiconductor substrate.

Next, as shown in Figure 1, a resist pattern is formed at a predetermined position by photolithography, and a highly anisotropic reactive ion etching (R, 1, E) etc. is used as a mask on this. Etch the silicon oxide film 3 to form a contact hole 4.
form.

Similarly, as shown in FIG. 1(0), a resist pattern 6 is formed so that the portion that will become the wiring portion is open.

At this time, care is taken to ensure that the resist remains in the contact hole 4 and that the n+ diffusion layer 2 is not etched when forming the next wiring groove.

Next, as shown in FIG. 1, using this resist pattern as a mask, the silicon oxide film is etched by reactive ion etching or the like to form wiring grooves 6.

Next, as shown in FIG. 1(e), an aluminum silicon alloy 7 as a wiring material is formed flat over the entire surface of the substrate by bias sputtering.

Next, as shown in Figure 1 (phantom), this aluminum-silicon alloy 7 is etched over the entire surface by highly isotropic plasma etching, leaving the aluminum-silicon alloy only in #6. The purpose of this is to prevent the step from remaining even if there is a slight step, and here, isotropic etching is performed using chlorine gas and plasma etching with suppressed RF power.

As is clear from the explanation up to this point, alignment for wiring formation is performed before depositing the wiring material (see Figure 1).
C)), there are no alignment problems no matter how flat the wiring material is deposited.

Therefore, the wiring can be formed flatly and accurately.

Thereafter, as shown in FIG. 1(q), a second layer of wiring is formed in the same manner as before. A silicon oxide film 8 is formed as a second interlayer insulating film, and contact holes 9 and wiring grooves 10 are formed in the same manner as in the first layer.

Finally, as shown in FIG. 1(h), like the first layer, an aluminum silicon alloy is formed by bias sputtering, and the entire surface is etched by plasma etching.
Complete the 2nd layer wiring.

In this case, an aluminum silicon alloy was used as the wiring material and deposited flatly by bias sputtering, but the process cross-section of another example in which tungsten was used as the wiring material and was deposited flatly by low-pressure CVD is shown below. A diagram is shown in FIG.

As shown in FIG. 2(a), as in the previous embodiment, a silicon oxide film 2 is formed on a silicon substrate 21 having an n+ diffusion layer 22.
3 is deposited, and a contact hole 24 and a wiring groove 25 are sequentially formed using photolithography.

Next, as shown in Figure 2(b), tungsten 2θ is n
+ Diffusion layer 22 and silicon oxide film 23 are non-selectively formed over the entire surface by low pressure CVD. At this time, the tungsten film thickness is set to be at least % of the width of the wiring trench, and the tungsten 26 is completely buried in the contact hole 24 and the wiring trench 26.

In this example, the width of the wiring groove is set to about 0.8 μm, and the tungsten film thickness should be at least 0.4 μm, but the tungsten film thickness was set here to make the final wiring shape as flat as possible. It is set to 0.8 μm.

Next, as shown in FIG. 2(c), the tungsten 26 is etched on the entire surface by highly isotropic plasma etching, as in the previous embodiment, so that it remains only in the contact hole 24 and wiring groove 26.

Although subsequent steps will be omitted, the same process is repeated for the second and subsequent layers to form multilayer wiring.

As described in detail, the present invention involves forming a contact hole/wiring groove in an interlayer insulating film, cleaning it, depositing the wiring material evenly by CVD or bias sputtering, and then etching the entire surface of the wiring material. In particular, the wiring material is left in the contact hole/wiring groove.

As described above, the present invention has the effect of making it possible to accurately and flatly form wiring materials without causing difficulties in mask alignment.Within the semiconductor integrated circuit manufacturing technology that is increasing in density and multi-layered wiring, , is of extremely high industrial value.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view showing a method for forming a multilayer wiring according to an embodiment of the present invention using a bias sputtering method, FIG. 2 is a process cross-sectional view of another embodiment method of the present invention using a CVD method,
FIG. 3 is a process sectional view of the prior art. 1... Silicon substrate, 2... ♂ diffusion layer, 3, 8... Silicon oxide film, 4, 9...
...Contact hole, 5...Resist pattern,
6,10... Wiring groove, 7.11...
Aluminum silicon alloy. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 flash
Silicon, base, winter break Figure 1 Figure 2 tlJ
Qt-11 silicon carrier 22 ---n" 4 2j --- Shisofun West 2 conversion

Claims (1)

[Claims] (1) A step of etching an interlayer insulating film on a semiconductor device formed on a semiconductor substrate to form a contact hole, a step of etching a region of the interlayer insulating film that will become a wiring part to form a vertical groove, and a step of etching the interlayer insulating film on a semiconductor device formed on a semiconductor substrate to form a vertical groove. A method for forming a multilayer wiring, including a step of forming a material over the entire surface and a step of etching the wiring material over the entire surface, so that the wiring material remains in the contact hole and the vertical groove. (2) The multilayer wiring forming method according to claim 1, wherein isotropic etching is used for etching the wiring material.