JPS63271553A - Information processor - Google Patents

Abstract

PURPOSE:To improve the processing speed of an information processor without any unnecessary increase in hardware by comparing register number information with working register information and generating information for privilege exception detection when execution level information indicates an instruction of non-privileged level. CONSTITUTION:For example, a source-side operand is a register operand, a register R1 is specified, and a value (m) is held as a register number 105. A source-side comparator 106 compares the both and outputs 1 when m<=1. An SROP signal 101 is 1 and the output of a source-side mask gate 108A is 1 so that the source-side operand is the register operand. The output of an OR gate 111 is therefore 1. When a privileged level signal 112 is 0, namely, when a program is being executed at non-privileged level, an AND gate 114 outputs 1 and the privilege exception signal 115 becomes 1 for an instruction execution part 203, so that a privilege exception is detected. Consequently, the processing speed is improved without any increase in hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a central processing unit included in the information processing device.

[Prior Art] Conventionally, this type of information processing device has two types of registers: a general-purpose register group used when executing a general non-privileged level program, and a privileged register group that can be used only when executing a privileged level program. had a swarm. These privileged register groups only have registers for special purposes related to the hardware of the central processing unit, and cannot hold arbitrary data values or be used for calculations like general-purpose register groups. I couldn't do it.

In addition, the values of registers used for such special purposes can only be referenced or changed using special privileged instructions, and the values cannot be changed during execution of a non-privileged level program. Preventing it from being referenced or modified.

[Problems to be Solved by the Invention] The above-mentioned conventional information processing devices only have a group of privileged registers related to the hardware of the central processing unit, and are used privilegedly when executing software including the operating system. No privileged register was prepared for the work to be done. This is because even the operating system is software, and the number of working privilege registers required differs depending on the operating system used, and the number of working privilege registers to be prepared cannot be determined in advance. If a large number of working privileged registers are prepared in consideration of the differences in the operating systems used, the working privileged registers can only be used at the privileged level, resulting in a large number of registers that are used infrequently. A problem arises in that the amount of hardware increases.

On the other hand, if all the working data of the operating system is held in external memory without preparing any privileged registers for work, as in the conventional example, the external Since data must be transferred to and from the memory, a problem arises in that the processing speed of the information processing device is reduced.

Therefore, an object of the present invention is to provide an information processing apparatus that improves processing speed without unnecessary increase in hardware.

Means and Effects for Solving Problem E The information processing device of the present invention has at least two or more execution levels, a non-privileged level and a privileged level, and has a plurality of general-purpose registers and one of the plurality of general-purpose registers. decode information including register number information indicating the general-purpose register specified as the operand and execution level information indicating whether the instruction is a non-privileged level instruction or a privileged level instruction. In an information processing device equipped with an instruction decoder that forms an instruction decoder, a general-purpose register that can be accessed only by a privileged-level instruction and is used as a working register among the plurality of general-purpose registers when executing a privileged-level instruction is specified. When the register number register that holds working register information is compared with the register number information included in the decoding information and the working register information, and the execution level information indicates that the instruction is a non-privileged level instruction. The present invention is characterized by comprising a comparison means for forming privileged exception detection information.

Therefore, in the information processing device according to the present invention, by changing the work register information of the register number register with a privileged level instruction, a general purpose register is selected from a plurality of general purpose registers to be used as a working register when executing a privileged level instruction. Registers can be separated, and privileged exception detection information can be formed by comparing working register information and register number information using a comparing means during subsequent instruction execution.

In other words, in contrast to the conventional information processing device described above, the present invention has a general-purpose register and a working privileged register as the same hardware, and for example, by having the number of the register corresponding to the boundary in the privileged register, the working register can be accessed from the general-purpose register area. It has an original content in that the privileged register area can be used separately.

[Example] Land disaster] Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram showing the overall configuration of an information processing apparatus according to the present invention. The instructions decoded by the instruction decoder 201 are supplied as decode information 202 to the instruction execution unit 203, and the instructions are executed based on the decode information. The instruction execution unit 203 has a general-purpose register group 204.

In this information processing device, the general-purpose register group 204 includes n general-purpose registers, and each general-purpose register is RO to R.
I'll call it N.

FIG. 1 is a block diagram showing a first embodiment of the present invention,
2 shows a portion of the internal configuration of the instruction execution unit 203 in FIG. 2 that detects a privileged exception, which is a feature of the present invention.

Decode information 202 supplied from instruction decoder 201
includes a source register operand signal (hereinafter referred to as 5ROP signal) 101 indicating that the source operand of the instruction is a register, and source register number information 102, and similarly for the destination operand. It includes a register operand signal (hereinafter referred to as a DROP signal) 103 and destination side register number information 104. 105 is a register number register, the value of which can be changed only by a privileged instruction.

106 is a source side comparator, 107 is a destination side comparator, and these comparators 106 and 107 have the following values: m, the value held in the register number register 105, and the values of the register number information 102, 104, 1. , m≦1
Outputs an output signal "1" when . Source side mask gate 108A, destination side mask gate 10
9 is composed of an AND gate, and when the 5 ROP signal 101 and the DROP signal 103 are "1", the outputs of the comparators 106 and 107 are transmitted to the OR gate 111 of the next stage.

The privileged instruction signal 110 in the decode information 202 becomes "1" when the instruction decoder 201 decodes a single privileged instruction. The OR gate 111 is the source side mask gate 108
A, the output of the destination side mask gate 109, and the privileged command signal 110 are logically summed. The privilege level signal becomes "1" when the instruction execution unit 203 executes privilege level processing. Not gate 113 inverts privilege level signal 112. AND gate 114 is OR gate 1
11 and the output of the NOT gate 113, a privileged exception signal 115 is generated and notified to the instruction execution unit 203.

Next, the effect will be explained. Assume that the source side operand is a register operand, register R1 is specified, and register number 105 holds a value m. The source side comparator 106 compares the two, and when m≦1, the output of the source side comparator 106 becomes rlJ. Since the source side operand is a register operand, 5HOP signal 10
1 is "1", and the output of the source side mask gate 108A is "1". Therefore, the output of OR gate 111 also becomes "1". When the privilege level signal 112 is "0", that is, the program is being executed at a non-privileged level, the output of the AND gate 114 becomes "1", and therefore the privileged exception signal 115 becomes "1" to the instruction execution unit 203. A privileged exception is detected.

A privileged exception is detected in the same manner for the destination register number. Furthermore, when attempting to use a privileged instruction at a non-privileged level as in a conventional information processing device (for example, when a privileged instruction to update the register number register 105 is decoded), the privileged instruction signal 110 becomes "1".
Then, the privilege level signal 112 becomes "0", and the AND gate 114 causes the privilege exception signal 115 to become "1", whereby a privilege exception is detected.

By setting the maximum value m held in the register number register 105 to be larger than the number n of general-purpose registers 204, when n
Everything up to and including can be used unprivileged.

Plan λ2 light body FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 3 shows a portion corresponding to the privileged exception detection section on the source register operand side of the privileged exception detection section of the first embodiment shown in FIG.

The information processing apparatus shown in FIG. 3 has a plurality of execution levels. 301 is a bit execution level signal, and 2 types of execution levels can be specified from level O to level (2 to 1), level 0 is privileged and the higher the level value, the lower the privilege level. . Each register number register 105 has a 1-bit read field 302.
, a light field 303, a K-bit access level field 304, and a register number field 305 similar to that shown in FIG. Reference numeral 306 indicates an execution level comparator, which compares the value EL of the execution level signal 301 and the value AL of the access level field 304 and determines that EL>A.
When it is L, the output becomes "1". The source side comparator 106 similarly to FIG.
and the value l of the source side register number information 102, and when m≦l, the output becomes “1”. The instruction decoder 201 shown in FIG. 1 newly generates a source read operand signal 307 indicating that the source side operand is a read operand, and a source write operand signal 308 indicating that the source side operand is a write operand. AND gate 309 outputs the logical product of read field 302 and source read operand signal 307.

Similarly, the AND gate 310 outputs the AND of the light field 303 and the source write operand signal 308. OR gate 311 is ant game) 309 output and 3
The logical sum with the output of 10 is output, and the access match signal 3 is output.
form 12. The source side mask gate 108B outputs the AND of the access match signal 312, the output of the execution level comparator 306, the output of the source side comparator 106, and the source register operand signal 101 to form the source side privileged exception signal 313. do. For the destination operand, a destination side privileged exception signal 314 is generated by a similar circuit, and a privileged exception signal 115 is generated by an OR gate 315.

The execution level comparator 306 determines whether the execution level EL and the value AL of the access level field 304 are EL>AL.
, that is, when the current execution level is a lower privilege level than the value of the access level field 304,
Further, when the value 1 of the source side register number information 102 and the value m of the register number field 304 are m≦1, access is further performed by the read field 302, the write field 303, the source read operand signal 307, and the source write operand signal 308. The type of matches,
When the source side register operand signal 101 is "1", the source side privileged exception signal 313 becomes "1", and it is detected that the source side register operand is causing a privileged exception.

In other words, it is possible to prevent a specific general-purpose register area from being read or written at a level lower than a specific execution level. Although FIG. 3 shows only source side privileged exception detection, a similar circuit can be applied to the destination side as well. Furthermore, by having a plurality of sets of the circuits shown in FIG. 3 on the source side and the destination side, including the register number register 105, it is possible to give privileges to the general-purpose registers in stages according to the execution level. For example, if you have two sets of the circuits shown in Figure 3 on the source side, you can divide the general-purpose registers RO-Rn into three areas, 0≦m2≦n, and R
The privilege level can be increased from O to Rn.

[Effects of the Invention] As explained above, in the present invention, it is possible to have a working privilege register, which conventional information processing devices could not have, without preparing a dedicated register, and it is also possible to The number of privileged registers can also be easily changed depending on the operating system used. therefore,
This has the effect that processing speed can be improved without increasing hardware.

Furthermore, with the method of detecting privileged exceptions by comparing register numbers, even if the number of general-purpose registers increases, the bit width of the required comparator and register number register is small, so it requires less hardware. It has the advantage that it can be easily realized by increasing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a privileged exception detection mechanism in an information processing device according to a first embodiment of the present invention, FIG. 2 is a block diagram showing the overall configuration of the information processing device of the present invention, and FIG. FIG. 2 is a block diagram showing a source side portion of a privileged exception detection mechanism according to a second embodiment of the present invention. 101-source register operand signal, 102-source register number information, 103-destination register operand signal, 104-destination register number information, 105
- register number register, 106 - source side comparator, 107 - destination side comparator, 108A, 10
8B-Source side mask gate, 109-Destination side mask gate, 110-Privilege instruction signal, 111-OR gate, 112-Privilege level signal, 113-Not gate, 114-AND gate, 115-Privilege exception signal, 201- instruction decoder, 202-decode information, 203-instruction execution unit, 204-general-purpose register, 301-execution level signal, 302-read field, 303-write field, 304-access level field, 305-register number field, 306-execution Level comparator, 307-source read operand signal, 308-source write operand signal, 309-AND gate, 310-AND gate, 311-OR gate, 312-access match signal, 313-source side privileged exception signal, 314-destination Side privileged exception signal, 315-
Orgate. Patent applicant Kiyoshi Kuwai, agent for NEC Corporation and patent attorney - Figure 2

Claims (1)

[Claims] A plurality of instructions having at least two or more execution levels, a non-privileged level and a privileged level, and including a plurality of general-purpose registers and an instruction that specifies any one of the plurality of general-purpose registers as an operand. An information processing device comprising an instruction decoder that sequentially decodes and forms decode information including register number information indicating a general-purpose register designated as an operand and execution level information indicating whether the instruction is a non-privileged level instruction or a privileged level instruction. , a register number register that can be accessed only by a privileged level instruction and holds work register information that identifies a general register that is used as a working register when executing a privileged level instruction among the plurality of general purpose registers; Comparing means for comparing the register number information included in the decoding information and the working register information to form privileged exception detection information when the execution level information indicates that the instruction is a non-privileged level instruction. An information processing device characterized by: