JPS6326716A - Central processing unit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a central processing unit CPU by outputting clocks to each function of the CPU after receiving the clocks from a clock generating circuit and the signals from an instruction decoder circuit. CONSTITUTION:An instruction supplied to an instruction register 106 outputs the function-based control signals 115 through an instruction decoder circuit 105 together with a control signal 117 that discriminated a specific function block that requires a clock. A stand-by circuit 102 receives a signal 113 from the circuit 105 and a clock 111 from a clock generating circuit 101 and controls supply of clocks. A clock distributing circuit 104 receives the signal 117 together with a clock 112 supplied from the circuit 101 via the circuit 102 and supplies the clocks only to the function blocks needed for actions of instructions.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a central processing unit.

[Conventional technology]

Conventionally, in this type of central processing unit, clocks are constantly supplied to each functional block from a clock generation circuit even when no program is being executed, resulting in large power consumption, waste, heat generation, and other important problems. Therefore, a standby circuit was used that stopped the clock supply when the program was not being executed.

An example of a conventional central processing unit will be described with reference to FIG.

For the command input to the command register 106, the command decoder 205 outputs a control signal 115 for each function and a control signal 113 indicating whether or not the clock 212 is supplied to the functional clocks 106 to 110 other than the standby release circuit 103. . The standby circuit 102 includes an instruction decoder circuit 105
In response to the signal 113 output from the clock generation circuit 101 and the clock 111 output from the clock generation circuit 101, the clock supply is controlled. For example, when a standby command is manually input to the instruction register 106, the supply of the clock 212 to devices other than the standby release circuit 103 is stopped, and unless a standby release signal such as an external interrupt request is input, the standby circuit will continue to use the clock 212. No supply.

[Problem that the invention seeks to solve]

The conventional central processing unit mentioned above is either running a program or
The clock is controlled in standby mode. Therefore, even when some functions are running, the clock is supplied to all 7 locks, so there is a drawback that power consumption is high during program execution.

An object of the present invention is to reduce power consumption by stopping the supply of clocks to unnecessary clocks even while the central processing unit is executing a program.

[Failure to solve the problem]

Central processing unit kr of the present invention: and standby circuit.

Equipped with an instruction decoder circuit and a clock distribution circuit.

A clock is supplied to the clock distribution circuit from a clock generation circuit via a standby circuit.

Receives the signal output from the instruction decoder circuit.

It is characterized by outputting clocks to each function of the central processing unit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a central processing unit according to an embodiment of the present invention. In the figure, blocks having the same functions as those in FIG. 2 are designated with I'F+]- symbols.

In FIG. 1, a clock distribution circuit 104 is added between the standby circuit 102 and each functional block, compared to the conventional relay shown in FIG.

The command input to the command register 106 causes the command encoder circuit 105 to output a control signal 115 for each function and a control signal 117 which determines which functions require a clock. The clock distribution circuit 104 is connected to the standby circuit 102.
It receives a clock 112 and a control signal 117 supplied from the clock generation circuit 101 via the clock generation circuit 101, and supplies only the clocks necessary for the command operation.

For example, transfer instructions in general-purpose registers, arithmetic instructions.

A comparison table of the clock supply status of an actual example and a conventional example in the serial output command and standby command is shown below.

However, the numbers in the table represent the respective clocks shown in FIGS. 1 and 2, and ○ and × represent the presence or absence of clock supply.

As described above, by controlling the clock supply for each instruction decode, instead of supplying the clock to all 10 blocks, by supplying the input clock to the blocks related to instruction operation, power consumption can be reduced compared to the conventional method. decrease compared to

〔Effect of the invention〕

As is clear from the above description, according to the present invention, power consumption can be reduced by stopping the supply of clocks to circuits other than those necessary for operation even when the central processing unit is executing a program. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a central processing unit according to the present invention, and FIG. 2 is a block diagram of a conventional central processing unit. 101... Clock generation circuit, 1o2...
...Standby circuit, 103...Standby release circuit, 104...-Clock distribution circuit, 105
, 205... Instruction decoder circuit, 106...
...Instruction register. IO2...Program counter, 10g...
... Arithmetic circuit, 1o9 ... General purpose register, 1
10... Serial output circuit, 111...
・・Basic clock, 112° 212・・・・・Clock % output from standby circuit 113・・・・
- Signal indicating standby or not, 114... Clock to each program, 115... Control signal for each function, 116... Group/internal bus, 117...・
- Control signal that determines which functional block requires a clock, 118... A signal indicating whether standby is to be released or not.

Claims (1)

[Claims] The clock distribution circuit includes a standby circuit, an instruction decoder circuit, a clock generation circuit, and a clock distribution circuit, and the clock distribution circuit receives a clock supplied from the clock generation circuit via the standby circuit and a signal output from the instruction decoder circuit. A central processing unit is characterized in that it outputs a clock to each functional block of the central processing unit in response to the clock.