JPS63255779A - Address control circuit - Google Patents

Abstract

PURPOSE:To improve the graphic drawing processing performance by giving drawing area information and a coordinate position on a two-dimensional drawing memory space to obtain a memory address and a bit position of a one- dimensional constitution. CONSTITUTION:Drawing area data is written in an X register 3 and a Y register 5. At the time of address conversion, coordinates of a prescribed point are written in an (x) register 7 and a (y) register 8. Contents of the Y register 5 and the (y) register 8 are inputted to an ALU 10 through multiplexers 6 and 9 by the instruction of a control circuit 1 and a prescribed arithmetic is performed; and if the result is not 0, the arithmetic result is stored in a shift number register 2, and contents of the (x) register 7 are transferred to a parallel shifter 4 and are shifted by contents of the shift number register 2. When the coordinate value is written in the (x) register 7, contents of 24 bits or more and said obtained arithmetic result are given to the ALU 10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a raster scan data drawing processing device, and more particularly to a control circuit that generates an address to a memory.

Conventional technology Conventionally, this type of memory address control has been processed within a one-chip LSI developed for graphic drawing processing.

Further, the processing is performed by a program using a general-purpose high-speed μmProcessor.

Problems to be Solved by the Invention The above-mentioned conventional memory address control in graphic drawing requires each machine operation to convert a two-dimensional address into a one-dimensional address, and also requires This method has the disadvantage that address translation processing must be performed, resulting in a significant drop in processing performance.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the conventional technology, and therefore, an object of the present invention is to provide a novel address control circuit that makes it possible to speed up the graphic drawing processing performance. It's about doing.

Means for Solving the Problems In order to achieve the above object, the address control circuit according to the present invention has a main scanning force direction width and a sub-scanning direction (which indicates the drawing area).
b) An X register and a Y register that store the width, an X register and a y register that store the coordinate position on the drawing memory of two-dimensional representation, a barrel shifter necessary for two-dimensional → one-dimensional conversion processing, and various calculations. The control circuit includes an ALU that performs the operation, a multiplexer that switches the input to the ALU, and a control circuit that generates control signals to the register groups, barrel shifter, M-sword, and multiplexer.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a schematic block diagram showing an embodiment of the present invention. FIGS. 2(a) and 2(b) are diagrams showing the correlation between address positions in two-dimensional representation and address positions in one-dimensional representation.

Referring to FIGS. 1 and 2, the drawing memory configuration will first be described. Generally speaking, drawing memory is
Each word is 16 bits long, and the drawn images are stored in order from the raster scan start position (Ul in FIG. 2(a)). Coordinates in the graphic drawing process are two-dimensional, and are managed with the lower left corner, ie, Qa in FIG. 2(a), as the origin. However, in the actual drawing memory configuration, since the device is in the raster scan direction, the upper left, ie, 01, is processed as the origin, as shown in FIG. 2(b). Therefore, point A in Fig. 2(a)
To convert (x, y) into a one-dimensional memory address an K, the following formula is used.

W=,, r,,==Xo+X1 (XO: quotient, X
i: remainder) as=wx((Y-y)-13+xo,,
, , , , , , , , , , , (Y)Xl indicates the bit position within the word.

In the present invention, the calculation of the above equation (Y) is processed at high speed.

At the time of initial setting, drawing area data (focus expression) is written into the X register 3 and Y register 5 of one address control circuit through the data signal line ai. At this time, the word in the drawing area +
11! In order to obtain (b), the lower 4 pins are ignored and written to the X register 3. Next, during address conversion, the coordinates (x, y) of point A are written to X register 7 and X register 8, respectively. The procedure here is that first, the data is written to the X register 8.

Then, the control circuit 1 outputs the instructions to the multiplexers 6 and 9.
The contents of Y register 5 and X register 8 are transferred to the ALU through
10, the calculation (Y-y)-1 of the above equation (Y) is performed, and if the result is other than "0", the calculation result is stored in shift number register 2, and the contents of X register 7 are The data is transferred to barrel shifter 4 and shifted by the contents of shift number register 2. As a result, wX ((Y−y)
-1) result is obtained. Next, enter the coordinates (x
When the X value of , y) is written, the contents of 2 bits or more and the contents of wx((Y-y)-[ obtained earlier
The result of the operation wX((Y-y)-t J+x, tv is obtained. In other words, the value of address arc is obtained. Also, the bit position on the address bus is determined by the lower 4 pinpoints of the X register 7. You can get 9 things by looking out.

As described in detail of the invention, the address control circuit of the present invention has drawing area information and coordinate position ft(x, y) on the two-dimensional drawing memory space.
) is given as y-4x by K, the memory address and bit position of a one-dimensional configuration can be obtained at high speed, and the effect of speeding up the graphic drawing processing performance can be obtained.

[Brief explanation of the drawing]

Figure 1 is a schematic block configuration diagram showing an embodiment of the present invention. Figure 2 is a diagram showing the correlation between the position of a drawing memory in a two-dimensional space and the address position in a memory in a one-dimensional space. Yes. 1...Control same temperature, 2...Fist shift number register, 3...
・X register CVZ, 4...barrel shifter, 5 fists・
・Y register, 6ψ...multiplexer, 7・fist・X register, 8...y register, 9...multiplexer, 10...@ALU, 11...multiplexer, ai
-・Fist card data pass, a.

Claims (1)

[Claims] In a device that draws raster scan image data,
The width in the main scanning direction (X) and the width in the sub-scanning direction (Y
) An X register and a Y register that store the width, an x register and a y register that store the coordinate position A (x, y) on the two-dimensional image drawing surface, and a barrel shifter necessary for the two-dimensional → one-dimensional conversion process. , an ALU for performing calculations, a group of multiplexers for switching inputs to the ALU, and a control circuit for generating control signals to the registers, the ALU, and the multiplexers.