JPS63244255A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To transmit data with simple processing by supplying a control signal to a data transmission means and a slave processor from a register that supplies an address signal to a decoder in a mask memory. CONSTITUTION:The mask memory 13 that supplies a selection signal to n-pieces of slave processors 14 as well as contains plural pieces of n-bit data is provided, and the register 12 that supplies an address signal to the decoder 15 in the mask memory 13 also is provided. This register is connected to a first bus 101 and supplies a data transmission means control signal to a data transmission means 11, and supplies a slave processor control signal to the n-pieces of slave processors 14. The plural pieces of n-bit data are stored in the mask memory 13, and their addresses are written in the register together with data transmission mode. In such a way, the initialization for data transmission can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to data transfer in a multiprocessor system having a host processor and a plurality of slave processors.

Prior Art A block diagram of a multiprocessor system according to the prior art is shown in FIG. The input/output terminal of the main memory 25, the first input/output terminal of the data transfer means 21, and the register 2 are connected to the first bus 201 to which the host processor 20 is connected.
2 input terminal and the input terminal of the n-bit wide mask register 23 are connected, and the second input/output terminal of the data transfer means 21 is connected to a second bus to which n slave processors 24 are connected.

Next, control of data transfer in a multiprocessor system according to conventional technology will be explained. In this multiprocessor system, data transfer is controlled by the host processor 2.
o does everything, and the slave processors 241-24n follow suit. First, the host processor 20 registers 2
Write the transfer mode in 2. The transfer direction, the type of transfer data, etc. are set in the transfer mode written here, and the data transfer means control signal 204 and slave processor control signal 205 are set according to the contents.

Next, the host processor 20 selects n slave boots o-t.
=Which slave processor 2 among Tsusa 241 to 24n?
n-bit data indicating whether data transfer is to be performed for 41 to 24n is written into the mask register 23. This n
The bit data is used as it is as the n slave processor select signals 203, and data is transferred via the data transfer means 21 between the slave processors 241 to 24n selected by this signal and the host processor 2o. A plurality of n-bit data to be written to the mask register 23 are stored in a certain area of the main memory 25 connected to the first bus 201, and any n-bit data 26 is written to the main memory 25 each time it is transferred. The data is read from the mask register 23 and written to the mask register 23. This completes the initial settings for data transfer and starts data transfer.

Problems to be Solved by the Invention In a conventional multiprocessor system, each time data is transferred, an arbitrary
It was necessary to read out the bit data 26 and write that data into the mask register 23. Therefore, for example, consider the case where the first bus 201 is 32 bits wide and the number n of slave processors 241 to 24H is 256.
In order to write data to the mask register, access to the main memory 25 is required at least eight times, and initial settings for data transfer take time, which is a bottleneck in performing data transfer at high speed. Furthermore, since data transfer occurs frequently during program execution, the inability to perform data transfer at high speed directly causes a reduction in program execution speed.

The present invention has been made in view of this point, and provides a multiprocessor system that transfers data through simple processing.

SUMMARY OF THE INVENTION The present invention provides a host processor, a first bus coupled to the host processor, data transfer means coupled to the first bus, and data transfer means coupled to the data transfer means. a second bus connected to the second bus, n slave processors connected to the second bus, a mask memory that supplies all select signals to the n slave processors and stores a plurality of n-bit data; a register for providing an address signal to a decoder in the mask memory, the register being coupled to the first bus, the register providing a data transfer means control signal to the data transfer means; This is a multiprocessor system characterized by supplying slave processor control signals to n slave processors.

The effect mask memory stores multiple pieces of n-bit data, and any n-bit data can be set simply by writing the address together with the data transfer mode to the register. Initial settings for data transfer can be made with simple operations.

Moreover, the data transfer means is the first. Since it is provided between the second buses, even if the data transfer speeds are different between the first bus and the second bus, data transfer between the buses can be performed while ignoring this difference.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. The first input/output terminal of the data transfer means 11 and the register 12 are connected to the first bus 101 to which the host processor 1o is connected.
input/output terminals are connected, and n slave processors 1
A second input/output terminal of the data transfer means 11 is connected to a second data bus to which the data transfer means 41 to 14n are connected.

The mask memory 13 is composed of ROM or RAM,
A device that can store multiple pieces of n-bit data.In the case of ROM, an arbitrary number of n-bit data as required is coded in advance, and in the case of RAM, it is coded before program execution. Write an arbitrary number of necessary n-bit data. For example, even if the number of n-bit data 16 is 256, only 8 bits are required for the address of the mask memory 13, and the increase in the amount of information written to the register 12 is small.

Next, data transfer control in the multiprocessor system according to the present invention will be explained. In this multiprocessor system, only the host processor 10 controls data transfer, and the slave processors 141 to 14n follow it. First, the host processor 10 writes the transfer mode and an arbitrary address of the mask memory into the register 12.

In the transfer mode written here, the transfer direction, the type of transfer data, etc. are set, and the data transfer means control signal 106 and slave processor control signal 106 are set according to the contents. At the same time, from the mask memory 13, n-bit data 1 corresponding to the address written in the register 12 is output.
6 is read out, and this n-bit data 1e is used as it is as the slave processor select signal 104.

This completes the initial settings for data transfer, and starts data transfer.

Here, for example, if the number n of slave processors 141 to 14n is 266 and the bus width is 32 bits, in the conventional technology, the main memory must be accessed at least eight times to perform initial settings for data transfer. (32 bits x 8 times = 256 bits), but according to this embodiment, just by writing the address to the register 12 once,
You can do the same thing. Further, the width of the address written to the register 12 is at most 8 bits even if 256 n-bit data are stored in the mask memory, so the amount of information written to the register 12 does not need to be increased much.

Therefore, according to this implementation, initial settings, which in the prior art required accessing the main memory many times each time data is transferred, can be performed with a simple operation of simply writing the address of the mask memory 13 in the register 12. be able to.

Note that if a FIFO memory or dual port memory is used as the data transfer means, there is no need for synchronization between host processors during data transfer, and data transfer can be performed independently. Further, if the data transfer means 11 is a simple bus switch, the first bus and the second bus can be regarded as one bus, and data transfer can be performed in DM mode or in synchronization.

Effects of the Invention As is clear from the above explanation, in the multiprocessor system according to the present invention, initial settings for data transfer can be performed through simple processing, and the setting time required for initial settings for data transfer is large. It is possible to prevent the program execution speed from decreasing due to

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system according to an embodiment of the present invention, and FIG. 2 is a block diagram of a multiprocessor system according to the prior art. 1o...Host processor, 11...
Data transfer means, 12...Register, 13...
...Mask memory, 16...Decoder,
16...n bit data, 1o1...
First bus, 102...Second bus, 103
...Mask memory address signal, 105...
...Data transfer means control signal, 106...Slave processor select signal, 141 to 14n...
...Slave processor.

Claims (1)

[Claims] a host processor, a first bus coupled to the host processor, a data transfer means coupled to the first bus, a second bus coupled to the data transfer means, and a second bus coupled to the first bus; n slave processors coupled to the n slave processors, a mask memory that supplies select signals to the n slave processors and stores a plurality of n-bit data, and a register that supplies address signals to decoders in the mask memory. and a register coupled to the first bus, the register providing a data transfer means control signal to the data transfer means, and the register providing a slave processor control signal to the n slave processors. A multiprocessor system characterized by: