JPS63231611A - Waveform generator - Google Patents

Abstract

PURPOSE:To increase the number of degrees of freedom by outputting address data of waveform data to be read out from each pattern memory to the pattern memory and converting waveform data read out in parallel to serial waveform data and subjecting it to D/A conversion and performing the control in accordance with a preliminarily set sequence program. CONSTITUTION:A first waveform generating system A is formed with a sequencer 16, an address generating part 10, a pattern memory 8, a data converting part 12, a data selecting part 14, and a D/A converter 15. A second waveform generating system B is formed with the sequencer 16, an address generating part 11, a pattern memory 9, a data converting part 13, the data selecting part 14, and the D/A converter 15. Thus, a waveform is quickly is obtained through relatively inexpensive memories are used, and a waveform generator where the number of degrees of freedom of the sequence program is large is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a waveform generator that converts digital waveform data into an analog signal waveform and outputs the analog signal waveform.

(Prior Art) FIG. 7 is a block diagram showing an example of such a conventional waveform generator. In FIG. 7, 1 is a pattern memory in which waveform data to be output is stored, and the waveform data stored in this pattern memory 1 is read out to the D/A converter 3 according to the address added from the sequencer 2. is converted into an analog signal waveform.

By the way, the D/A converter 3 is 100MH2~50MHz.
Devices that convert waveform data into analog signal waveforms at a frequency of 0 MHz can be obtained relatively inexpensively, but pattern memories 1 that can be accessed at a frequency of about 100 MHz are quite expensive and difficult to obtain. Furthermore, it is difficult to obtain such a high-speed memory with a large memory capacity.

Therefore, for example, as shown in FIG.
An address to which waveform data stored in multiple 8-stage pattern memories 41 to 4 whose speed is lower than the operating frequency of the A converter 7 is distributed and stored in each of these pattern memories 41 to 4 from the sequencer 5. It is also practiced to read out the data and add it to the shift register 6, for example, to convert it into serial waveform data, and then add this serial waveform data to the D/A converter 7, where it is converted into an analog signal waveform.

With this configuration, a pattern memory with a large capacity can be produced at a much lower cost than the pattern memory 1 shown in FIG. 7.

(Problem to be Solved by the Invention) However, the configuration shown in FIG. 8 has the disadvantage that the data length of one waveform unit can only be set with the number of samples that is an integral multiple of the number of stages of the pattern memory. .

That is, in the case of FIG. 8, the waveform must be a multiple of 8 as the number of samples. As a result, when trying to generate a TV signal, for example, since there is a relationship between the subcarrier frequency rsc and the horizontal synchronization frequency f, fsc = 455 · fH/2, the number of samples of 1H scanning line is of'
Generally, it is 4 times fsc, 910, but 910 is not a multiple of 8, so 910 samples are 11
It is not possible to create a 1-minute waveform, which limits the number of samples.

The present invention has focused on these points, and its purpose is to provide a waveform generator that can generate high-speed waveforms while using a relatively inexpensive memory and has a high degree of freedom in sequence programming. be.

(Means for Solving the Problems) The waveform generator of the present invention comprises a first waveform generator, each of which is divided into a plurality of n stages, and predetermined waveform data is distributed and stored in each stage. a second pattern memory, and a first pattern memory that outputs address data of waveform data to be read from each of these pattern memories to each pattern memory. a second address generating section; and a first address generator that converts waveform data read out in parallel from each of the pattern memories into serial waveform data. a second data converter, a data selector that selectively outputs the serial waveform data output from each of these data converters, and a D/A that converts the waveform data added from the data selector into an analog signal waveform. a converter; and the first. A sequencer that controls the second address generation section and the data selection section according to a preset sequence program.

(Example) Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, 8.9 is a first stage which is divided into a plurality of n stages, and predetermined waveform data is distributed and stored in each stage.
．． This is a second pattern memory. 10.11 outputs address data of waveform data to be read from each pattern memory 8.9 to each pattern memory 8.9. Second
This is the address generation part. 12.13 converts the waveform data read out in parallel from each pattern memory 8.9 into serial waveform data. This is a second data conversion section. Reference numeral 14 denotes a data selection section that selectively outputs the serial waveform data output from each data conversion section 12 and 13. 15 is a D/A converter that converts the waveform data added from the data selection section 14 into an analog signal waveform. 16 is the first. This is a sequencer that controls the second address generation section 10.11 and the data selection section 14 according to a preset sequence program. Here, sequencer 16→address generator 10→pattern memory 8→
Data converter 12 → data selector 14 → D/A converter 1
5, a first waveform generation system A is formed, and a second waveform generation system B is formed by the sequencer 16 → address generation section 11 → pattern memory 9 → data conversion section 13 → data selection section 14 → D/A converter 15. is formed.

FIG. 2 is a block diagram showing a specific example of FIG. 1. In FIG. 2, the depth of the pattern memory 8.9 is assumed to be 128 kilowords, one word is formed by 12 bits, and the number of division stages n is eight. A shift register is used as the data converter 12, 13, and a multiplexer is used as the data selector 14. Φ is a basic clock, which is applied to the sequencer 16, address generators io and ii, data converters 12.13 and D/A converter 14.

The sequencer 16 generates a control signal Cot for controlling the multiplexer 14, a control signal Cv for controlling the address generating section 10, and a control signal 02 for controlling the address generating section 11, according to a preset sequence program. Generate and output. The pattern memory 8.9 includes eight stages of pattern memories 81-8s, each having a width of 12 bits/word and a depth of 16 kilowords.
It is composed of 9+ to 9B. The address generator 10 outputs 14-bit address data to each pattern memory 81-88 according to the waveform data to be read from each pattern memory 81-88 according to the control signal C1, and the address generator 11 outputs each address data according to the control signal C2. 14 depending on the waveform data to be read from the pattern memories 91 to 9s.
Bit-configured address data is stored in each pattern memory 91~
Output to 9B. 12-bit predetermined waveform data corresponding to the address data is outputted from the pattern memories 81 to 88 to the shift register 12, and then transferred to the pattern memories 91 to 98.
From there, 12-bit predetermined waveform data corresponding to the address data is output to the shift register 13. The shift register 12 sequentially shifts eight relatively slow sets of 12-bit waveform data added from the pattern memories 81 to 8B, converts them into one set of high-speed 12-bit waveform data, and outputs the converted data to the multiplexer 14. shift register 1
3 sequentially shifts eight relatively slow sets of 12-bit waveform data added from pattern memories 91 to 98 to convert them into one set of high-speed 12-bit waveform data and outputs the converted data to multiplexer 14. Multiplexer 1
4 is added from the shift registers 12 and 13 according to the control signal Co applied from the sequencer 16.
Bit waveform data is selectively output to the D/A converter 15.

FIG. 3 shows the pattern memory 8.9 in II of FIG.
FIG. In the example of FIG. 3, the sequencer 16 has [
Assume that a program is written that reads 30 words (decimal) of waveform data stored between addresses 148 and 31H of pattern memory 8.9 repeatedly. In the pattern memories 8 and 9, (a)
As shown in (b), the same waveform data is stored in a distributed manner, and in FIG. , address i of pattern memory 9
The waveform data stored in H is shown with a corresponding symbol ■'. In the case of this embodiment, ■-0- is satisfied for all i. (C) shows the address space (OH to IFFFFH) of each pattern memory 8.9.

FIG. 4<8) is an explanatory diagram of the configuration of the address counter 17 that constitutes a part of the address generation units io and i1, and (b)
is the truth table of the action. As shown in the figure, the load signal S
When L is at the L level, a 14-bit start address is set at the rising edge of the clock CL, and when the load signal SL is at the H level, the count is counted up at the rising edge of the clock OL, and a 14-bit pattern address is sequentially output. Note that these load signals SL and clock CL are processed by the sequencer 16 into control signals C;
Together with I*02, it is basically created based on R0tsukΦ. However, the clock OL is obtained by dividing the basic clock Φ according to the number of stages of each pattern memory 8, 9.

That is, in this embodiment, the frequency is divided into 1/8. The clock OL created by frequency division in this way is a signal that separates one cycle of each group, and it can be said that one pulse of the clock CL is created by eight pulses of the basic clock Φ. Specifically, the control of the address generation section 10.11 by the sequencer 16 mainly focuses on controlling the operation of the address counter 17 as described above.

FIG. 5 is a timing chart for explaining the operation of FIG. 2. In FIG. 5, (a) shows the basic clock Φ, and (b) shows the load signal SL! applied to the address counter of one system A. , and (C) is the clock CL + added to the address counter of one system A.
, (d) shows the load signal SL2 applied to the address counter of the other system B, (e) shows the clock CL2 applied to the address counter of the other system B, and <r> shows the load signal SL2 applied to the address counter of the other system B. It shows the applied control signal Co. Note that this timing chart ignores propagation delays in each part of the circuit. Also,
The time point at which the selection of the system changes from A to B is designated as To, and the operation will be explained centering around this time point 0. Then, each phase of the basic clock Φ is centered on To and is
2+ T-1+To, T+, T2...

In this example, the final cycle of one system A is T −2
This is for 8 clocks from ~T5, and the waveform data e-Q are sequentially output from the shift register 12.

However, in this embodiment, since the necessary waveform data is up to O, it is necessary to switch to the output of the shift register 13 of the other system B using the control signal Go at the time To when the shift register 12 has output the waveform data .Furthermore, at the time of To, the shift register 13 has waveform data 0-
Therefore, the first cycle of system B must be started retroactively to the time point T-a.

That is, the first cycle of system B corresponds to eight clocks from T-4 to T3, and at this time, waveform data O=, o-, . . . - are sequentially output from the shift register 13. Then, the moment To when the waveform data G)- is output
The output is switched to the grid date output by the control signal Co.

The load signal SLI changes from H to L during the final cycle of system A. After this, we will move to system B,
During this time, the next start address for system A is set. Therefore, when the load signal @S L I is L, Otsuk CL
Start up I and reload the address counter.

The load signal SL2 needs to be changed from L to `` before the first cycle of system B starts with the rising edge of clock CL2.

FIG. 6 shows an example of a waveform output according to such control.

All cycles of systems A and B are clocked by clock C.
L1. Controlled by CL2. Note that each of these clocks CL1. CL2 corresponds to 8 clocks of 0 clocks Φ from the reference.

Furthermore, the phases of these clocks CL+ and CL2 do not necessarily match. In the case of this embodiment, in general, 8 j + 1 - . . . address of the pattern memory where the final data is stored in the selected system before switching the system (j: natural number, ρ-0, 1 . . . ..., 7) 8
+m... Assuming that the pattern memory address (k; natural number, m-0, 1, . . . , 1) where the first data is stored in the system selected after switching the system is as follows. I can say that.

T-ti-+...Start point of the final cycle of the system selected before switching systems, T-11L...
・Start point of the first cycle of the system selected after switching the system, To... Time of system switching.

Actually, T-ti-+ cannot be moved because it is the currently selected cycle. Therefore, T-J! -t
T-m and To will be calculated based on . Note that the clock OL1. CL2 phase difference and reference clock Φ
The timing of is determined each time the system is switched. In addition, the minimum packet length in such a device is determined by the time required for these calculations, the time required to switch systems, and the time required to reload the address counter with the starting address after switching systems. .

In addition, in the above embodiment, an example was explained in which one packet is repeatedly generated, but although the minimum word length of the packet is limited, it is also possible to generate a packet of any word length starting from any address with the same circuit configuration. You can also create waveforms by freely selecting them.

For example, if the sequencer 16 has "pattern memory 8.9"
30 words (decimal) of waveform data (packet 1) stored between addresses 14H to 31H of 5
"Repeatedly read 86 words (decimal) of waveform data (packet 2) stored between addresses 55H-AΔH of pattern memories 8 and 9 10 times." It is assumed that a program with the following content has been written. The basic control in this case is the same as the control described above, but differs in the following points.

First, in the previous embodiment, the reset value of the start address to the address counters of both series A and B is always the same, but in this embodiment, the start address of packet 1 is set to the address counter of series A. After alternately setting the address counter of system B three times and twice, the start address of packet 2 is alternately set in the address counter of system B five times and the address counter of system A five times.

Here, it must be noted that since the number of repetitions of packet 1 is an odd number, system B is set first for packet 2.

Second, in the previous embodiment, the switching timing of systems A and B is always the same, but in this embodiment, packet 1
It changes when moving from packet 2 to packet 2.

(Effects of the Invention) As explained above, according to the present invention, it is possible to obtain high-speed waveforms while using a relatively inexpensive memory, and it is possible to realize a waveform generation device with a high degree of freedom in sequence programming. is big.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific example of FIG. 1, FIG. 3 is an explanatory diagram of a pattern memory used in the present invention, and FIG. 5 is a timing chart for explaining the operation of FIG. 2, FIG. 6 is an example of the output waveform of the device of the present invention, and FIGS. 7 and 8 are diagrams of conventional devices, respectively. It is a block diagram showing an example. 8.9...Pattern memory, 10.11...Address generation section, 12.13...Data conversion section (shift register), 14...Data selection section (multiplexer)■
6 Figure No. 812

Claims (1)

[Claims] First and second pattern memories, each of which is divided into a plurality of n stages, each of which stores predetermined waveform data in a distributed manner, and address data of the waveform data to be read from each of these pattern memories. first and second address generation units that output to the pattern memory; first and second data conversion units that convert waveform data read out in parallel from each of the pattern memories into serial waveform data; and each of these data conversion units a data selection unit that selectively outputs serial waveform data output from the data selection unit; a D/A converter that converts the waveform data added from the data selection unit into an analog signal waveform; and the first and second address generation units. 1. A waveform generator comprising: a sequencer that controls a data selection section and a data selection section according to a preset sequence program.