JPS63226151A - Multiple packet communication system - Google Patents

Abstract

PURPOSE:To improve transmission efficiency by providing a packet memory corresponding to each of the priority given to each packet, on both a transmission system and a reception system. CONSTITUTION:When a second packet whose priority is high is inputted from an input signal line 11, and written to a memory 110-n, a transmission system 100 suspends the transmission of a first packet, and starts the transmission of a second packet. In this case, a flag adding circuit 120 adds a packet delimiting flag to the second packet and sends it out to a transmission line 30. A reception system 200 detects its flag by a flag detecting circuit 220, suspends write and read-out to and from the memory 210-1 of the first packet which is receiving, and writes the second packet to a memory 210-n. Also, it is read out and sent out to an output signal line 22. Subsequently, the remaining part of the first packet which has been suspended is read out of the corresponding memory 110-1, and its transmission is started continuously after the regular flag of a termination of the second packet. In such a way, the transmission efficiency can be improved.

Description

[Detailed Description of the Invention] [Summary] Both the transmitting system and the receiving system are provided with packet memories corresponding to the respective priorities given to each packet, and even during the transmission of the first packet. is interrupted, a second packet with a higher priority is transmitted in advance, and then transmission of the remaining part of the first PIF is resumed,
When the receiving system also receives the second packet, it interrupts the reception of the first packet, receives the second packet in advance, and then resumes receiving the remaining part of the first packet 7). Not only can the second packet be sent and received immediately, but the first packet does not need to be retransmitted, thereby improving transmission efficiency.

[Industrial application field]

The present invention relates to a packet communication system, and more particularly to a bucket communication system that multiplexes and transmits packets each having a priority, and further separates and receives the packets.

In multi-packet communication, each packet having its own priority, packets with higher priorities must be sent and received in real time. Furthermore, regarding packets with low priority, transmission and reception must be resumed after a short waiting time, and the procedure must be as straightforward as possible. In other words, in a multi-packet communication system with priorities, improving transmission efficiency is one of the important issues.

[Conventional technology]

FIG. 15 is a schematic block diagram of a conventional communication system for multiplex paqueso 1. In this figure, 10 is a transmitting system, and 20 is a receiving system, which are connected by an uplink transmission path 30 and a downlink transmission path 31. In the transmission system IO, the packet from the input signal line 11 is applied to the input selection section 12, and is sent to the non-priority side queue 14 in the transmission queue I3.
Alternatively, it is stored in the priority side queue 15. Furthermore, the output selection unit 16 selects either a priority or non-priority packet and sends it to the transmission path 30.

The receiving unit 21 of the receiving system 20 receives normal packets among the packets received from the upstream transmission line 30, that is, the packets transmitted from the non-priority side queue 14, and sends them as is to the output signal line 22. .

Assuming that a transmission request for a priority packet is now generated in the transmission system 10, this priority packet is stored in the priority side queue 15, and further sent to the transmission line 30 by the output selection section 16. In this case, the priority packet will be transmitted by interrupting the non-priority packet that is being transmitted.

FIG. 16A is a diagram showing a general packet format, and FIG. 16B is a diagram showing an example of a conventional packet format when a priority packet interrupts a non-priority packet. Figure 16R shows non-priority Paqueso]-(
This example shows a state in which a priority packet (including data DT2) is interrupted during transmission of a packet (including data DTl), and is interrupted, for example, at the dot-dashed line of a packet (non-priority packet) in FIG. 16A. In this case, the non-priority packet that was being transmitted is not sent to the receiving system 20 (Fig. 15) as a complete formant packet shown in Fig. 16A, and reaches the receiving system 20 with the frame check sequence FC3 missing. do. Then, the receiving section 21
(FIG. 15) detects an FCS error and discards the incomplete packet (non-priority packet).

Since the discarded non-priority packet needs to be retransmitted once again, the receiving unit 21 sends it to the transmitting system 10 (Fig. 15) via the downlink transmission path 31 (Fig. 15). A retransmission command is issued to request retransmission from the input selection unit 12 (FIG. 15), thereby completing communication of the non-priority packet.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional multiplex packet communication system,
If a high-priority packet tries to interrupt a low-priority packet, only the high-priority packet will be sent with the highest priority, so the low-priority packet will end up being discarded. Put it away. Furthermore, in order to recover from the discarded data, it is necessary to perform retransmission, resulting in a problem of transmission delay. Furthermore, since the same information that has already been sent is sent again, a problem arises in that the utilization rate of the transmission path, that is, the transmission efficiency is deteriorated. Also, as a matter of course, a problem arises in that packet congestion occurs due to retransmission on the output signal line 22 side compared to the input signal line 11, increasing traffic congestion. In particular, these problems have become increasingly noticeable in view of the recent tendency for packet lengths to increase, for example, for data (DT) to consist of several thousand bytes.

The present invention was developed in view of the above-mentioned problems, and requires that high-priority packets be immediately transmitted, and low-priority packets that are interrupted by packets with high priority A☆ must be retransmitted. The purpose of this invention is to provide a multi-packet communication system with high transmission efficiency.

c. Means for Solving Problem] FIG. 1 is a diagram showing the principle configuration of a multiple packet communication system according to the present invention. In this figure, 100 is a transmission system,
200 is a receiving system, and these are connected by a transmission path 30. The transmitting system 10 ( ) includes a transmitting side packet memo 10 for storing -1 packets supplied from the input signal line 11 . This bucket is assigned one of a plurality of (n) predetermined priorities, and the memory (110-1, 110-2...110~
n). These memories (110-1, 11
Each packet read from packets 0-2 .

On the other hand, the receiving system 200 is provided with a flag detection circuit 220 for identifying the above-mentioned predetermined flag, and depending on the detected flag, the received packet is transferred to one of the memories in the receiving side packet memory 210 ( 210-1, 210
-2...210~n). Furthermore, this is read out and sent to the output signal line 22.

[For production]

When the transmitting system 100 selects the memory 110-1 in the packet memory 110 and reads out the first packet with a low priority, the flag adding circuit 120 normally adds the flag (
F) and sends it to the transmission line 30. While this first packet is being transmitted to the receiving system 200, if a second packet with a higher priority is input from the input signal line 11 and written to the corresponding memory, for example, memories 110 to n, then the transmission The system 100 immediately stops transmitting the first packet at that point and starts transmitting the second packet. At this time, the flag adding circuit 120
sets this second packet to the packet delimiter flag (IF
) and sends it to the transmission path 30.

When the reception system 200 receives the second packet with the IF, the flag detection circuit 220 detects the IF, and
Memory 210 of the above first packet being received so far
-1 is interrupted, and the second packet is written to the corresponding memory 210-n. Furthermore, this is read out and sent to the output signal line 22.

In the transmission system 100, when the transmission of the second packet with a high priority is completed, the flag adding circuit 120
A normal flag (F) is attached to the end of the second packet and it is sent to the transmission path 30, and the remaining part of the interrupted first packet is read out from the corresponding memory 110-1 and Transmission starts following the normal flag (F) at the end of the second packet.

In the reception system 200, when the flag detection circuit 220 detects the normal flag (F) at the end of the second packet, the reception of the first packet, which has been interrupted, is changed to the normal flag (F).
) and then resumes writing to the corresponding memory 210-1. Furthermore, this is read out and sent to the output signal line 22.

By transmitting and receiving multiple packets as described above, the present invention eliminates the need to discard or request retransmission of a low-priority first packet that is interrupted by a high-priority second packet. Transmission and reception of the first packet can be completed with only a delay corresponding to the waiting time for the transmission of the second packet to be completed. Therefore, transmission efficiency is improved and traffic on the output signal line 22 can also be alleviated.

〔Example〕

FIG. 2 is a block diagram showing the basic configuration of a multiple packet communication system according to the present invention. In this figure, when a packet is manually input to the transmitting side input selection unit 130 from the input signal line 11, memories 110-1, 110-2 .=110 to n according to the packet priority order ■, ■...0 will be forwarded to. This priority is set in advance at the time of link setup, and is written as header information in the header (H in FIG. 16A) of each packet.

This header information typically includes an LCN (Logical Channel Number).

Packet memory 1 selected by input selection unit 130
Assuming that the packet is transferred and written to the memory in the memory 10-1, for example, the memory 110-1 of the lowest rank, the transmission request from the memo January 10-1 is transmitted to the output control unit 140. The output control unit 140 outputs the memory 11 that received the transmission request.
0-1 and the transmitting side output selection unit 160 are activated,
Connect these to each other.

On the other hand, the memory 110 connected to the output selection section 160
The packet read from -1 is transferred to the output selection section 160. The flag adding circuit 120 adds a predetermined flag to the transferred packet using the inserting section 170 and sends it to the transmission line 30. In this case, a normal flag F is added. These controls are performed by commands from the output control section 140.

Now, while the first packet with a lower priority is being transferred (in the case of the above example, the packet from Memo January 10-1 is being transferred), the second packet with a higher priority than this,
For example, if a packet with the highest priority (◎) is input from the input signal line 11, it is written to the corresponding memo I/month 10-n via the input selection section 130. At the same time, the output control tray section 140 stores the written priority order (■) of the interrupted first packet in the 0 section 150. By the appearance of a second packet with higher priority,
The output control unit 140 interrupts the transmission of the first packet currently being transferred, puts the memory 110-1 of the priority order ■ written in the storage unit 150 in a waiting state, and
The flag adding circuit 120 is instructed to generate a packet delimiter flag IF instead of the normal flag F. At the same time,
Memo with new top priority packet written January 10-n
and the output selection section 160 are connected. Immediately after the first packet is interrupted, the packet separation flag TF is added and in synchronization with the completion of transmission to the receiving system, transmission of the second packet with the highest priority is started.

When the transmission of the second packet with the highest priority is completed, the output control unit 140 instructs the flag adding circuit 120 to generate the normal flag F again. At the same time, the priority order being saved (■ in this case) is read out to the storage unit 150,
The output selection unit 16 outputs the memory 110-1 that was in the waiting state.
0 and resumes transmitting its contents (first packet) in synchronization with the end of transmission of the normal flag F attached to the end of the second packet.

FIG. 3 is a diagram showing an example of a transmission format of multiplex packets according to the present invention. As shown in this figure, the priority quotient second packet (including data DT2) that interrupts the first packet (including data DTI) with a lower priority is the first half of the first packet (before interruption). ) and the second half (after the interruption).

Returning to FIG. 2 again, in the receiving system 200, the flag detection circuit 220 detects that the flag at the head of the first packet (low priority) input from the transmission path 30 is the normal flag F. do. Furthermore, the input control unit 240 is notified of the detection.

The input control unit 240 connects the corresponding memory in the packet memory 210 (memory 210-1 in this case) and the input selection unit 230, and selects the first packet from the memo+72
Write in 10-1. At the same time, the input control section 240
stores the priority order ■ in the receiving side storage unit 250 and saves it.

Next, when the flag detection circuit 220 detects the packet delimiter flag IF while receiving the first packet, it notifies the input control unit 240 of this fact. Upon receiving the notification, the input control unit 240 puts the memory 210-1 corresponding to the priority order (in this case ■) stored in the storage unit 250 into a waiting state, and stores a new highest priority packet (the second packet described above). )
Memories 210 to n and receiving side output selection unit 260 corresponding to
and interconnect each other. Furthermore, a second
write a packet of

After that, the normal flag F attached to the end of the second packet
When detected by the flag detection circuit 220, this is notified to the input control unit 240. Human control unit 240 that received the notification
is the priority order stored in the storage unit 250 (■ in this case)
The memory 210-1 corresponding to 210-1 is placed in a waiting state, and a new high-priority packet (memory 210-n in this case) corresponding to the second packet recording day mentioned above and the input selection unit 2 are placed in a waiting state.
30 are interconnected. Furthermore, the memory 210~n
writes that second packet to .

Thereafter, when the flag detection circuit 220 detects the packet delimiter flag IF attached to the end of the second packet, it notifies the input control unit 240 of this fact. The input control unit 240 that received the notification reads the priority order ■ saved in the storage unit 250, and stores the corresponding memory 2 in the waiting state.
10-1 and the input selection section 230 are connected. As a result, reception of the remaining portion of the first packet is resumed.

Thus, the packets written in the memories 210-1 and 210-n are alternatively read out by the receiving side output selection section 260, and then the output signal 1i! 22 and subjected to the next stage of processing. Note that the storage unit 150 described above
and 250 is, for example, RAM (RandomAc
cess Memory).

FIG. 4A is a state transition diagram for explaining the operation in the transmitting system, and FIG. 4B is a state transition diagram for explaining the operation in the receiving system.
(Fig. 2) and the operation of the input control unit 240 (Fig. 2) are mainly shown. It should be noted that each state is classified and shown as (1) to (2).

In the state transition diagram of the output control section 140 in the transmission system shown in FIG. 4A, first, in the reset state (2), the inside of the circuit is reset and placed in the initial state by an initial request from the outside.

In the idle state (2), the output control unit 140 becomes capable of transmitting a packet, and when a packet transmission request 1/request 2 is generated from the previous stage circuit, a transition is made to the next transfer state (2) for packet transfer work.

The transfer state of ■ is the state in which the packet is actually being sent to the transmission path 30, and when the packet transfer is completed, a flag is sent.
When a higher priority packet transmission request 1 arrives, the state changes to the packet separation flag state (2).

The flag transmission state (2) is a flag transmission state that indicates the end of packet transmission, and after the flag transmission is completed, the remaining packets during multiple interrupt transfer (when request 1 and request 2 occur at the same time) It transits to the packet delimiter flag state (■) for transfer, and otherwise shifts to the idle state (■).

The packet delimiter flag state (2) is a state in which a request 1 with a high priority occurs during packet transmission, the currently transmitting packet is temporarily stopped, and the packet delimiter flag for sending the request 1 packet is being transmitted. After transmitting the packet delimiter flag, the state transitions to transfer state O in order to transfer the new request 1 packet.

Next, a state transition diagram of the input control section 240 in the receiving system shown in FIG. 4B will be explained.

First, in the reset state (■), the output control section 14 of the transmission system
It is placed in the initial state as in 0.

The idle state (2) is a state in which the input control unit 240 is able to receive packets from the transmission path 30, and when it receives a notification of packet reception from the transmission path 30, it receives the packet (2) for packet reception processing. Move to state.

The packet reception status in (2) indicates that the packet is actually sent to the transmission path
After receiving the packet, there is a transition to the flag reception state (■) due to flag reception, and a transition to the packet delimitation flag state (■) due to reception of the packet delimiter flag.

The flag reception state (■) is a flag reception state that indicates the end of packet reception. After the flag reception is completed, the status changes to the packet separation flag state (■) in order to receive the remaining packets when multiple interrupts are received. Otherwise, it moves to the idle state of ■.

The packet delimiter flag state (2) is a case where a packet delimiter flag is received during packet reception, and this is regarded as a multiple interrupt, and a highly requested packet can be received. After receiving the packet delimiter flag, the state changes to the packet receiving state (2) in order to receive a highly requested packet.

Hereinafter, specific examples of the basic configuration shown in FIG. 2 will be described for a first embodiment and a second embodiment. FIG. 5 is a circuit diagram showing a transmitting system according to a first embodiment of the present invention, and FIG. 6 is a circuit diagram showing a receiving system according to a first embodiment of the present invention. In both figures, the same reference numerals are given to the same components as described above.

In the first embodiment (Figures 5 and 6), the packet memo January 10 (Figure 2) is FIFO (First In
In FIG. 5, packet memories 110 and 2 are used.
10 (FIG. 2), FIFO memory IILI,
111-2 . . . 111 to n are introduced, and in FIG. 6, FIFO memory 211-1.

211-2...211 to n are introduced.

First, in FIG. 5, an input packet from the input signal line 11 is inputted to a logical channel number (LCN) analysis section 180, and then enters a transmission line correspondence section via a transmission processing section 190. This transmission path corresponding section (the sections disposed on the right side of the transmission processing section 190) is particularly relevant to the present invention. In other words, the LCN analysis section 180 and the transmission processing section 190 are originally required for normal packet communication.

The LCN analysis unit 180 includes a shift register 182 that sequentially takes in input packets, a control circuit 183 that outputs a required timing signal upon receiving a notification that a packet has been received (P R) in the shift register 182, and a shift register 182. At the timing when the logical channel number (LCN) is stored in the logical channel table 181 that takes in the L'CN, the LCN is stored in the table 181.
When the search for a new logical channel number LCN' corresponding to the new logical channel number LCN' is completed, the LCN' is sent out at a predetermined timing in order to rewrite this LCN' to the original LCN in the packet of the current user. Gate 184 and L C
It consists of a packet gate 185 that cuts off the corresponding part of the packet (bit position W of the original LCN) only at the timing when it should be rewritten to N'. Note that the logical channel numbers (LCN, l, CN') form part of the header (H) information as described above, and a new L
This information is rewritten to CN' and is one of the important pieces of information in implementing packet communication services. During call setup, the logical channel table 181 has an input L CN
, output LCN (LCN' described above), and information necessary for communication are also set.

The priority order, which is particularly relevant to the present invention, is set in the logical channel table 181 along with the output LCN.

Note that the priority order of each packet is not always the same from the calling party to the called party, and may change from one relay exchange to another.

The transmission processing section 190 at the previous stage leading to the transmission path correspondence section performs 0 insertion, FC3 addition, etc. O insertion means to prevent consecutive “l”s from continuing in the data, and to insert a flag (for example, “
11111110”) and data to avoid misidentification.
- Refers to operation. The FC3 addition is the addition of a frame check sequence (Fe2) in FIG.

Now, we will move on to the transmission path corresponding section, which is the main part of the present invention. The packet that has passed through the transmission processing section 190 first enters the shift register 134 in the input selection section 130.

The priority order in the header ([I) information updated in the logical channel table 181 described above is determined by this shift register 13.
4 to the decoder 133. The input control circuit 131, which has received the notification that the packet has been received (PR), instructs the decoder 133 as to the timing at which the priority order should be decoded. By this decoding, the FIFO memory (llll
-1 to 111 to n) and write the contents of the packet therein. That is, the write clock WC from the input control circuit 131 is passed through one write clock gate 132 opened by the output of the decoder 133,
Apply to the corresponding FIFO memory. Each FIFO memory 1
11-1 to 111 to n individually output a packet presence/absence signal PE indicating whether or not a packet has been written inward. Output control unit 14 that receives this bucket presence/absence signal PE
0 is shown as an output control circuit 141 in FIG. The insertion part 170 is the flag gate 17
1 and 172, and selects the output of one of the normal flag generator 121 and the pass/soto delimiter flag generator 122 forming the flag adding circuit 120. Further, the output selection section 160 consists of a read clock gate 161,
A read clock RC from the output control circuit 141 is applied to any one of the FIFO memories 111-1 to 111-n.

The aforementioned bucket presence/absence signal PR is constantly monitored by the output control circuit 141, and when there is "no packet", the normal flag generator 121 is activated and the normal flag continues to be transferred to the transmission line 30. On the other hand, the packet presence/absence signal PE
If "one or more 1 bucket exists" is displayed, the output control circuit 141 stores the FIFO memory (111-1 to 111-1
1 to n), a read clock RC is applied to the FIFO memory. The read packet is sent to the transmission path 30. When the sending of this packet is completed, the normal flag generator 121 generates the normal flag F.
is sent to the transmission line 30. If further packets to be sent are stored in other FIFO memories (111-1"111~n
), continue reading it and transmitting it to transmission line 3.
Send to 0.

While a packet with a low priority, for example, the first packet with priority ■ is being read from the FIFO memory 111-1, a second packet with a lower priority, for example a packet with priority O, is read out from the FIFO memory 11Ln. Suppose that it is written to . Then, the output control circuit 141 outputs an even higher priority (0) as the packet presence/absence signal PR.
Knowing that there are packets, the FI currently being read
Supply of the read clock RC to the FO memory 111-1 is temporarily stopped. At the same time, the priority order (■) of the first packet whose reading was interrupted is stored in the storage unit 150. Then, the read clock RC is supplied to the FIFO memories 111-n, and the transmission of the second packet is started. At this time, the output control circuit 141 opens the flag gate 172 and adds the packet delimiter flag IF to the beginning of the second packet. Thereafter, the second packet is sent to the transmission path 30 from the FIFO memory January 11-n.

When the transmission of the second packet with higher priority is completed, the output control circuit 141 opens the flag gate 171, adds the normal flag F to the end of the second packet, and marks the end of the transmission of the second packet. . At the same time, the output control circuit 141 accesses the storage unit 150, reads out if there is a low priority waiting queue, and stores the suspended first packet from the corresponding FIFO memory (111-1 in this case). The remaining portion is read out and sent to the transmission line 30. Hereinafter, the bucket format of the main part in FIG. 5 will be explained with reference to the drawings.

7A is a diagram of the bucket format on the input signal line 11, FIG. 7B is a diagram of the packet format at the input of the shift register 134, FIG. 7C is a diagram of the packet format on the transmission line 30 when there is no priority interrupt, and FIG. 7D
The figure is a diagram of the packet format on the transmission line 30 when a priority interrupt occurs. In FIG. 7A, a priority P is written in a part of the control section in the header H. The control unit also writes the type of audio or data.

LCN and DT are the previously described logical channel number and data portion. In FIG. 7B, LCN is LCN'
can be rewritten as Furthermore, the priority order P may also be rewritten in the logical channel table (181 in FIG. 5). In Figure 7D, the second highest priority (for example O)
packets are inserted into the first bucket with a low priority (for example, ■).

In the reception system 200 shown in FIG. 6, the reception bucket from the transmission path 30 is transmitted through a normal flag detector 221 and a bucket separation flag detector 222, which constitute a flag detection circuit 220.
It is applied in parallel to a shift register 234 that forms part of the input selection section 230. In the idle state, the normal flag F is flowing on the transmission line 30, and this fact is indicated by the input control unit 240.
This notification is sent to the input control circuit 241 that makes up the system, and no other activation is performed. When the packet node is received from the transmission path 30, the normal flag reception notification FR from the flag detector 221 is stopped, and instead, the bucket reception notification PR is transmitted from the shift register 234 to the input control circuit 241. At the same time, the priority order P' in the header H is decoded by the decoder 233 forming the input selection section 230. This decoding results in one write clock gate 2 corresponding to P'.
32 (forming the input selection section 230) is opened, and the write clock WC from the input control circuit 241 is applied to one corresponding FIFO memory 2 in the receiving side packet memory 210.
11-1 to 211 to n, and the packet just received is written therein. If this packet is the first packet mentioned above (priority ■), is it 1? IFO memory 211-
Write to 1. When a packet is written to the FIFO memory 211-1, the packet presence/absence signal PE is notified to the output control circuit 242 forming the input selection section 240 as "one packet exists", and the corresponding read clock gate 261 (output selection section 260 ) is opened. As a result, the read clock RC from the output control circuit 242 is supplied to the corresponding FIFO memory (211-1 in this case), from which the packet is read and sent to the output signal line 22. Note that the reception processing section 290 located in the middle of the output signal line 22 corresponds to the transmission processing section 190 in FIG. 5, and performs zero inversion removal and FC3 removal.

If a second packet (with priority level 0) interrupts the reception of the first packet, the input control circuit 241 is notified of the bucket delimiter flag reception notification IFR, and the interrupt flag is stored in the storage unit 250. 35) Store the priority order (■) of the first packet received.

Thereafter, the first packet is sent to the output signal line 22 in the same procedure as the first packet described above, and when the normal flag F at the end is detected again by the detector 221, the information in the storage unit 250 ( ■) to the FIFO memory 211-1 based on
Start writing the first packet.

The output control circuit 242 detects that the packet presence/absence signal PR from the FIFO memory 21L1 is "packet present" and reads out the remaining portion of the first packet from the memory 21L1. As a result, the interrupted transmission of the first packet is restarted.

In the first embodiment described above, FIFO memory was used as the packet memory, but in the second embodiment described below, RAM (Random AccessM) was used as the packet memory.
Emory) is used.

FIG. i is a circuit diagram showing a transmitting system according to a second embodiment of the present invention, and FIG. 9 is a circuit diagram showing a receiving system according to a second embodiment of the present invention. Note that the same components as those already described are indicated with the same reference numbers or symbols.

The operating principle of the transmission system 100 in FIG. 8 is basically almost the same as that of the first embodiment shown in FIG.

As a whole, it consists of a logical channel number (LCN) analysis section 180 at the input end of the transmission processing section 190, and a transmission line correspondence section at the output side thereof. Of these, other than the transmission line support section (
180, 190) are as explained in the first embodiment.

Specifically, the transmission side input selection section 130 in the transmission path correspondence section is a shift register 1 that sequentially stores input packets.
37, an input control circuit 136 that is activated when a packet arrives at the shift register 137 and controls the input pointer table section 135, etc., and a write address gate 38 that supplies or stops the supply of addresses to the RAM section 113. . With these, the shift register 137
The packets sent from the memory are sequentially written into the corresponding memory area. The corresponding memory area is determined by the priority order P' of the input packet, and this P' is also input to the RAM section 113.

To read the packet, the read address from the output pointer table section 163 forming the output selection section 160 is given to the RAM section 113 via the read address gate 62 under the control of the output control circuit 143 forming the output control section 140. This is done by The output control circuit 143 also outputs the normal flag F or bucket delimiter flag IF from the flag adding circuit 120 to the flag gate 171 or 172.
is output selectively by controlling. This point is exactly the same as in the first embodiment.

Next, looking at the receiving system 200 in FIG.
The flag detection circuit 220 at the exit of the flag consists of a normal flag detector 224 and a bucket delimiter flag detector 225, as in the first embodiment. The input selection section 230 includes a shift register 235, an input control circuit 236, a manual pointer table section 237, and a write address gate 238. According to the address from this gate 238, the packet in the shift register 235 is written into the RAM section 213. Which memory area to select at this time is designated by the priority order P' read from the shift register 235.

The input control section 240 includes an output control circuit 244, and the receiving side output selection section 260 includes an output pointer table section 263 controlled by the circuit 244, and a read address gate 2.
64, and the gate 264 is controlled to open and close by a timing circuit section 245, which together with the gate 238 constitutes the human control section 240. When the gate 264 is opened, the bucket is read out from the RAM unit 213 addressed and sent to the output signal line 22 through the reception processing unit 290 described above.

FIG. 10 is a diagram schematically showing the relationship among the RAM section, input pointer table section, and output pointer table section. Note that these RAM sections, pointer table sections, etc. are included in the transmission system 10.
0 and the receiving system 200 are common. The manual pointer table unit 135 (237) stores the start addresses corresponding to the priorities ■, ■...O, increments (adds) each start address by 1, and when the next start address is reached, it returns to the original address. Return to Therefore, RAM section 1
13 (213) is divided into n pieces corresponding to each priority level, and a write address is cyclically specified for each memory area. Note that which priority level is to be accessed is specified by an input side priority level storage register, which will be described later.

On the other hand, the output pointer table section 163 (263) also stores the start addresses corresponding to priorities ■, ■...0, and increments each start address by 1, and when it reaches the next start address, it returns to the original address. Return to

Therefore, the RAM section 113 (213) is divided into n parts corresponding to each priority level, and a read address is cyclically designated for each memory area. Note that which priority level is to be accessed is specified by an output side priority level storage register, which will be described later. In addition, the packet number storage table, which will be described later, is stored in the RAM section in order to prevent previously written buckets from being overwritten (erased) by newly input buckets due to the above-mentioned cyclic writing. It is used to detect whether the number of packets that can be tolerated in the divided memory area has been reached.

If the number of allowed packets is reached, writing to the input bucket will be temporarily prohibited. Thus, the RAM of the second embodiment functions equivalently to the plurality of FIFO memories of the first embodiment.

FIG. 11 is a diagram showing a detailed example of a circuit for realizing the configuration schematically shown in FIG. 10. Therefore, the circuit example in FIG. 11 is also common to the transmitting system 100 and the receiving system 200. The configuration of FIG. 11 is roughly divided into four functional groups, and these areas are shown divided by dotted lines.

In addition, the input control circuit 136 (236) is necessary for the sake of explanation.
, the output control circuit 143 (244) is also drawn.

The left end in Fig. 11 is the input side IN (human power signal line 11 in Fig. 8).
, corresponding to the transmission line 30 in Fig. 9), and the right end in Fig. 11 is the output side OUT (corresponding to the transmission line 30 in Fig. 8,
(corresponding to the output signal lines 22 in FIG. 9).

When a bucket is input to the shift register (1?EG) 137 (235), the bucket reception PR is notified to the input control circuit 136 (236), and its priority P' is stored in the priority storage register (P-REG). 311. The input control circuit 136 (236)
1 is in the active state, and its priority P' is partially flipped.
After latching with flop (FF) 312 (operates with clock CK), write pointer table (WI'T) 31
Access 3. This specifies the corresponding pointer (input pointer table section 135 (23
7) address, see ■...). The specified pointer (address) is used to read/write the read command from the input control circuit 136 (236).
)] After partially launching the address indicated by the pointer in flip-flop 314, l? AM321 and adder (A D + 1)
315. The adder 315 increments the pointer (address) by 1, and then writes the pointer (address) to the table 313 again.
By returning to , the currently designated memory area can be accessed cyclically, as explained in FIG. Note that the rewriting of the address from the adder 315 is performed by R.
This is done by a write command from the input control circuit 136 (236) via the /W1 line.

The address previously output from the pointer table 313 specifies the address for the llAM321. At the same time, the timing circuit (TM) 3 is activated by the data write clock DWC from the input control circuit 136 (236).
41, the packet in the register 137 (235) is written to the RAM 321.

The timing circuit 341 in the timing circuit section 144 (245>) has a clock CK obtained by dividing the original clock CLK by 2 and a clock CK obtained by inverting this by an inverter.
Outputs . Clock CK is write timing signal W
The inverted clock CK is the read timing signal R.
Make a T. These timing signals alternately open and close write address gate 342 and read address gate 343. This prevents simultaneous writing of a packet and reading of a packet (to be described later) within the R11M321.

Note that the gate 342 corresponds to the gate 138 in FIG. 8 and the gate 238 in FIG. 9, and the gate 343 corresponds to the gate 162 in FIG. 8 and the gate 264 in FIG.

On the other hand, the priority stored in the priority storage register 311 is transferred to the RAM unit 113 (2) via the address gate 322.
13) Packet number storage table (PNT) 324
and a decoder (DEC) 334. The priority is determined by accessing the corresponding packet number storage location in the table 324, and after part of the data representing the packet number is launched in the flip-flop 325, it is applied to the comparator (CMP) 331, and Gate 327 (
(opened by WT) through an adder (A D +
1) Applied to 330. The output of comparator 331 controls terminator (TRM) 335. That is, the decoder 334 decodes the data indicating the priority of accessing the previous packet number storage table 324, and sets "l" in a predetermined bit position of the terminator 335 corresponding to this priority. This "1" is RAM3
It is displayed that the packet has been written to the corresponding memory area in 21.

On the other hand, the adder 330 described above increments the number of packets corresponding to the previous priority by 1 and writes the packets to the same storage location again. At this time, the gate 326 is
is open.

“1” of the predetermined bit in the terminator 335 is transmitted to the output control circuit 143 (244) as a bucket presence/absence signal PE indicating “packet present”. The output control circuit 143 (244) that recognized "packet present"
The priority storage register (P-REG) 351 in the output pointer table section 163 (263) is activated, and the priority corresponding to the predetermined focus position (“1” is set) of the terminator 335 is set to the encoder (ENC). 33
6 and stored in the register 351. Furthermore, after this priority is partially lied in the flip-flop 352, the corresponding read pointer table (RP
T) Specify the address for 353, and first
321, a pointer indicating the blank area where the packet is written is output. Note that this pointer is R/
It is read out by the command from the output control circuit 143 (244) via the W3 line, and further read out by the flip-flop 354.
After being read and laundered, it is applied to the LLAM 321 through the read address gate 343, which is now open due to the read timing signal RT. I? AM321 reads the packet indicated by the pointer in accordance with the data read clock DRC, and sends it to the output side OUT.

The pointer (address) output from the read pointer table 353 is added to the adder (AD+1) 355.
It is incremented by 1 and written back to the original position.

On the other hand, the output from the priority storage register 351 is transmitted to the gate 32 which is opened by the read timing signal RT.
3, accesses the corresponding packet number storage position in the packet number storage table 324, reads out the packet number, and sends it to the comparator 331 and adder 330.

At this time, the inverter-equipped gates 329 and 328 are opened by the read timing signal RT. The number of packets given to the comparator 331 is given to the maximum value register 33 via the gate 332, which is in charge.
The number of packets is compared with the maximum number of packets starting from 3, and if the maximum value has been reached, the predetermined focus position of the terminator 335 is reset to "O". At the same time, this fact is given to the input control circuit 136 (236) as a MAX notification, and input is prohibited. As a result, when each memory area in the RAM 32 becomes full of packets, the original packets are prevented from being erased by the next packet player 1. If the maximum value has not been reached, the current state is maintained.

The number of packets transferred through the inverter-equipped gate 329 is decremented (subtracted) by 1 at the adder 330 by the action of the inverter, and then returned to its original polarity at the inverter-equipped gate 328 and then stored in the packet number storage table 324 again. is written to the corresponding storage location.

“1” in each bit position in the terminator 335
, the presence/absence information of the packet indicated by “O” is the signal P F,
The packets are then sent to the output control circuit 143 (244), where the packets are controlled to be sent out in order of priority, and based on this, the packets with higher priority are sent out first to the output side OUT.

While sending the packet to the output side OUT, the terminator 33
The "packet present" hint displayed in bit position 5 is a bit with a higher priority than the packet being sent.
packets must be interrupted. This interrupt processing is performed as follows.

Figure 12 shows the priority storage register 35 on the output side of the transmission system.
FIG. 1 is a circuit diagram showing details of FIG. In order to interrupt the transmission of the first packet with a second packet having a higher priority, the output control circuit 143 temporarily stores the priority of the first packet being transmitted in the priority storage RAM 414. This is done by a write command from the R/W4 line. In this case, the priority of the first packet being transmitted is the one stored in priority register 412, and is flipped.

It is written into the priority storage RAM 414 via the flop 413. The address to the RAM 414 at this time is given by the counter 415, and is incremented by 10l after writing. This increment command is U/D
(Up/Down) line.

The priority of the second packet with the highest priority that newly arrived is output from the encoder 336, and is set in the register 412 by opening the gate 411 with the command S1. In this case, output control circuit 1
43, the packet delimiter flag generator 1
22 (FIG. 8) is activated, the packet delimiter flag IF is sent out, and the second packet is transmitted following this IF (as described above). At the end of this transmission, a flag is usually added as described above.

During this time, the output control circuit 143 constantly monitors the contents of the counter 415 and checks whether or not there is a priority that is being saved in the IAM 414 (priority storage). If there is a priority, this value is decremented by 1 (according to the command from the U/D line) and the address is set as the address.
Read the priority of Furthermore, the original priority order is set in the register 412 again through the gate 416 opened by the command S2.

As a result, the RA of the first packet node that was suspended
Reading from M321 is resumed.

Figure 12 shows the priority storage register 35 on the output side of the transmission system.
1 has been shown, but the configuration of the priority storage register 311 at the input end in the receiving system is also almost the same as the configuration shown in FIG. FIG. 13 is a circuit diagram showing details of the priority storage register 311 on the input side of the receiving system. Furthermore, the priority storage register 311 on the input side of the transmission system has almost the same configuration as shown in FIG. 14.

Figure 14 shows the priority storage register 35 on the output side of the receiving system.
FIG. 1 is a diagram showing a specific example of No. 1; In this figure, games 1-6
Reference numeral 11 denotes a gate that opens in response to a command from the output control circuit 244, and sets the priority from the encoder 336 in the priority register 612. The priority is sent to the read pointer table 353 and packet number storage table 324 described above. The priority storage register 311 on the input side of the transmission system is the encoder 336 in FIG.
is replaced with the shift register 137, the output control circuit 244 in FIG. 14 is replaced with the input control circuit 136, and the first
This is equivalent to replacing 353 in FIG. 4 with the write pointer table 313.

〔Effect of the invention〕

As described above, according to the present invention, packets with higher priority can be transmitted preferentially over packets with lower priority without deteriorating transmission efficiency.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the multiple packet communication system according to the present invention, FIG. 2 is a block diagram showing the basic configuration of the multiple packet communication system according to the present invention, and FIG. 3 is a diagram showing the basic configuration of the multiple packet communication system according to the present invention. FIG. 4A is a state transition diagram for explaining the operation in the transmitting system; FIG. 4B is a state transition diagram for explaining the operation in the receiving system; FIG. 5 is a state transition diagram for explaining the operation in the receiving system; 6 is a circuit diagram showing a receiving system according to the first embodiment based on the present invention; FIG. 7A is a packet format diagram on input signal line 11; Figure 7B is a diagram of the packet format manually generated by the shift register 134, Figure 7C is a diagram of the packet format on the transmission line 30 when there is no priority interrupt, and Figure 7D is the packet format on the transmission line 30 when a priority interrupt occurs. 8 is a circuit diagram showing a transmitting system according to a second embodiment based on the present invention, FIG. 9 is a circuit diagram showing a receiving system according to a second embodiment based on the present invention, and FIG. 10 is a RAM section FIG. 11 is a diagram showing a detailed example of a circuit that realizes the configuration schematically shown in FIG. 10, FIG. Priority storage register 35 on the output side of
Figure 13 is a circuit diagram showing the details of 1, and Figure 13 shows the priority storage register 31 on the input side of the receiving system.
1 shows the details of circuit diagram 1, and Figure 14 shows the priority storage register 35 on the output side of the receiving system.
Figure 15 shows a schematic block M of a conventional multiplex packet communication system, Figure 16A shows a general packet format, and Figure 16B shows a case where a priority packet interrupts a non-priority packet. FIG. 2 is a diagram showing an example of a conventional packet formant. In the figure, 30...transmission line, 100...transmission system, 1
DESCRIPTION OF SYMBOLS 10... Packet memory, 120... Flag addition circuit, 130... Input selection part, 140... Output control part, 150... Note jQ part, 160... Output selection part, 200...・Reception system, 210... Packet memory, 220... Flag detection circuit, 230... Input selection section, 240... Input control section, 250... Recording section, 260... Output selection section .

Claims (1)

[Claims] 1. A multiple packet communication system that multiplexes and transmits a series of packets, each having a priority, from a transmitting system (100) to a receiving system (200) via a transmission path (30), The transmission system (100) includes memories (110-1 to 110-n) in which packets corresponding to each priority are written.
a packet memory (110) consisting of a normal flag (F) or a packet delimiter flag (110) for each said packet;
a flag adding circuit (120) for adding IF);
When a second packet with a higher priority occurs during the transmission of the first packet read from one of the memories, the transmission of the first packet is interrupted, and
The packet delimiter flag (IF) is added to the second packet.
The receiving system (200) transmits the normal flag (F) added to the packet transmitted from the transmitting system (100).
Alternatively, a flag detection circuit (220) for identifying a packet delimiter flag (IF) and a memory (210-1 to 210-2) for writing the received packet in accordance with its priority.
and a packet memory (210) consisting of: (100), upon completion of transmission of the second packet, the normal flag (F) is added to the first packet.
The transmission of the remaining part of the packet is resumed, and the receiving system (2
00), the detection of the normal flag (F) causes the first
A multi-packet communication system characterized in that the reception of the remaining portion of the packet is resumed. 2. The transmission system (100) stores each of the packets in the memory (110-1 to 110-n) corresponding to its priority.
), an output selection section (160) that reads packets from a predetermined one of the memories (110-1 to 110-n), and an output control section (160) that controls writing and reading of packets. 140), and a storage unit (150) for saving the priority of the first packet whose transmission is interrupted by the second packet in preparation for restarting transmission of the first packet, System (200)
is an input selection unit (210-1 to 210-n) that writes each packet to the memory (210-1 to 210-n) corresponding to its priority order;
230) and a predetermined one of the memories (210-1 to 210
- an output selection unit (260) that reads out packets from n), an input control unit (240) that controls writing and reading of packets, and a priority order of the first packet whose reception is interrupted by the second packet. 2. The communication system according to claim 1, further comprising a storage section (250) for evacuating the first packet in preparation for restarting reception of the first packet. 3. In the transmission system (100), the memory (11
0-1 to 110-n) is FIFO (First In
First Out) memory (111-1 to 111-n
), and in the reception system (200), the memories (210-1 to 210-n) are FIFO memories (21
1-1 to 211-n). 4. In the transmission system (100), the input selection section (
130) is an input control circuit (131) that generates a write clock (WC), and a write circuit that controls supply or stop of supply of the write clock (WC) to each of the FIFO memories (111-1 to 111-n). clock gate (13
2), and a decoder (133) that detects the priority order in the packet and opens the corresponding one of the write clock gates (132);
0) represents each of the FIFO memories (111-1-111-
The output control unit (140) includes a read clock gate (161) corresponding to the FIFO memory (161), and the output control unit (140)
11-1 to 111-n), and the read clock gate corresponding to the high priority FIFO memory (111-1 to 111-n) (161) and saves the priority to the storage unit (150), and supplies the read clock (RC) to the FIFO memory through the read clock gate (161) which is opened. The communication system described in Section 3. 5. In the reception system (200), the input selection section (
230) each of the FIFO memories (211-1 to 21
a write clock gate (232) that controls the supply or stop of supply of a write clock (WC) to 1-n);
a decoder (1) that detects the priority of the received packet and opens the corresponding one write clock gate (232);
Upon reception of the packet delimiter flag (IF), the input control unit (240) saves the priority of the second packet in the storage unit (250), and the write clock (233). an input control circuit (241) that generates a packet (WC); and a packet presence/absence signal (PE) that indicates the presence or absence of a packet in each of the FIFO memories (211-1 to 211 to n).
is received and the corresponding FIFO memory (211
-1 to 211-n), and the output selection section (260) is controlled by the output control circuit (242) to The FIFO memory (211-1 to 211-2)
Claim 3 consisting of a read clock gate (261) for sending a read clock (RC) to
Communication system as described in Section. 6. In the transmission system (100), the flag adding circuit (120) consists of a normal flag generator (121) and a packet delimiter flag generator (122), and operates under the control of the output control circuit (141). 5. The communication system according to claim 4, wherein the normal flag (F) or the packet delimiter flag (IF) is added to the packet. 7. In the reception system (200), the flag detection circuit (220) includes a normal flag detector (221) and a packet break flag detector (221) and a packet break flag detector (221) that detect the normal flag (F) and the packet break flag (IF), respectively. 2
22), and the normal flag reception notification (
FR) and packet delimiter flag reception notification (IFR)
6. The communication system according to claim 5, wherein the input control circuit (241) receives: 8. The priority order is written in the header (H) of each packet, and the logical channel number analysis unit (180)
2. The communication system according to claim 1, wherein each of the priority orders is set in the following manner. 9. In the transmission system (100), the memory (11
0-1 to 110-n) are RAM (Random Ac
The receiving system (200) consists of a memory area obtained by dividing the memory of the receiving system (200) into n pieces.
, the memories (210-1 to 210-n) are R
3. The communication system according to claim 2, comprising a memory area obtained by dividing the memory of the AM section (213) into n areas. 10. In the transmission system (100), the input selection section (130) includes an input pointer table section (130) that cyclically accesses and writes to each of the divided memory areas.
35), and the input pointer table section (
135) stores the priority order of the second packet to be transmitted with priority and the priority order of the first packet to be saved, and specifies the corresponding one of the divided memory areas according to the priority order. The output selection section (160) includes an output pointer table section (163) that cyclically accesses and reads out each of the divided memory areas, and the output pointer table section (163) includes an input side priority storage register. 163), stores the priority of the second packet to be transmitted with priority and the priority of the first packet to be saved, and identifies the corresponding one of the divided memory areas according to the priority. 10. The communication system according to claim 9, comprising an output priority storage register. 11. In the reception system (200), the input selection section (230) includes an input pointer table section (2) that cyclically accesses and writes to each of the divided memory areas.
37), and the input pointer table section (
237), stores the priority order of the second packet to be received with priority and the priority order of the first packet to be saved, and specifies the corresponding one of the divided memory areas according to the priority order. The output selection section (260) includes an output pointer table section (263) that cyclically accesses and reads out each of the divided memory areas; 263), stores the priority order of the second packet to be received with priority and the priority order of the first packet to be saved, and identifies the corresponding one of the divided memory areas according to the priority order. 10. The communication system according to claim 9, comprising an output priority storage register. 12. In the transmission system (100), the output control section (140) is composed of an output control circuit (143), and the flag adding circuit (120) is a normal flag generator (121).
and a packet delimiter flag generator (122), and the output control circuit (143) controls the output pointer table section (163) and the RAM section (113) while outputting data from these flag generators (121, 122). 11. The communication system according to claim 10, wherein an output flag is added to the packet. 13. In the receiving system (200), the flag detection circuit (220) includes a normal flag detector (224) that detects the normal flag (F) and a packet delimiter flag detector that detects the packet delimiter flag (IF). vessel(
225), which forms part of the input selection section (230), and includes the input pointer table section (237) and the RAM section (213).
12. The communication system according to claim 11, wherein the detection flag from the flag detector (224, 225) is transmitted to an input control circuit (236) that controls the input control circuit (236).