JPS6322518B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a one-wire remote control system that performs control by sending various control signals through a single transmission path. A one-wire remote control device suitable for remote control of a car radio, etc., connects the transmitting section (remote controller) on the operation section side to the receiving section on the radio receiver body side, such as power on/off, AM / FM switching, volume up, down, etc. various control signals are transmitted over one wire, that is, a single transmission path. The present invention simplifies the configuration of such a one-wire system and improves its reliability. That is, the present invention includes a transmitter that converts N-bit parallel input information into N-bit serial output information and transmits the same, and a receiver that converts received N-bit serial input information into N-bit parallel information and receives the same. In the one-wire remote control method, which connects and controls with a single transmission path,
The transmission line is composed of an optical fiber, and the transmission signal format on the transmission line is a pattern in which one frame has a transmission period of N bits and a pause period of a predetermined length of time, and the pause period is at the beginning of one frame. The frame structure is such that a start code of the opposite level is placed, a stop code is placed at the end, and an n (<N) bit data code and a parity code are inserted between them. 2 corresponds one-to-one with turning on and off of the required equipment.
The present invention is characterized in that the serial data code is read in the receiving section at the center of the code by a receiving side clock synchronized with the start code. This will be explained in detail with reference to. FIG. 1 is a block diagram showing an overview of the present invention.
0 is a transmitter, 20 is a transmission line (optical fiber), 30
is the receiving section. When applied to a car radio, the transmitting section 10 is placed in the driver's hand, and the receiving section 30 is placed on a dash board or the like on the vehicle body, and the transmission path 20 connecting them has a length of several meters. , electrical noise such as ignition noise from the engine may enter the transmission path. If the transmission line 20 is an optical fiber, such noise will not be mixed in, which is advantageous in terms of S/N ratio. The transmitter 10 includes a clock oscillator 11 that generates a transmit clock _CK1 (1KHz) that determines the data transmission speed;
Switch SW ₁ to generate transmission data D ₁ to D _12
SW12 , N bits (in this example, N=
16) Parallel/serial conversion register 12, transmission data
A transmission control section 13 that follows SD' with a pause period of a predetermined length, a parity data generation section 14 that generates a parity code PT for the read parallel data _D1 to _D12 , and a parity data generation section 14 that generates a parity code PT for the read parallel data D1 to D12. a gate 15 for inserting a parity code PT into (described later);
It consists of an output section (not shown) that converts the output SD of the gate 15 into an optical signal. The receiving section 30 has an input section (not shown) that photoelectrically converts the optical signal received via the transmission path 20 to obtain serial reception data RD. 31 is a reception clock CK ₂ (8K
32 is a data detection unit that discriminates between a data section and a rest section from the received signal, 33 is a clock oscillator that generates a read (shift) clock _CK3 (1KHz) for the received data, and a parity check timing. 34 is a 16-bit serial/parallel conversion register that converts the received serial data RD into parallel data; 35 is a 16-bit serial-parallel conversion register that confirms whether or not the 16-bit serial data RD has been reliably read; The data checking section 36, which checks for errors using parity bits, is a latch that takes in 12 bits of data _D1 to _D12 from the checked code string of one frame using a latch signal RT. FIG. 2 is a waveform diagram, and a indicates the format of the transmission signal. Serial data (16 bits) on the transmission line 20 is inserted into a transmission period (16 mS), and a 16 mS pause period (all "1") is provided between each data period. Figure 2b shows the data interval (1
frame) data format, with a start code ST (“0”) as the first bit and
The 15th and 16th bits have a 2-bit stop code SP (both "1"), which realizes an asynchronous synchronization system. That is, the start code that comes after the rest period is the L level after the H level that lasted for a predetermined length.
level (reverse level), it can be reliably identified, and synchronized timing can thereby be obtained. Data codes D ₁ to _{D 12} for the second and third bits
is inserted, and the parity code PT is inserted in the 14th bit.
1 bit is inserted. In this example, even parity is adopted, and if the number of "1"s in data D ₁ to D ₁₂ is even, PT="0", and if it is odd, PT="1". The data D ₁ to _{D 12} are generated when the switches SW ₁ to SW ₁₂ in FIG.
Figure c shows the case when these are all off (input off). Similarly, b turns on only switch SW ₅ (D ₅
="0"), e is switch SW ₅ , SW ₁₂
is turned on (D ₅ =“0”, D ₁₂ =“0”). 2C to 2E all show normal waveforms, but if an error occurs during the transmission process, the total number of "1"s included in the data D ₁ to D ₁₂ and the parity code RT will be an odd number. Generally, the data is n bits (in this example, n=
12), and the false reception rate of data with vertical parity bits added is n+1C ₂・P ² _e (1−P _e ) ⁿ⁻¹ +n+1C ₄・P ⁴ _e (1−P _e ) ^n-3 +n+1C ₆・P ⁶ _e (1-P _e ) ^n-5 +... Here, if 1≫P _e , the false reception rate can be expressed as n+1C ₂ ·P ² _e (1−P _e ) ^n-1 = n(n+1)/2P ² _e . Since the false reception rate of n-bit data without check bits is approximately nP _e (1-P _e ) ^n-1 ≒nP _e as 1≫P _e , the parity bit improves the error rate by n+1/2P _e. can do. Next, an embodiment of the present invention applied to a separate type electronically tuned radio will be described with reference to FIGS. 3 to 6. FIG. 3 shows a specific example of the transmitter 10, in which data D ₁
The types of ~ _D11 are as shown in the table below.

[Table] Here, the word "static" in the "output" column means that the switch is configured as an on/off dual stable type, and the output level is continuously H or L. LOCAL/DX, which controls power on/off, AM/AF selection, and attenuator insertion/removal, etc., fall into this category.The term "pulse" means that the switch is on only while the switch is pressed, and therefore the output level remains unchanged during the period when the switch is pressed. It is H only, and L when you stop pressing it. Volume increase/decrease, left/right balance,
This applies to before and after the feeder. In this way, each bit D ₁ , D _{2 .} . . of the transmission data has a one-to-one correspondence with whether the controlled device is turned on or off, and a plurality of bits do not determine one operation. In other words, since it is not encoded, there is no need to decode it on the receiving side, just the H,
Predetermined control is immediately performed at the L level. With this method, one control signal or multiple control signals can be transmitted simultaneously, and there will be no interference or interference with each other. In order to avoid malfunctions, switches with contradictory operations such as VOL UP and DOWN are combined into one seesaw type switch so that only one of them is transmitted. The clock oscillation circuit 11 is composed of a crystal oscillation circuit and a divider, and outputs a 1KHz transmission clock _CK1 . The parallel/serial conversion register 12 converts 16-bit parallel input data into 16-bit serial output data SD'. The up counter 13a and the flip-flop FF ₁ constitute the transmission control section 13, and the counter 13a counts the clock CK ₁ , and as shown in FIG. Generates output D divided by 16. The flip-flop FF ₁ further divides the frequency of the output D divided by 16 by 2 to generate an output Q ₁ obtained by dividing the frequency of the clock CK ₁ by 32, that is, an output P/S which determines the transmission period S and the pause period P. flip flop
FF ₂ and Noah Gate G ₁ are parity data generation section 14
Configure. Flip-flop FF ₂ is transmit data
SD' is inverted by the shift clock of the register 12 every time "1" of the captured data SD' is input. The transmitted data SD′ is the 14th data in which the parity code PT is inserted.
The bit is forcibly fixed to "0". The transmission data SD' in this example is all "1", that is, indicates input off. T in FIG. 4 is the parity timing indicating this 14th bit. flip flop
At the output _Q2 of _FF2 , the value of the 14th bit of the clock _CK1 is the parity code PT (“0” in this example), which is passed through the gate _G1 to the NOR gate _G2.
It is inserted into the 14th bit of data SD' (gate 15 in FIG. 1). Therefore, the output SD of gate G ₂
becomes the completed serial transmission data. 16 is data
This is an output section that converts SD into an optical signal, and resistors R ₁ ,
It consists of R ₂ , transistor TR ₁ , and light emitting diode LED. And transistor TR ₁ is data SD
Accordingly, when the diode LED is turned on and off, current flows intermittently through the diode LED, and the modulated light ν is transmitted to the receiving section 30 through the optical fiber 20 shown in FIG. FIG. 5 shows a specific example of the receiving section 30. First, received light is converted into an electric signal (serial data) RD by a phototransistor or photodiode of the input section 30. The serial data RD is supplied to the serial/parallel conversion register 34 and is also supplied to the flip-flops FF ₃ and FF _{4 .}
You will also be guided to The clock generation circuit 31 generates a receive clock CK 2 (8KHz) which is 8 times the transmit clock CK ₁ using a crystal oscillator circuit and a divider, and generates a receive clock CK ₂ (8KHz) which is 8 times as large as the transmit clock CK ₁ .
3a. Flip-flop _FF3 constitutes a data detection section 32, and is set when it detects "L" of the start signal ST of received data RD (actually detects "H" since it is inverted by an inverter). FIG. 6 shows this state, where 1 is the general timing and 2 and 3 are detailed timings (enlargement and reduction). flip flop
When FF ₃ is set and the output Q ₃ becomes "H", the counter 33a becomes operational. If the clock CK ₂ at Q ₂ =H is CK' ₂ , then the counter 33a
The composite value of the 2-divided output A to 8-divided output C (・
B.), that is, the output CK ₃ of ANDGADE G ₃ is 1K
This pulse has a frequency of Hz and is located at the center of each pulse of the transmitting clock _CK1 . When the data RD is read into the register 34 using this as a shift clock, since the clock _CK3 is the above timing, the data RD will be sampled at approximately the center of its pulse width. This gate _G3 and the counter 33a constitute the reception control section 33, and the counter 33
The frequency-divided output of a is also used in other places. For example, the divided-by-16 output D and the divided-by-256 output H are led to an AND gate _G4 , which generates a signal RS that resets the flip-flop _FF3 . AND gates G ₅ and G ₆ and flip-flop FF ₄ constitute a data check (parity check) section 35. That is, the flip-flop _FF4 is driven by the shift clock _CK3 , and every "1" of the received data RD, the output ₄ is inverted to generate a parity bit, and the data _G5 is a start code ST, a received parity code PT, a stop code SP, and a parity bit. Output ₄ of flip-flop FF ₄
As input, the quality of the frame structure and the presence or absence of code errors are detected. If everything is good, open gate _G6 and output C of up counter 33a,
Latch signal when H matches (at the end of frame)
Generate RT and latch the contents of register 34 36
Incorporate into. The output of latch 36 controls on/off of the controlled device connected to the terminal. The output of this latch circuit is held until the next data period, and is updated every 32 seconds during remote control. The one-wire system of the present invention described in detail above can transmit a large amount of parallel data from the transmitting section to the receiving section using only a single transmission path, but it also has the following advantages. (1) Pause the transmission format,
Since the start-stop synchronization method in which transmission is repeated and the parity check method are adopted, the configuration is simplified by asynchronous transmission, and reliability is improved.
(2) Since the transmitted data is transmitted one-to-one without being encoded like a TV remote control,
Even if multiple inputs are received at the same time, they are transmitted as is and latched by the receiver. In the case of a coded system, there are multiple inputs; for example, if two switches are pressed by mistake, a combination of them will be output, and control that is different from the intended control will be performed or will not operate at all. In order to prevent this, a priority circuit is provided, but in the system of the present invention, even if two switches are pressed, each piece of information is transmitted and only two controls are performed as described above. Therefore, the method of the present invention reduces the malfunction rate.
(3) does not have high transmission efficiency, but since it is serial transmission, multi-bit data can be transmitted without increasing the number of transmission paths, and various controls that are practically sufficient for remote control can be performed. (4) Since light is used as a medium for data transmission, it is resistant to electrical noise, and has great advantages especially when applied to in-vehicle equipment.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the outline of the present invention, Figure 2 is a block diagram showing an overview of the present invention.
The figure is a time chart showing the transmission format and frame structure, Figures 3 and 4 are block diagrams and waveform diagrams showing a specific example of the transmitter, and Figures 5 and 6 are block diagrams showing a specific example of the receiver. and a waveform diagram. In the figure, 10 is a transmitter, 20 is a transmission line (optical fiber), 30 is a receiver, ST is a start code, and D ₁ to
_D12 is a data code, ST is a parity code, and SP is a stop code.

Claims (1)

[Claims] 1 A transmitter that converts N-bit parallel input information into N-bit serial output information and transmits it, and a
In the one-wire remote control system, which performs control by connecting a single transmission path to a receiver that converts serial input information of bits into N-bit parallel information and receives it, the transmission path is constructed of optical fiber, and The transmission signal format on the transmission path is one frame N.
The pattern is such that the bit transmission period and the pause period of a predetermined length of time repeat alternately, and a start code of the opposite level to that of the pause period is placed at the beginning of one frame, and a stop code is placed at the end of the frame. The frame has a structure in which an n (<N) bit data code and a parity code are inserted in between, and the data code is composed of a binary signal that corresponds one-to-one to the on/off state of the device to be controlled. A one-wire remote control system, characterized in that reading of a serial data code is carried out at the center of the code by a receiving clock synchronized with the start code.