JPS63219252A - Multilevel qam communication system - Google Patents

Abstract

PURPOSE:To improve an error rate characteristic with comparatively simple constitution, by providing a required error correction encoder/decoder in the inside of a differential logic. CONSTITUTION:In a multilevel Quadrature Amplitude Modulation(QAM) communication system on which the differential ligic is applied setting a multivalue as Z<n>, the error correction encoder 2 which performs error encoding independently for each of (n) series is provided in the inside of a differential logic part 1 on a transmission side, and a multilevel QAM signal is transmitted via the encoder 2 and a transmission modulation part 3. Also, on a reception side, the error correction decoder 5 is provided in the inside of a differential logic part 6 similarly. ln such a way, the expansion of a one-bit error to a two-bit error due to the continuance of the one-bit error which occurs in a case where the error correction encoder/decoder is arranged outside the logic can be prevented from being generated, thereby, no two-bit error correction circuit, etc., is required, and it is possible to heighten an error rate characteristic with comparatively simple constitution.

Description

[Detailed Description of the Invention] [Summary] In the multi-level QAM borrowing system, differential logic is applied and
Inside the differential logic, error correction encoding is performed on the transmitting side and error correction decoding is performed on the receiving side independently for each of the n sequences when the multilevel number is 2n, and it is a relatively simple method. This configuration can improve the error rate characteristics in the multilevel QAM Ill communication system.

[Industrial application field]

The present invention relates to a multilevel QAM communication system for transmitting digital signals using multilevel orthogonal amplitude modulation.

Multivalued CAM (Quadrature Amplitude
The (orthogonal amplitude modulation) communication system transmits a multi-level QAM signal that is a combination of orthogonal m-value amplitude modulation signals of I and Q channels, and this multi-level QAM signal has m2 ( = 2") signal points. For example, if m = 8 (n = 6), then 6
It becomes a 64-value QAM signal with 4 signal points, m=1
6 (n=8), 256 with 256 signals
It becomes a value QAM signal.

On the receiving side, a carrier wave is regenerated from this multilevel QAM signal,
Demodulation is performed using regenerated carrier waves whose phases are orthogonal to each other, and multi-level level identification is performed.1. A total of n series of digital signals of Q channel signals are obtained. In that case, the pull-in phase of the reproduced carrier wave is 0 degrees.

Since there is a phase uncertainty of 90 degrees, 180 degrees, or 270 degrees, a common method is to apply differential processing to the transmitted signal. Furthermore, a Gray code is employed so that the identification error between adjacent signal points is within 1 bit.

In the multilevel QAM communication system, the transmission capacity can be increased by increasing the number of levels, but on the other hand, the deterioration of error rate characteristics due to noise and transmission distortion becomes significant. Therefore, there is a need for a system in which the error rate characteristics do not deteriorate even when the number of multilevel values is increased.

[Conventional technology]

As described above, conventional multilevel QAM communication systems generally employ differential logic so as not to be affected by the phase uncertainty of the recovered carrier wave on the receiving side.

Also, when m = 8 (n = 6), the signal points are in each quadrant (I) divided by the I and Q axes, as shown in Figure 4.
There are 16 pieces in each of ~(IV), making a total of 64 pieces.

Also, Gray codes are used for the codes of signal points in each quadrant (I) to (IV), and the codes of adjacent signal points differ by only 1 bit, so even if there is an error, it will be a 1-bit error. becomes.

Furthermore, even if the arrangement of signal points shown in Fig. 4 is rotated by an integral multiple of 90 degrees, the code arrangement in each quadrant (I) to (TV) will be the same, that is, the code arrangement will be rotationally symmetrical. In many cases, a method is adopted in which the sign of each signal point is selected. With this rotationally symmetrical code arrangement, differential logic is applied only to the two bits representing the quadrant, so differential logic processing becomes simple.

[Problem that the invention seeks to solve]

As the multilevel number 2fi of the multilevel QAM signal increases,
The bit error rate increases for the same S/N. For example, in FIG. 5, curve a is 4-phase QAM (4-phase PS
(equivalent to K), b is 16-value QAM, C is 64-value QAMSd
shows the characteristic curve of the theoretical value of each bit error rate of 256-value QAM, and the actual focus error rate in the case of 64-value CAM is larger than the theoretical value as shown by the dotted line curve e, and the curve C is shifted. Approximate characteristics. This 64-value QA
In 256-value QAM where the number of multi-values is larger than M, the actual bit error rate becomes even larger than the theoretical value, as shown by the dotted curve f, and shows a different tendency from the theoretical value curve d. becomes. That is, even if the S/N is increased, the actual bit error rate decreases only slightly compared to the theoretical value.

It has been proposed to use an error correction code in order to improve the deterioration of bit error rate characteristics when the multi-level number 2n is increased as in the case of H.256-level CAM. That is, the bit error rate is improved by performing bit error correction encoding on the transmitting side and performing bit error correction decoding on the receiving side.

When applying such an error correction code, it is conceivable to provide a bit error correction code/decoder outside the differential logic. That is, on the transmitting side, differential logic is applied after performing error correction encoding, and on the receiving side, after performing differential logic decoding, error correction decoding is performed.

However, in this method, a 1-bit error is expanded to a consecutive 2-bit error. It is essential to use them in combination. In general, a 2-bit error correction code has the disadvantage that it has about twice the redundancy as a 1-bit error correction code, and also significantly increases the scale of the decoding circuit. on the other hand,
Since consecutive 2-bit errors become 1-bit errors, it is possible to decode correctly even if a 1-bit error correction code is used, but in that case, the signal received first is held until the decoding is completed. This has the disadvantage of increasing the circuit scale.

Contrary to the above, it is also conceivable to provide a bit error correction code/decoder inside the differential logic. That is, on the transmitting side, error correction encoding is performed after applying differential logic, and on the receiving side, differential logic is applied after performing bit error correction decoding.

In this case, the differential logic is for eliminating the influence of phase uncertainty of the recovered carrier. When bit error correction coding is performed after applying differential logic, it is necessary to use an error correction code, a so-called transparent code, that allows correct error correction even if the signal is inverted. The codes in this case can be divided into binary codes and multi-element codes. The latter multi-dimensional code has restrictions on its code system due to its relationship with rotationally symmetric codes, and only a few types of code systems are currently known. Furthermore, since it is necessary to perform multiplication and division of multiple elements, there is a drawback that the circuit configuration becomes complicated.

Furthermore, if the former binary code is applied as is, it does not match well with rotationally symmetric codes and has the disadvantage that it cannot correct errors that cross quadrants.

The present invention aims to enable transparent error correction coding and decoding and improve the error rate in multilevel QAM communication.

[Means for solving problems]

The multilevel QAM communication system of the present invention has an error correction code/decoder provided independently for each series inside the differential logic, and will be explained with reference to FIG. When the multilevel number is 2n, the differential logic unit 1 performs differential logic on n-bit data D1 to Dn on the transmitting side. The output is subjected to error correction coding independently by the n-series error correction encoder 2 and is applied to the transmission modulation section 3. In the transmission modulation section 3,
③ Multi-level conversion is performed by DA conversion etc. for each Q channel, and this I
, Q channel signals are modulated by mutually orthogonal carrier waves and then combined to form a multilevel QAM signal and send it out.

On the receiving side, a reception demodulator 4 performs carrier wave recovery from the received multi-level QAM signal, demodulates it using mutually orthogonal recovered carrier waves, performs multi-level discrimination by AD conversion, etc., and obtains a total of n bits of data. . The error correction decoder 5 independently corrects bit errors in n series of the outputs, and inputs them to the differential logic decoding section 6, where differential logic decoding is performed and n-bit data D1 to Dn are output.

[Effect]

Differential logic is applied to the differential logic by the differential logic unit 1, and transparent error correction encoding is performed independently for each sequence on the output thereof, so that the relationship in which the differential logic is applied is maintained and the transmission modulation unit 3 Transparent error correction encoding is performed between the differential logic unit 1 and the transmission modulation unit 3. Furthermore, since the error correction code is a binary code, the circuit configuration is also simple. Also, on the receiving side, an error correction decoder 5 is provided between the reception demodulation section 4 and the differential logic decoding section 6, and error correction is performed independently on each series of demodulated output to improve the bit error rate. is improved and the relationship applied with differential logic is maintained and applied to the differential logic decoding section 6, so decoding can be performed that eliminates the influence of phase uncertainty of the reproduced carrier wave.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of the essential parts of the transmitter of the present invention, and shows the case of a 256-value CAM where n of the multi-value number 2'' is 8. In the figure, 11 is a differential logic department,
12-1 to 12-8 are error correction encoders, 13 is a D/A converter, 14.15 is a low-pass filter, 16.17 is a modulator, 18 is a π/2 phase shifter, and 19 is a reference carrier wave. generator, 2
0 is a synthesizer.

The eight series of transmission data D1 to D8 are subjected to differential logic in the differential logic section 11. Further, if necessary, encoding is performed to provide a rotationally symmetric code arrangement for intra-quadrant Gray encoding. The 8 series output signals are sent to 8 series error correction encoders 12-1 to 1.
2-8, each code is converted into a code having error correction capability of 1 bit or more. For example, it is converted into a random error correction block code, and the block length is selected depending on the required error rate, redundancy, hardware scale, etc.

The output signals of the error correction encoders 12-1 to 12-8 are D/
The A converter 13 converts the signal into a 16-level analog signal. That is, 16
The signal is converted into T and Q channel signals. These two series of 16-value signals are spectrum-shaped by a low-pass filter 14.15 and then applied to a modulator 16.17.

The modulator 16 is supplied with a carrier wave from the base Y$ carrier generator 19, which is phase-shifted by 90 degrees by the π/2 phase shifter 18, and the modulator 17 is supplied with the carrier wave from the base Y$ carrier generator 19. The carrier waves are applied directly and modulation is carried out by orthogonal carrier waves in each modulator 1.6.17,
The modulated output signals are combined by a combiner 20 and 25
It becomes a 6-level QAM signal.

For signals subjected to differential logic processing by the differential logic unit 11, error correction encoding is not performed on each series at once, but transparent error correction encoding using a binary code is performed for each series. .

FIG. 3 is a block diagram of the main parts of the receiving device according to the embodiment of the present invention, in which 21 is a distributor, 22 and 23 are demodulators, and 24 is a π/
2 is a phase shifter, 25 is a carrier wave regeneration unit, 26.27 is a low-pass filter, 28.29 is an A/D converter, 30-1 to 30-
8 is an error correction decoder, and 31 is a differential logic decoder.

The received 256-value QAM signal is split into two parts by a divider 21 and applied to demodulators 22 and 23, respectively, and the recovered carrier wave from the carrier wave regeneration unit 25 is directly sent to the demodulator 23 and the demodulator 24 is sent to the phase shifter. 24, demodulated into I and Q channels by phase detection, harmonic components removed by low-pass filters 26 and 27, and added to A/D converters 28 and 29. Although the carrier wave regenerating section 25 in this embodiment has a configuration in which the carrier wave is regenerated using the outputs of the A/D converters 28 and 29, various other known configurations may also be used. Of course it is possible.

A/D converter 28.2 via low pass filter 26.27
The demodulated signals of the I and Q channels of the 16-level level added to the I/Q channel are converted into digital signals of 4-bit configuration, and are applied to the error correction decoders 30-1 to 30-8, respectively, and are converted into error correction codes on the transmitting side. The decoding corresponding to the encoding by the decoders 12-1 to 12-8 is performed, bit errors are corrected, and the resulting data is applied to the differential logic decoding unit 31.

The differential logic decoding unit 31 decodes the differential logic to remove the influence of the 90 degree phase uncertainty of the recovered carrier wave in the carrier wave recovery unit 25, and when delay encoding is performed on the transmitting side. decodes a signal with an intra-quadrant Gray code rotationally symmetric code arrangement and outputs data D1 to D8.

The error correction decoders 30-1 to 30-8 are A/D converters 2
8.29, the 16-level demodulated signal is converted into a 4-bit digital signal, and the error correction is performed for each focus series, and it does not change the relationship of the differential logic, so the differential logic The decoding unit 31 can perform processing to remove the influence of phase uncertainty of the reproduced carrier wave.

The above embodiment shows the case where the multilevel number 2 is 256, but it can also be applied to a case where the multilevel number is even larger, such as a 1024-value QAM signal with n-10. It is something.

Although the case where intra-quadrant Gray encoding is performed on a signal subjected to differential logic is described above, the present invention is not necessarily limited to this, and other encoding may be performed. In that case, of the differential logic encoding section and the differential logic decoding section, the section related to encoding described in "2" may be changed depending on the type of encoding.

〔Effect of the invention〕

As explained above, the present invention provides a multi-value QAM communication method 2 in which the multi-value number is 2n and multi-value QAM signals subjected to differential logic are transmitted. An error correction code/error correction code is located between the differential logic unit 1 of A decoder, that is, an error correction encoder 2 and an error correction decoder 5, is provided.Compared to the case where an error correction code/decoder is provided outside the differential logic, ■Bit error correction code is used. This has the advantage of simplifying the configuration.

Compared to the case where an error correction code/decoder is provided inside the differential logic and a multi-dimensional code is used, in the case of a binary code, the configuration of error correction coding and decoding is simplified. Furthermore, there is an advantage that relatively many types of error correction codes can be used as so-called transparent codes that can perform error correction even when there is phase uncertainty of a reproduced carrier wave.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram of main parts of a transmitter according to an embodiment of the invention, FIG. 3 is a block diagram of main parts of a receiver according to an embodiment of the invention, and FIG. is 64-value QA
An explanatory diagram of the code arrangement of M, and FIG. 5 is a bit error rate characteristic curve diagram. 1 is a differential logic section, 2 is an error correction encoder, 3 is a transmission modulation section, 4 is a reception demodulation section, 5 is an error correction decoder, and 6 is a differential logic decoder.

Claims (1)

[Claims] In a multi-value QAM communication system in which the number of multi-values is 2^n (n = positive integer) and differential logic is applied, inside the differential logic, for each of the n series, A multilevel QAM communication system characterized by having an error correction code/decoder that independently encodes and decodes error correction codes.