JPS63213198A - Read only memory circuit - Google Patents

Abstract

PURPOSE:To prevent a through current and malfunction from being generated, by preventing the lowering of potential due to the off-leak current of a line in a DROM circuit from being generated by two transistors TRs inserted between the bit line and a power source. CONSTITUTION:Since the TR 101 is turned ON and the TR 102 is turned ON when a pre-charge signal PG becomes inactive, the potential of a power source line 40 is supplied to the bit line 28. Consequently, the off-leak current I0 flows from the bit line 28, but, a current supplying capacity, by third and fourth TRs 101 and 102 exceeds remarkably the current I0, therefore, the potential of the bit line 28 is held at a logic 1 without being lowered less than that of the power source line 40, and no through current more than a leak current flows from an inverter 21.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a dynamic lead-only system [
Regarding the circuit.

[Conventional technology]

FIG. 3 is a circuit diagram of a conventional example of a dynamic read-only memory circuit (hereinafter abbreviated as a DROM circuit), and FIG. 4 is its timing chip p-I.

The output terminal 36 is output by the 2-bit address signals A and B from the DROMR2M17 address input terminals 26 and 27.
, 37, 38.39, 4-bit output signal 01.02,
03, 04, bit lines 28, 29,
The address lines are connected by transistors 9, 10, 11, and 12 which supply charges from the power supply line 40 to 30 and 31, address signals A and B at the address input terminals 26 and 27, and a precharge signal PG at the precharge input terminal 25. Address decoder 41 that gives outputs to 32.33, 34.35 and address lines 32°33.34.35 ■!
(Transistors 13, 14゜15.16.17.18, 19.20 for the purpose of ice-charging the charge precharged to the bit line 28゜29.30.31
, and inverters 21.22, 23.24, etc., which invert the logic of bit lines 28.29 and 30.31, respectively, and apply the inverted logic to output terminals 36, 37, and 38.39.

Here, the address decoder 41 provides the logical values of the positive phase and negative phase of the address signals A and B to the address lines 32, 33, 34, and 35, respectively, during a period other than the precharge period. It consists of 5 to 8.

However, the functions of the internal circuit of the address decoder 41 are indicated by logical symbols, and in reality, a static ROM type circuit is often used. Further, the positions and numbers of the discharge transistors 1 to 13 to 20 are changed depending on the output cover turn.

Next, the operation of the conventional circuit shown in FIG. 3 will be explained with reference to FIG. In this conventional example, the precharge periods T+, T3 .
T5. T7 and discharge period T2. Ta, Te, T
a is repeated.

Period T1: Precharge signal PG is “0” at time t1
Then, the transistors 9, 10, 11゜12 are turned on, and the signals C1, C on the bit lines 28, 29, 30゜31 are turned on.
2, C3, and C4 are each precharged to "1", and the output terminals 36 to 3 outputs 01 to 04 are It OII
becomes. Note that the address lines 32, 33, 34 during this period
．． The logical value of 35 becomes °°O'' by setting the outputs of NOR gates 5, 6, and 7.8 to 0'' by the precharge signal PG.
Therefore, discharge transistor 13.14.15
．． 16, 17, 18, 19°20 are all off. Also, address signals A and B change within this discharge precharge period T1, and 8-0+1, 8, 11
011 is input.

Period 2: Precharge signal PG becomes II 1 at time t2
+1, precharge transistor 9.10
．． 11.12 will be off. At the same time, Noah Gate 5.6.
7.8 becomes active and address lines 32, 33, 3
4.35, signals A, input, B, and Ill are output, respectively, and A="l Q Tl.

Since B="O°', transistors 16, 18° 19.20 whose gates are connected to the address line 33.35 are on, and transistors 13, 15° 14. whose gates are connected to the address line 32.34 are turned on. 17 is turned off.As a result, the charges on the bit lines 29, 30, 31 are discharged, and only the charges on the bit line 28 are held.The logic value of each bit line 28, 29, 30, 31 is determined by the inverter 21.
22, 23, 24 and the output terminals 36, 37 .
Output at 38.39.

Period T3: When the precharge signal becomes O11 again at time t3, bit lines 28, 29, 30 .
31 is precharged, and the address signals Δ and B change to A="O" and B-1".

Period T4: At time t4, precharge signal PG is LL 1
11, similarly to the precharge period T2, the precharge transistors 9.10 and 11.12 are turned off, and at the same time, the output of the address decoder 41 turns on the discharge transistors 14.17 and 18.19, and discharges. Transistor 13, 15, 16゜2
0 is off, which causes bit rA28°30.
The charges on bit line 31 are discharged, and only the charges on bit line 29 are held in a high impedance state. The logic value of each bit line 28, 29.30°31 is determined by the inverter 21, 2
2, 23.degree. 24 and output to output terminals 36, 37.degree. 38.39.

Period T5: At time t5, precharge signal PG becomes II O
11, the bit lines 28, 29, 30, and 31 are precharged as in the precharge period T1, and the address signals A and B are A=11111, E3=I
Changes to I Q l#.

Period T6: When the precharge signal PG becomes "1" at time t6, the precharge transistors 9, 10, 11, and 12 are turned off, and at the same time, the discharge transistor is turned off by the output of the address decoder 41. Transistor 13゜15.16.20 turns on, discharge transistor 14.17.18.19 turns off,
As a result, the charges on the bit lines 28, 29, and 31 are discharged, and only the charges on the bit line 30 are held. The logic value of each bit line 28, 29° 30.31 is inverted by an inverter 21.22° 23.24 and sent to an output terminal 36.
Output on ゜37.38.39.

Period T7: Precharge signal PG is 110 at time t7
When it comes to IT, the bit line 2 is
8, 29, 30, and 31 are precharged, and address signals A and B change to A="1" and B-111++.

Period T82 At time t8, precharge signal QPG is it 1
++, similarly to period T1, the precharge transistors 9, 10, 11, and 12 are turned off, and at the same time, the output of the address decoder 41 turns on the discharge transistors 13, 14, 15, and 17, and the discharge transistors 9, 10, 11, 12 are turned off. Transistors 16.18.19.20 are turned off, thereby discharging the charge on bit line 28.29.30 and retaining only the charge on bit line 31. The logical value of each bit a28, 29°30.31 is inverted by an inverter 21.22°23.24 and output to an output terminal 36°37.38.39.

In the operation in each of the above periods T1 to T8, the discharge period T2. Ta, T6. Strobe signal QS within Ta
TB is activated and output signal 01 is output at this timing.
．． Considering an application referring to 02, 03, 04, the conventional DROM shown in FIG. 3, that is, the output pattern of the conventional example shown in FIG.
This is an example in which only one output signal N out of 02°03.04 is 0''. In this way, in the conventional example shown in FIG. 3, the discharge transistors 13, 14, 15°16, T7,
18, 19. Swapping or adding the insertion position of 20,
By deleting the desired output pattern D
The ROM circuit is composed of transistors that determine the logic of bit lines 28 to 31, that is, transistors 13, 14, 15, 16, 17, 1 in the conventional example shown in FIG.
Since 8゜19.20 can be configured with only one type of conductivity type, it can be realized with approximately 1/2 the area occupied by an integrated circuit compared to static ROM, which also requires complementary transistors. It has the characteristic of being able to

[Problem that the invention seeks to solve]

The conventional DROM circuit described above has the advantage of being integrated into a circuit with a small footprint, but the bit lines 28, 29 .
30. When the logical value of 31 is “1”, bit line 2
Since the charge stored in the parasitic capacitance of 8.29.30.31 is held in a high impedance state, it often malfunctions and cannot be used in applications where the operating frequency is low. In other words, in this high impedance state, ideally the impedance is infinite and the bit line is 28°29.3
The charge charged to 0.31 will be held forever, but in reality, the transistor 13 for the
, 14.15.16.17゜18.19.20 There is a finite off-leak 'I■ current, and it is further coupled to other signal lines by a finite coupling capacitance, so the signal on this signal line changes. Each time, a portion of the charge is removed.

Therefore, the retained charge decreases with time, and the potential of the bit lines 28, 29, 30, 31 gradually decreases from the potential of the power supply line 40, so that when the access time of the DROM circuit is long, the state is "1". cannot hold.

FIG. 5 is a timing chart showing this holding and the drop in holding potential. Times t1 to t3 in FIG. 5 are the fourth
Corresponding to that shown in the figure, this is a case where the discharge time during period T2 is very long. In FIG. 5, only changes in the bit line 28 are shown for simplicity. In FIG. 5, during the precharge period T1, each bit line 28, 29.3-0.31 is precharged in exactly the same way as the precharge period T1 in FIG. 4, and the address signals A and B are A=11.
011r3 = 11 Q Switched to II. Fifth
In the discharge period T2 in the figure, the precharge signal PG
becomes ゛・1'' and becomes inactive, so the precharging transistors 9, 10, 11, 12 are turned off, and at the same time, the dimechanism transistors 13, 14, and 12 are turned off.
15.17 is off, discharge 1 - transistor 1
6, 18, 19, 20 will be turned on.

As a result, the charges on the bit lines 29, 30, and 31 are discharged, and the logic becomes such that only the charges on the bit lines 28 are held. Here, the transistor for distilage 13.1
Since a finite off-leakage current flows through the bit line 28, the waveform of the signal C1 on the bit line 28 tends to deteriorate over time due to the withdrawal of charge from other signal lines via old coupling damage. If the charge discharge due to this off-leakage current continues, the sum of the off-leakage currents of the transistors 13 and 14 becomes IO, the input threshold voltage of the inverter 21 whose input is the logic of the bit line 28 becomes 1, and the potential of the power supply line 40 becomes V. If Tl+ is set to 0, T= (V, o-V,,
)/[0 time later, the potential of the bit line 28 becomes lower than the inverter's input threshold voltage ■Tl+, and as the charge continues to be discharged by the off-leak current, the output of the inverter 21, that is, the output signal o1 is inverted, If the strobe signal 5sTs is activated at this point, the output signal 01="1°'.

02-1", 03="1", 04='"1
and becomes the original address signal -'I Q II,
3 = 1 The result is different from the output pattern for 0°', resulting in malfunction.

In this way, the conventional circuit shown in Fig. 3 operates without problems in applications where the operating frequency is sufficiently high, but it cannot be used in applications where the discharge Akima T2 is T2 > T, and it cannot be used in applications where the discharge Akima T2 is T2 > T. For this application, it has been necessary to use a static ROM, which occupies a large integrated circuit area. Further, in the case of the conventional circuit shown in FIG. 3, a through current flows through the inverter 21 due to a decrease in the potential of the bit tlA28, and there is a drawback that the circuit current increases even when T2<T.

[Means for solving problems]

The read-only memory circuit of the present invention has a first precharge circuit whose source is connected to a first power supply line, whose drain is connected to a bit line, and whose terminals are connected to a precharge input terminal. an address decoder inputting the signals of the address input terminal and the precharge input terminal and having its output connected to the address line;
a second transistor of a complementary conductivity type to the first transistor, the address line being connected to the gate, the source being connected to the second power supply line, and the drain being connected to the bit line; In a read-only memory circuit consisting of an inverter whose input terminal is connected to the precharge input terminal and whose output is connected to the output terminal, the source is connected to the first power supply and the gate is connected to the signal of the precharge input terminal which has the opposite phase. a third transistor of the same conductivity type as the first transistor, into which a signal is input, and a third transistor whose source is connected to the drain of the third transistor and whose drain is connected to the bit line. and a fourth transistor of the same conductivity type.

[Effect]

When the precharge signal becomes inactive, the third transistor is turned on, and the inverter inverts the logic "'1" of the precharged bit line, turning on the fourth transistor, so that the first power supply line is turned on. A potential is applied to the bit line.

Therefore, an off-leakage current flows from the bit line. Since the current supply capability of the fourth transistor is much larger than the off-leakage current, the potential of the bit line is maintained at the logic [3II 11+] without decreasing from the potential line of the first power supply line. Therefore, a through current exceeding the leakage current does not flow into the inverter, and the discharge period can theoretically be set to infinity without malfunction.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the read-only memory circuit of the present invention.

In this embodiment, in the conventional circuit shown in FIG.
, and an inverter]00 for the purpose of obtaining an inverted signal of the precharge signal PG.

FIG. 2 is a timing chart 1 showing the operation of the bit line 28 in FIG. 1.

Here, for comparison with the conventional example, the precharge and discharge periods T1 to T4 correspond to those in FIGS. 4 and 5, respectively.

Period T1: Precharge signal PG becomes II at time t1
When it becomes OII, the bit lines 28, 29, 30.31 are precharged by the precharging transistors 9, 10.11°12. At this time, the transistors 101, 103, 105, and 107 are turned off by the inverter 100, so that the transistors 101, 103, 105, and 107 are turned off from the power supply line 40.
Current path to bit line 28 via 102, current path from power line 40 to bit line 29 via transistor 103.104, current path from power line 40 to bit 'fA30 via 1 to transistor 105.106. Path and power line 40 to 1 to transistor 107,10
All current paths to the bit line 31 via the bit line 8 are circuits.

This is for the purpose of preventing more than necessary charging current when precharging the parasitic capacitance of each pin 1 to wire 28, 29, 30, and 31. Further, the address lines 32, 33, 34, and 35 all become inactive due to the output of the address decoder 41, and the discharge transistors 13 and 1 become inactive.
4°15, 16, 17, 18, 19.20 are all off.

Period 2: Precharge signal PG becomes II 1 at time t2
When it comes to II, precharging transistor 9.10
．． 11.12 are all turned off, and at the same time, the address decoder 41 turns off the discharge transistors 16.1.
8, 19, 20 are turned on, discharge transistors 13, 14 and 15, 17 are turned off, and the bit line 28 becomes a logic state in which charge is held. At this time, the output of the inverter 100 becomes "O" at the same time, which turns on the transistor 101, and the logic "1'' of the precharged bit line 28 becomes O" by the inverter 21, turning on the transistor 102. By this, power line 4
A potential of 0 is applied to the bit line 28. Therefore, an off-leakage current Io flows from the bit line 28, but since the current supply capability of the transistors 101 and 102 is much larger than Io, the potential of the bit line 28 does not decrease from the potential of the power supply line 40, and the logic ll 1 II
is retained. Therefore, a through current exceeding a leakage current does not flow into the inverter 21, and the discharge period T2 can be selected to a logical infinity without malfunction.

Period T3: Similar to period T1, bit line 28.29°30
．． 31 precharges are performed.

Period T4: At time t4, precharge signal PG becomes It1.
11, address signals A-'“O”, B-II
1 +1, the address decoder 41 turns off the discharge transistor 13 whose drain is connected to the bit line 28 and turns on the transistor 14. Further, the transistor 101 outputs a precharge signal PG=
It is turned on by "1", and at the same time, the 1-transistor 102 is turned on via the inverter 21 by the logic 11111 of the bit line 28 immediately after precharging is completed. That is,
Immediately after the precharge ends, transistors 14, 101 and 102 are all turned on for the bit line 28. Here, the current amplification factor gl of the transistors 101 and 102,
11o1. q1. By making l11o2 the same and setting the current amplification factor q of the transistor 14 to q≧9, the potential of the bit line 28 due to the voltage division by the three transistors 14, 101 and 102 of m14 m14 m101 is equal to the input threshold of the inverter 21. The voltage v1] can be lower than or equal to 1. As a result, the potential of the bit line 28 reaches the input threshold voltage vTH of the inverter 21 with a delay time of jT in FIG. 2, and the output of the inverter 21 is inverted to 1''. ~ As the transistor 102 turns off, the current path from the double line 40 through the transistors 101 and 102 is circuited, and after jT time, only the transistor 14 is turned on for the bit line 28, and the charge on the bit line 28 is reduced. fully discharged.

This state continues until the next precharge is started.

Above is the discharge period T2. T, I middle ii 1 I
If held in T and It O! The operation when the bit line is discharged to + has been explained only for the bit line 28, but the same applies to the other bit lines 29, 30, and 31, so the explanation will be omitted here.

〔Effect of the invention〕

As explained above, the present invention logically lowers the lower limit of the operating frequency by preventing potential drop due to off-leakage current in the bit line of a DROM circuit by using two transistors inserted in series between the bit line and the power supply line. is 01
Since it can operate up to 1z and can prevent through current in the gate connected to the bit line, it can also be applied to extremely low frequency circuit operation. This has the effect of providing a circuit that has the advantages of low frequency operation and low circuit leakage current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the read-only memory circuit of the present invention, FIG. 2 is a timing chart showing the circuit operation of FIG. 1, section 3 is a circuit diagram of a conventional example, and FIG. Fifth
This figure is a timing chart showing the circuit operation of the conventional example shown in FIG. 1.2, 3, 4, 21, 22, 23. 24... Inverter, 5.6, 7.8... NOR gate, 9-20. 101-108... Transistor, 25.
...Precharge input terminal, 26.27...Address input terminal, 28-31...Bit line, 32-35...Address line, 36-39...Output terminal, 40...Power line , 41...address decoder.

Claims (1)

[Scope of Claims] A first transistor for precharging whose source is connected to a first power supply line, whose drain is connected to a bit line, and whose gate is connected to a precharge input terminal; an address decoder that receives a signal from an input terminal and has an output connected to an address line; the address line is connected to a gate; a source is connected to a second power supply line; and a drain is connected to the bit line. , an input terminal is connected to the bit line and a second transistor of a conductivity type opposite to that of the first transistor;
In a read-only memory circuit configured with an inverter whose output is connected to the output terminal, the source is connected to the first power supply line, and the gate is inputted with a signal opposite in phase to the signal of the precharge input terminal. Ru,
a third transistor of the same conductivity type as the first transistor; a third transistor whose source is connected to the drain of the third transistor; whose gate is connected to the output of the inverter; and whose drain is connected to the bit line. A read-only memory circuit comprising a transistor and a fourth transistor of the same conductivity type.