JPS632116B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a cursor display method for a CRT display, in which a cursor pattern is stored in a part of VRAM, and one raster of the cursor pattern is displayed during a horizontal retrace period of the display. It attempts to read data from VRAM to a register and display it.

Conventional Technology and Problems The cursor used to indicate the input position on a CRT (cathode ray tube) display has multiple patterns, or shapes, and has different patterns for each mode to increase identification. It is convenient to use a different cursor for each window on a type of display (with a screen). A conventional CRT display control device (CRTC) has a cursor pattern memory (CPM) that stores various cursor patterns in order to make the cursor pattern variable.
It has two buses so that VRAM (RAM that can be accessed from the CRTC or CPU) and CPM can be accessed simultaneously from the side, and the area without the cursor is displayed by accessing only the VRAM, and the cursor is When the display timing comes, VRAM and CPM are accessed simultaneously to display the image and cursor. For this reason, fast CPM, applicable
The drawback is that it requires a dedicated CPM bus and other peripheral circuits.

Figure 1 shows a conventional example, where 20 stores image information.
VRAM, 21 is an address generator that specifies the address, 22 is a CRT, 23 is a cursor pattern memory (CPM) that stores various cursor patterns, 24 is a cursor position register (CSR), 25 is a comparator, 26, 27 is a parallel to serial converter, and 28 is a selection gate. CRT22 from address generator 21
Addresses corresponding to the above raster scan are sequentially generated, and image data is read from the VRAM 20.
At the same time, the address is also supplied to the comparator 25, so that when it matches the cursor position in the register 24, a cursor pattern is generated from the CPM 23. The gate 28 simply outputs the output of the P/S converter 26 while there is no output from the P/S converter 27.
When the P/S converter 27 produces an output, it is supplied to the CRT 22 along with or in place of the output of the P/S converter 26.

OBJECTS OF THE INVENTION The present invention attempts to reduce the number of cursor pattern memories and their peripheral circuits by storing cursor patterns on VRAM.

Structure of the Invention The present invention stores a cursor pattern to be displayed on a CRT screen in a memory that can be accessed by a CRT controller, and stores the cursor pattern from the memory during the retrace period of a horizontal scan immediately before the horizontal scan in which the cursor is to be displayed. Read the cursor pattern for the horizontal scan, load it into a shift register, start shifting the register at a timing corresponding to the cursor display position during the horizontal scan period, and display the output on the CRT screen together with the display data read from the memory. This will be described in detail below with reference to the illustrated embodiment.

Embodiment of the Invention FIG. 2 shows an embodiment of the invention. In the figure, 1 is the raster scanning CRT controller (CRTC)
generates a display address. The display address is, for example, a numerical value indicating the number of horizontal scans.
Reference numeral 2 denotes a timing generator which generates a timing clock that defines the operation of the entire CRT display device.
A register 3 selects and holds the cursor address of the circuit 5 and a display address of the CRTC 1, and a register 4 holds the cursor positions X and Y. Here, Y indicates the number of the scanning line, and X is a numerical value indicating the number of the pixel (dot) on the scanning line. Reference numeral 5 designates a cursor address generator, which generates the address of the VRAM 6 to store the cursor pattern during the horizontal retrace period immediately before the raster where the cursor is to be displayed, according to the Y cursor position from the register 4; During the display period, the converter 8 starts shifting. 6 holds the cursor pattern and display pixel data
It is VRAM. Reference numerals 7 and 8 designate P/S (parallel/serial) conversion units, which are specifically comprised of shift registers, into which data is loaded in parallel and outputted serially by shifting, thus performing P/S conversion. The converter 7 is for display pixels, and the converter 8 is for cursor patterns. Reference numeral 9 denotes an overlay unit that synthesizes the display pixels output from the conversion units 7 and 8 with the cursor pattern.

The cursor pattern is composed of, for example, 24 x 24 dots like the displayed characters, and can take various shapes such as rectangles, stars, arrows, etc.
) is stored in VRAM6. Raster where the cursor should be displayed (referred to as RST in Figure 3)
During the horizontal retrace period (HS) just before the cursor address (VRAM storing the cursor)
This cursor address is input to the register 3, the VRAM 6 is accessed, and the cursor pattern for one raster is read out. This is input to the cursor P/S converter 8 in parallel. period
When the signal passes through HS, the input of the register 3 is switched to the display address from the CRTC 1, and the counter provided in the address generator 5 and loaded with X starts counting down. CRTC to VRAM6
The display address from 1 is input and accessed using the address, and the read display data for one line is input to the display P/S converter 7. The converter 7 synchronizes with each horizontal scan and performs P/S conversion on the display data according to the dot timing, and the converter 8 converts the dot timing (that is, the contents of the counter 5) from the circuit 5 at which the raster cursor should be displayed. (becomes negative), the shift operation begins. As mentioned above, the counter of the cursor address generation circuit 5 starts counting down when the horizontal retrace period (HS) ends, and when the count value reaches 0 in the middle of the subsequent raster, it sends a shift pulse to the conversion section 8. Shift the cursor pattern. One-sided display P/S converter 7
is inputted with pixel (dot) information for one raster in parallel, and the cursor P/S conversion unit 8 is inputted with pixel information of the cursor area in the raster in parallel,
The shift clocks of these conversion units are synchronized with the raster, and the shift start of the conversion unit 8 coincides with the start of the cursor area on the raster, so the exclusive OR (EOR) output by the overlay unit 9 is
When input to the CRT, a cursor is displayed on the screen of the CRT together with the raster image at the position specified by the register 4. When one cursor is displayed as n×n dots, the above operation is repeated n times. For example, if one cursor is displayed with 24×24 dots, only 24 dots are displayed horizontally in one raster, and this is repeated vertically for 24 rasters, thus displaying the entire cursor.

A plurality of arbitrary cursor patterns can be stored in the VRAM 6, and since the VRAM is a memory space that can be accessed by the CPU, the cursor patterns can be stored by the CPU. Also, VRAM is 1
Since the cursor pattern can be updated for each screen, it is possible to store one type of cursor pattern and update the pattern for each screen, but if multiple types of patterns are stored in VRAM in advance, the cursor pattern can be updated for each window in a multi-window display device. Cursors of different patterns can be easily displayed, or by simply rewriting the cursor pattern address conversion table inside the circuit 5 during the vertical retrace period, a VRAM address storing a different cursor pattern can be generated and the shape can be changed for each screen. This provides advantages such as being able to display different cursors as desired. The cursor positions X and Y, which indicate which cursor pattern is to be displayed at which position, can be given to the register 4 from the CPU.

Effects of the Invention As described above, according to the present invention, a memory dedicated to cursor patterns (cursor pattern memory)
You can keep the cursor pattern in VRAM without using the
By loading a cursor pattern into the S converter), the cursor can be displayed at any dot timing and at any position, which has the advantage of reducing the number of circuits. In particular, recent memory chips have become more integrated, and there are no chips suitable for small-capacity memory for holding cursor patterns, so the effect of holding cursor patterns in a portion of VRAM is significant. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional cursor display system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a horizontal retrace period. In the figure, 1 is the CRT controller, 6 is the video
RAM 8 is a shift register for cursor patterns.

Claims (1)

[Claims] 1 Set the cursor pattern to be displayed on the CRT screen.
The cursor pattern is stored in a memory that can be accessed by the CRT controller, and during the retrace period of the horizontal scan before the cursor is to be displayed, the cursor pattern for the horizontal scan is read from the memory and loaded into the shift register. A cursor display method characterized in that the shift of the register is started at a timing corresponding to the cursor display position in the horizontal scanning period, and the output thereof is displayed on a CRT screen together with the display data read from the memory.