JPS6320631A - Register selecting system - Google Patents

Abstract

PURPOSE:To omit the labor of rewrite of an operand pointer to reduce the capacity of a control storage part and shorten the instruction execution time by exclusively controlling the operand pointer and a base register in accordance with contents of a microprogram latch, where a micro instruction is held, to refer to the micro operand. CONSTITUTION:The micro operand address obtained by decoding an instruction in a decoding part is stored in an operand pointer 3 and a base register 1 before the start of instruction execution in an executing part of contents on a data bus 11 are stored there by the control of the control storage part. A micro instruction in the control storage part is held in a microprogram latch 2 before executed, and contents of the operand pointer 3 and those of the base register 1 are exclusively controlled in bit units in accordance with these held contents and are outputted to an operand bus 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a register selection method, and particularly to a register selection method in a microprogram-controlled information processing device.

[Conventional technology]

Conventionally, in a register selection method in a microprogram-controlled information processing device, the microoperand to be referenced in the microprogram is specified either by the microprogram itself storing the microoperand address in an operand pointer, or by having a decoder decode the instruction. This was done by storing the micro-operand address obtained by the micro-operand address in the operand pointer before starting execution of the instruction in the execution unit, and transferring this micro-operand address to the micro-operand decoder via the micro-operand bus.

[Problem that the invention seeks to solve]

In the register selection method in the conventional microprogram-based information processing device described above, references to one microoperand for one operand pointer are limited to one, so when referencing a different microoperand, the microoperand must be I had to rewrite the value of the operand pointer sequentially. For example, when the lower n (positive integer) bits of the m (positive integer 8) bits of the micro-operand address access the same micro-operand, ■ consecutive micro-operand addresses, ■ lower-order n bits of the micro-operand address This method requires the following steps: masking, (1) calculating a new micro-operand address, and (2) writing to the operand pointer, which has the drawback of increasing the capacity of the control storage and increasing the instruction execution time.

In view of the above-mentioned points, an object of the present invention is to reduce the capacity of a control storage unit and reduce execution time by eliminating the need to write and recall operand pointers when referencing different micro-operands. An object of the present invention is to provide a register selection method that achieves this.

[Means for solving problems]

The register selection method of the present invention has a control memory section that stores a microprogram, and under the control of this control memory section, a microoperand address is output to the microoperand bus, and the microoperand address is decoded by a microoperand decoder for reference. In a microprogram-controlled information processing device that accesses a micro-operand to be processed, a micro-operand address obtained by decoding an instruction in a decoding unit is stored before the execution unit starts executing the instruction, or the control storage unit is controlled. an operand pointer that stores the contents on the data bus, and
Similarly, a base that stores a micro-operand address obtained by decoding an instruction in the decoding section before the execution section starts executing the instruction, or stores the contents on the data bus under the control of the control section. A register and a microinstruction in the control storage section are held before execution of this microinstruction, and the contents of the operand pointer and the contents of the base register are exclusively controlled bit by bit by the held contents, and the contents of the operand pointer and the contents of the base register are controlled bit by bit. It has a microprogram latch that outputs to the bus.

[Effect]

In the register selection method of the present invention, the operand pointer and the base register store the micro-operand address obtained by decoding the instruction in the decoding section, or store the micro-operand address obtained by decoding the instruction in the decoding section, or The above contents are stored, and the microprogram latch holds the microinstruction in the control storage section before executing this microinstruction, and uses this held contents to exclusively control the contents of the operand pointer and the contents of the base register bit by bit. Control and output to the operand bus.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The register selection method of this embodiment consists of a base register 1 that holds micro-operand addresses, and a control storage section (
a microprogram latch 2 that holds microinstructions from (not shown); an operand pointer 3 that holds microoperand addresses; microoperand address output gates 4 to 7; and a data bus 11 controlled by a control storage. It is configured to include a source micro-operand bus 18 for source operands and a destination micro-operand bus 19 for destination operands.

The base register 1 can obtain the contents on the data bus 11, and can also receive a microoperand address from a decoder (not shown) via a signal line 12 before starting execution of an instruction. . The base register 1 is also connected to the source micro-operand bus 18 via the micro-operand address output gate 4 via the signal vA14, and to the destination micro-operand bus via the signal line 14 and the micro-operand address output gate 5. It is connected to 19.

The operand pointer 3 can obtain the contents on the data bus 11, and the decoder (
(not shown) can receive and receive microoperand addresses via signal line 12. Further, the operand pointer 3 is connected to a source micro-operand bus 18 and a destination micro-operand bus 19 via a signal line 15, and is also connected to a source micro-operand bus 18 and a destination micro-operand bus 19 via a signal line 15 and a micro-operand address output gate 6, respectively. It is connected to the operand bus 18 and to the destination micro-operand bus 19 via the signal line 15 and the micro-operand address output gate 7 .

The microprogram raft 2 holds microinstructions to be executed via the signal line 13 from section 4.9 of section 1 of the system.

Further, the microprogram latch 2 is connected to the microoperand address output gates 4 and 6 via the signal line 16.
microoperand address output gates 5 and 7 via signal vA11.
are connected to each.

In addition, numeral 20 is a write permission signal for the base register 1, 21 is a write permission signal for the base register 1 and operand pointer 3, 22 is a write permission signal for the operand pointer 3, and 23 is a write permission signal for the microprogram raft 2, respectively. show. Further, reference numerals 24 and 26 indicate output enable signals for the source micro-operand bus 18, and reference numerals 25 and 27 indicate output enable signals for the destination micro-operand bus 19, respectively.Each enable signal 20.22.2
4-27 are controlled by microinstructions in the control store.

FIG. 2 is a diagram showing a more detailed circuit example of the microoperand address output gates 4 and 6. Microoperand address output gate 4 is connected to base register 1
It is composed of a combination of AND circuits and gates with the same number of bits (6 bits in the figure) as the number of bits in the microprogram, and the inverted signal of the source operand of the microprogrammer M2 and the output enable signal (BR-3-3EL) 26. The contents of the base register 1 are selectively output to the source micro-operand bus 18 bit by bit by opening and closing each gate in accordance with the logical product of .

The micro-operand address output gate 6 is composed of a combination of AND circuits and gates having the same number of bits as the operand pointer 3 (6 bits in the figure), and outputs the source operand signal of the micro-program latch 2 and the output enable signal 26. The contents of the operand pointer 1 are selectively output to the source micro-operand bus 18 bit by bit by opening and closing each gate in accordance with the logical product.

Therefore, operand pointer 3 and base register 1
each via) is exclusively controlled by the corresponding bit of the micro-operand latch 2 in response to the output enable signal 26 and is output to the source micro-operand bus 18.

Although only the micro-operand address output gates 4 and 6 are shown in FIG. 2, the micro-operand address output gates 5 and 7 are similarly constructed. However, the microoperand address output gates 5 and 7 are
The contents of the base register 1 and the operand pointer 3 are exclusively controlled bit by bit in accordance with the contents of the destination operand, and are output to the destination micro-operand bus 19.

Next, the operation of the register selection system of this embodiment configured as described above will be explained.

The micro-operand address given by the decoder is
It is transferred to the base register 1 and operand pointer 3 via the signal line 12. The write permission signal 21 is output at the end of execution of the previous instruction, and the values of the HAS register 1 and operand pointer 3 are fixed at the start of execution of the current instruction.

Now, when 0OIOLIB (B indicates a binary number), which specifies general-purpose register (OR) 11, is specified in operand pointer 3 and base register 1 at the start of instruction execution, if you change the specification to OR7. think of. First, the write enable signal 20 is activated to write 0OOIXχB into the base register 1 via the data bus 11. Next, the micro-instruction whose source operand is 000011B is written into the microprogram latch 2 by applying the write permission signal 23 from the control '4'B storage section, and the micro-operand is accessed by applying the output permission signal 26.

As a result, the source micro-operand bus 18 has 0
00111B is output as a source micro-operand address, this micro-operand address is decoded by a micro-operand decoder (U!J not shown), and OR7, which is the micro-operand to be referenced, is accessed.

In the above explanation of the operation, the case where the register is referred to as the source operand is described, but when the register is referred to as the destination operand, the output permission signal 27 can be used instead of the output permission signal 26. good.

In this way, the conventional register selection method requires the following steps: ■ Reading the operand pointer, ■ Masking the lower two bits of the micro-operand address, ■ Calculating the new micro-operand address, and ■ Writing to the operand pointer. However, according to the register selection method of this embodiment, it is possible to access a necessary micro-operand through a few steps such as (1) writing a micro-operand address to a base register, and (2) accessing a micro-operand using a micro-instruction. This is particularly effective when a microoperand address must be analyzed, such as when calculating an effective address using a microprogram.

〔Effect of the invention〕

As explained above, the present invention provides an operand pointer and a base register that hold a micro-operand address prior to execution of an instruction, and sets the operand pointer and base register according to the contents of a microprogram latch that holds a micro-instruction to be executed. Exclusively controlled? By referencing the micro-operand using I, the effort of rewriting the operand pointer can be saved, and the capacity of the control storage section and instruction execution time can be reduced.

[Brief explanation of the drawing]

The first diagram is a block configuration diagram showing an embodiment of the register selection method of the present invention, and the second diagram is a diagram showing an example of a circuit that performs exclusive control between the operand pointer and the base register shown in FIG. be. In the figure, l...Base register, 2...Micro program latch, 3...
Operand pointer, 4-7... Micro-operand address output gate, 11... Data bus, 12-17... Signal line, 18... Source micro-operand bus, 19...
. . . Destination micro-operand bus, 20 to 23 . . . Write permission signal, 24 to 27 . . . Output permission signal.

Claims (1)

[Claims] A control storage unit that stores a microprogram, and outputs a microoperand address to a microoperand bus under the control of the control storage unit, and the microoperand address is decoded by a microoperand decoder to be referenced. In a microprogram-controlled information processing device that accesses a micro-operand, a micro-operand address obtained by decoding an instruction in a decoding unit is stored before the execution unit starts executing the instruction, or data is stored under the control of the control storage unit. An operand pointer for storing the contents on the bus and a micro-operand address obtained by decoding the instruction in the decoding section are also stored prior to the start of instruction execution in the execution section, or by controlling the control storage section. A base register that stores the contents on the data bus, and a microinstruction in the control storage section that holds the microinstruction before execution of this microinstruction, and uses the held contents to convert the contents of the operand pointer and the contents of the base register bit by bit. A register selection method comprising: a microprogram latch that exclusively controls and outputs to the operand bus.