JPS63193685A - Signal processing system for digital vtr - Google Patents

Abstract

PURPOSE:To improve the quality, color reproducibility, and the responsiveness of a reproduced picture by setting the start address at every field signal of a video signal and the start sample of a line signal so that the phases of the color subcarrier wave at every field are equal to each other. CONSTITUTION:A PAL system analog video signal of is separated into two channels from an input terminal 1 through a LPF 2, a clamping circuit 3, and A/D converter 6. The phase of the start address of each field signal of a video signal and that of the start sample of a line signal are controlled by shuffling circuits 7a, 7b by using a timing signal from a timing generation circuit 5 so that the phases of the color subcarrier waves at every field come equal to each other. Output signals from the circuit 7a, 7b are time-base compressed by time base compression circuits 8a, 8b, and their outputs are sent through CRC signal adding circuits 9a, 9b and inputted to P/S circuits 17a, 17b. The outputs of the circuits 17a, 17b are supplied to rotary magnetic heads Ha, Hb through TTL/ECL circuits 20a, 20b and recorded on a magnetic tape TP.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a signal processing system for a digital VTR that records and plays back PAL digital video signals.

[Summary of the invention]

According to the present invention, in a recording circuit system, a PAL digital video signal to be recorded is recorded with the same address assigned to each field signal, and the reproduced PAL digital video signal is stored in a field memory of a reproduction circuit system. In a signal processing method for a digital VTR that writes a digital video signal according to an address and reads a PAL video signal from a field memory, an address is assigned to each field signal of a PAL digital video signal to be recorded. By setting the start address and start sample for the line signal so that the phase of the color subcarrier for each field is the same, the image quality and color reproducibility of the forward screen are good during variable speed playback such as high-speed playback. The system has good responsiveness to moving images and the like, and requires only a small memory capacity during playback.

[Conventional technology]

In conventional digital VTRs, ff1 is used in the recording circuit thread.
to the digital composite color video signal to be
Each field signal is assigned the same address and recorded, and on the other hand, a memory is provided in the reproduction circuit system, and the reproduced digital composite color video signal is stored in this memory based on the address. When a digital composite color video signal has accumulated for a predetermined length, it is read out, making it possible to reproduce a composite color video signal that can constitute an almost complete playback screen even during variable speed playback. I was trying to do that.

[Problem that the invention seeks to solve]

Incidentally, in a PAL color video signal, the color subcarrier has an 8-field sequence, so when considering the color reproducibility of the reproduced signal, it is necessary to maintain the 8-field sequence of the subcarrier. Therefore, P.A.
In the digital TR for the L system, the memory of the reproduction circuit system is provided with a capacity for 8 fields in order to store the digital composite color video signal for each of the first to eighth field signals. Once eight fields of digital composite color video signals were stored in this memory, they were read out. However, when such a memory having a capacity of eight fields is used, there are disadvantages in that the memory is not only expensive but also has a low response speed.

Therefore, if a memory with a capacity for one field is used, this drawback can be avoided. However, in this case, even if the signal has the same address in the digital composite color video signal, the phase of the color subcarrier will differ depending on which of the first to eighth field signals it belongs to. It is hardly possible to store field signals in which the phase of the color subcarrier changes according to a sequence of eight fields, and therefore the color reproducibility of the reproduced digital composite color video signal deteriorates.

In view of the above, the present invention is such that, in the recording circuit system, the PAL digital video signal to be recorded is recorded with the same address assigned to each field signal, and the same address is assigned to the field memory of the reproduction circuit string. Regenerated PA
In a digital VTR signal processing system that writes L format digital video signals according to addresses and reads PAL format video signals from field memory, image quality and color reproduction on both sides of the playback are improved during variable speed playback such as high-speed playback. Good performance and responsiveness to videos etc.
Moreover, it is an attempt to propose a method that requires less memory capacity during playback.

[Means for solving problems]

According to the present invention, in a recording circuit system, a PAL digital video signal to be recorded is recorded with the same address assigned to each field signal, and the reproduced PAL digital video signal is stored in a field memory of a reproduction circuit system. In a signal processing method for a digital VTR that writes a digital video signal according to an address and reads a PAL video signal from a field memory, an address is assigned to each field signal of a PAL digital video signal to be recorded. The start address and start sample for the line signal are set so that the phase of the color subcarrier for each field is the same.

[Effect]

According to the present invention, the start address of the address assigned to each field signal of the PAL digital video signal to be recorded and the start sample for the line signal are set so that the phase of the color subcarrier for each field is the same. do.

(Embodiment) Referring to FIGS. 5 and 6, a recording circuit system and a reproducing circuit system of an example of a digital VTR to which the present invention can be applied will be described below. First, prior to explaining the recording circuit and reproducing circuit shown in FIGS. 5 and 6, the configuration of the rotating magnetic head device will be explained. A recording rotary magnetic head and a reproducing rotary magnetic head are attached to the rotating upper drum of a tape guide drum consisting of a fixed lower drum and a rotating upper tram at an angular interval of, for example, 120°. The recording rotary magnetic head and the reproducing rotary magnetic head each include a pair of closely spaced rotary magnetic heads (head chips) having different gap azimuths. Then, a magnetic tape of, for example, 330 mm is placed on this tape guide drum.
The winding angle is such that the winding is guided diagonally around the corner.

Further, the digital video signal is transferred to the magnetic tape by a pair of rotating recording magnetic heads so as to form a pair of adjacent inclined recording tracks per 1/2 field, thus forming two pairs of inclined recording tracks per field. Record. The digital video signals of each pair of inclined recording tracks recorded in this manner can be respectively reproduced by the above-mentioned pair of rotary magnetic heads for reproduction.

First, the recording circuit system of this digital VTR will be explained with reference to FIG. 11) is an input terminal for a PAL analog composite color video signal (one frame has 625 lines). An analog composite color video signal from an input terminal (1) is supplied to a clamp circuit (3) and a sync separation circuit (4) via a low-pass filter (2). A bedscale clamp level detection signal from the sync separation circuit (4) is supplied to the clamp circuit (3). Horizontal and vertical synchronization signals from the synchronization separation circuit (4) are supplied to a timing signal generation circuit (5). Furthermore, the composite color video signal from the clamp circuit (3) is
/D converter (6), where it is converted into a parallel 8-bit digital composite color video signal (the portion of one line excluding the vertical blanking section consists of 948 samples of data), and is also channel coded. The data is separated into two channels consisting of 474 samples and is supplied to the Sharaf ring circuits (7a) and (7b) of each channel. Note that the sampling frequency is four times the color subcarrier frequency.

The Sharaf ring circuits (7a) and (7b) each have a memory for, for example, 20 to 30 lines, and the timing of writing signals to the memory is determined by the timing signal from the timing signal generation circuit (5). controlled. In addition, these Sharafling circuits (7a)
, (7b) will be detailed later.

Outputs from the Sharafling circuits (7a) and (7b) are supplied to time axis compression circuits (8a) and (8b), respectively. These time axis compression circuits (8a), (8
b) each has a memory with a capacity of, for example, 1/6 field, and the digital video signals from the Sharaf ring circuits (7a) and (7b) are written into the memory with a clock signal of, for example, 7Mh, and the digital video signals from the Sharaf ring circuits (7a) and (7b) are written in the memory with a clock signal of, for example, 7Mh, and Time axis compression is performed by reading out signals.

The outputs of the time axis compression circuits (8a) and (8b) are sent to the CRC code signal addition circuits (9a> and (9b), respectively).
- Vertical parity check code signal addition circuit (10a)
.

(10b) - Block address adding circuit (adds a block address every 1/6 lines) (lla).

(llb) - an 8-8 conversion circuit (13a) for reducing the error appearance when a bit error exists in the MSH through the horizontal parity check code signal addition circuits (12a) and (12b) in sequence; (13
b) respectively. 8-8 conversion circuit (13a).

The output of (13b) is the block synchronization signal addition circuit (
14a), (14b) - Preamble and postamble addition circuit (15a), (15b
)-delay compensation circuit (16a), (16b) in sequence, and then the parallel-to-serial conversion circuit (17a),
(17b) respectively.

Then, the parallel-serial conversion circuit (17a), (1
The output of 7b) is sent to a scrambling circuit (18a) for averaging the number of 1's and 0's of each bit, respectively.
(18b). Scramble circuit (18a
), (18b) are output from the delay compensation circuits (the above-mentioned delay compensation circuits (16a), (16b), respectively).
) (19a)
, (19b) to the TTL and ECL circuits, and their outputs are supplied to the reproducing rotary magnetic healds Ha and H, respectively.
b, and is recorded on the magnetic tape TP.

Next, referring to FIG. 6, the reproducing circuit thread of this digital VTR will be explained. The digital video signal recorded on the magnetic tape TP is transmitted to the rotating magnetic heads H'a, H' for reproduction.
After being regenerated by b, the amplifier (22a),
PLL for clock signal detection via (22b)
(phase locked loop) and block synchronization signal detection circuits (23a) and (23b), respectively. The outputs of the circuits (23a) and (23b) are serial-parallel conversion circuits (24a) and (24b).
After being converted into an 18-bit parallel digital signal, the signals are supplied to block synchronization signal and block address signal reproducing circuits (25a) and (25b), respectively.

It should be noted that if the block address is reproduced, the address of each sample data will also be known based on it.

The output of the reproduction circuits (25a) and (25b) is 8
-8 horizontal error correction circuits (27a), (27b) through inverse conversion circuits (26a), (26b)
are supplied respectively. Horizontal error correction circuit (27a),
(27b) output from the vertical error correction circuit (28a
), (28b) are respectively supplied to 1.

The outputs of the vertical error correction circuits (28a), (28b) are sent to the error detection circuits (30a), (30b) via switching means (29a), (29b).
are supplied respectively. And shuttle playback (variable speed playback)
Sometimes a horizontal error correction circuit (27a),
(27b) direct switching means (29a),
(29b) through the error detection circuit (30a)
, (30b).

And error detection circuits (30a), (30b
) output is on the time axis l! 4 difference correction circuit, time axis extension circuit, lid deshuffling circuit (31a), (31b
), and their outputs are supplied to the deshuffling circuit (
32a).

(32b) respectively.

The circuits (31a) and (31b) each have a memory with a capacity for, for example, one field, and store sample data for one field based on the block address during variable speed playback. Once the sample data is collected, it is read out and sent to the deshuffling circuit (32
a) and (32b). Actually, the same holds true during constant speed playback. Also, the circuit (
The outputs of 30a) and (30b) are written to that memory with a clock signal of approximately 8Mk, and a fixed 7MHz
By reading with the clock signal of 1, the time axis is expanded, and by frequency modulating the write clock (1) according to the time axis fluctuation, the time axis error is corrected.Deshuffling circuit (32a), (3
2b) each have a memory capacity for 1/6 line.

Deshuffling circuit (32a), (32b
) is supplied to a mixing circuit (33), channel decoded, and then supplied to an error correction circuit (34). The output of the error correction circuit (34) is supplied to a luminance/chromaticity separation circuit and a chromaticity phase control circuit (35).

The output of this circuit (35) is supplied to the horizontal, vertical and burst signal addition circuit (37) through the dark clip circuit and limiter circuit (36).
) horizontal and vertical synchronization signals and a burst signal from a synchronization signal source (38) are added to the digital color video signal. The output of the synchronization signal addition circuit II (37) is D/
The PAL obtained from the A converter (39) is supplied to
The analog composite color video signal of the system is outputted to an output terminal (41) via a low-pass filter and buffer circuit (40).

Next, referring to FIG. 4, the specific structure of the Sharaf ring circuits (7a) and (7b) in the recording circuit system of FIG. 5 mentioned above will be explained. The channel coded 8-bit digital composite color video signal from the input terminal (42) is supplied to the memories (44) and (45) and is written alternately to the memories (45), (44).
) are outputted to an output terminal (43). (46) is an address counter that counts the clock signal from the input terminal (46a) and generates an address signal, and the parallel 13-bit address signal from this counter is sent to the address selection circuits (48), (49) and the address counter. It is commonly supplied to encoders (50) and (51).

Now, the frequency Fsc of the color subcarrier in the PAL system is expressed as follows.

Fsc= (1135/4) ・Fh+Fv/2
-(11 However, Fh is the horizontal frequency and Fv is the vertical frequency.

1v/2 in equation (1) is called offcent, which is a much smaller value than the first term and can be ignored between several consecutive lines. It will be done.

Psc# (1135/4) ・Fh
= = = (21) From equation (2), it can be seen that the color subcarrier and the horizontal synchronization signal are synchronized with approximately 4 line periods.

Now, No. 111A-H is a composite synchronization signal 5 of field signals F1 to F8 of 8 fields of a PAL color video signal.
The phase S of the burst signal of YNC and each line thereof is shown. Then, in the phase S part of this burst signal,
Considering the phase of the color subcarrier, each line signal is assigned a code Ll~
Attach L4. 2A to 2D show the phases of the burst signals of the line signals L1 to L4, and the phases of the burst signals of the line signals L1 to L4 are shown. When the burst signal of L2 is in positive phase, the burst signal of line signals L31L4 is in reverse phase. Also, line signal L is shown in FIG. 2 E-H.
The phases of the color subcarriers 1 to L4 are sequentially shifted by 90 degrees, and the color subcarriers of line signals L1 and L3 are in opposite phases to each other, and the color subcarriers of line signals L2 and L4 are opposite to each other. It is phase.

Thus, the address counter (46) has the timing signal from the timing signal generator (5) to control the start timing of counting for each field.
As shown in D, field signals F1 to F4 of the first to fourth fields are all line signals LX (generally L n
(n-1~4)) to memory (44),
(45), field signals F5 to F8 of the fifth to eighth fields are both line signal L3 (general Specifically, L<nφ2>
) +However, L5 = Lt.

Le”L2) to memory (44), (45
) is started. in this case,
Since the color subcarrier of the line signal L3 has an inverted phase with respect to the line signal L1, the field signals F5 to F8 of the fifth to eighth fields are the field signals F! of the first to fourth fields. ~For F4, memory (44),
The start of writing to (45) is shifted by 1/2 of the period Tsc of the color subcarrier (2 samples when the sample frequency is four times the color subcarrier frequency) as shown in FIG. The field signals F of the first to eighth fields are
1 to Fe are written into the memories (44) and (45) so that the phases of the color subcarriers at the writing start part are the same. Considering this and the offset Pv/2 in equation (1) above, the sample data of the part surrounded by the solid line parallelogram of the field signals of the 1st to 8th fields in FIG. , will be written in (45).

Parallel 13-bit address signals from circuits (4B) and (49) are supplied to memories (44) and (45), respectively. Address selection circuit (4B), (49)
, the address signals encoded by the address encoders (50) and (51) directly from the address counter (46) and the address signals encoded by the address encoders (50) and (51) are respectively stored in the memory ( 44) and (45).

(47) is a selection control circuit, which is an address counter (
46), and the obtained selection control signal is controlled by the address selection circuit (4B), (49) and the memory (
44) and (45). And memory (4
When the memory (4) is in the process of writing, the memory (45) is in the read state, and when the memory (45) is in the process of being written, the memory (44) is in the read state. However, memory
A parallel 8-bit digital composite color video signal is written into (44) and (45) by the address signal from the address counter, and this is read out by the address signal encoded by the address encoders (48) and (49). Sharafing of the digital composite color video signal is performed by this method. In this case, the first sample data in which the phases of the color subcarriers of the field signals F1 to pg of the first to eighth fields of color framing are equal are stored in the memory (4).
4).

(45) is written as sample data at address 0 (start address).

On the other hand, the digital composite color video signal is encoded by the address encoders (50) and (51), and the memory (
44) and (45) and read out by the address signal from the address counter (46), the digital composite color video signal may be shuffled.

According to this embodiment, in the recording circuit system, the PAL digital composite color video signal to be recorded is recorded with an interval address attached to each field signal, and the field memory of the reproduction circuit system is recorded. , in a digital VTR signal processing method that writes the reproduced PAL digital composite color video signal according to the address and reads the PAL composite color video signal from the field memory, during variable speed playback such as high-speed playback. Therefore, it is possible to obtain a method that has good image quality and color reproducibility on the playback screen, good responsiveness to moving images, etc., and can use a small memory capacity during playback.

〔Effect of the invention〕

According to the present invention described above, in the recording circuit system, the PAL digital video signal to be recorded is recorded with the same address assigned to each field signal,
In a digital VTR signal processing system that writes the reproduced PAL digital video signal to the field memory of the reproduction circuit string according to the address and reads the PAL video signal from the field memory, the PAL to be recorded is The start address of the address attached to each field signal of the digital video signal of the system and the start sample for the line signal are set so that the phase of the color subcarrier for each field is the same, so during variable speed playback such as high-speed playback, A method that provides good image quality and color reproducibility on the playback screen, good responsiveness to videos, etc., and requires less memory capacity during playback.

[Brief explanation of the drawing]

1, 2, and 3 are diagrams for explaining an embodiment of the present invention, FIG. 4 is a block diagram showing an example of a Sharaf ring circuit according to an embodiment of the present invention, and FIG. FIG. 6 is a block diagram showing a recording circuit system and a reproducing circuit system, respectively, of a PAL digital VTR to which the present invention is applied. (7a) and (7b) are Sharafling circuits, respectively.

Claims (1)

[Claims] In the recording circuit system, the PAL digital video signal to be recorded is recorded with the same address assigned to each field signal, and the field memory of the reproduction circuit system records the reproduced signal. In a signal processing method of a digital VTR, in which a PAL digital video signal is written in accordance with the address, and the PAL video signal is read from the field memory, a field of the PAL digital video signal to be recorded is provided. A signal processing method for a digital VTR, characterized in that a start address of an address given to each signal and a start sample for a line signal are set so that the phase of a color subcarrier for each field is the same.