JPS63193233A - Instrument control equipment - Google Patents

Abstract

PURPOSE:To process plural tasks in parallel and to easily control the respective tasks by providing a main control part with plural subordinate control parts. CONSTITUTION:A bus OBUS dedicated to the extension element of an I/O is connected directly to subordinate control parts COP0-COPn, which operate I/O elements independently according to the composition of tasks and also control the timing of a sequence and eternal devices by counting a clock PCLKn. A u-LAN determines constant protocol by a system and assigns it to some COP. A CPU is interrupted from an internal data RAM assigned on a DPRAM and COPs. The COP finds the interruption to the CPU according to the program and report state changers to the CPU. The CPU and COPs operate asynchronously to access the same memory.

Description

[Detailed description of the invention] 〔Technical field) The present invention applies to copiers, facsimiles, and warps.

Articles regarding equipment control devices that control mechatronics equipment, including OA equipment such as personal computers.

(Background of the Invention) Nowadays, the application of microcomputers to equipment has become commonplace, and the performance of equipment has improved significantly.

This trend is expected to increase further.

This is due to semiconductor technology and the lower cost of these chips. As the functionality of products improves, the number of microcomputers in use increases, and the program capacity of their software increases dramatically year by year. Software now accounts for the majority of product development man-hours. The current situation is that product development periods are being squeezed by software. This is exactly why it is called a software crisis. Since the price of the chips themselves is extremely low, there is a tendency to increase the number of chips used in order to increase the added value. Hardware has become extremely simple and its functionality has continued to improve, but software has not been able to keep up with hardware. Furthermore, if you want to change the design, you will have to change the entire program from its roots17. From the outside, the computer sequence provides the user with an extremely flexible device, but it is difficult to set up. Therefore, real-time O5 is commercially available, and the number of systems using it is increasing. However, apart from large-scale devices, stand-alone OAi devices and plugging devices that use commercially available real-time O5 are too difficult to use, and these devices are impossible to program. Therefore, we fundamentally reviewed the conventional microcomputer architecture and proposed an architecture that can perform parallel processing of tasks and real-time processing. composition,
Changes can be made easily, programs that have been created once can be reused, and software resources can be recycled. The lifespan of products is getting shorter every year, and there is not enough time for development.

In the past, the software that was created once (application cage program) was not used at all in the next development 1fffi. This is because the architecture of conventional microcomputers had such a structure. Regarding the reuse of software, we proposed Silicon O5 and applied it as a means of managing various tasks.
No. 8 "Image forming device", also published in JP-A-59-221749
No. ``Image Forming Apparatus''.

FIG. 8 shows the heart configuration of a conventional control system for a control device mainly based on mechatronics such as a copying machine.

In the figure, the configuration consists of four one-chip microcontrollers MC, ~MC4, and the microphone is an 8-bit NEC μm microcomputer.
C0M87AD is often used. In addition to various types of Ilo, 4 bytes of ROM and 128 bytes of RAM are on-chip. Because it has good cost performance,
There is a strong tendency to use this chip.

MCI to MC4 control the inside of the device, and serial 110 (SIlo) is extended to the outside.
When adding external equipment, it is possible to communicate with the equipment via this path line.

If we were to compare it to a copying machine, there would be a sorter, colleter, and ADF (automatic document feeder) that are optional accessories in addition to the main unit.
, fare counters, etc.

In the configuration shown in the figure, MCI is a host processor,
Mainly performs sequence control of equipment. This inputs timing pulses to the MC's counter, reads them sequentially, and compares them with the values written in the ROM to advance the sequence.It controls the actuators such as solenoids, clutches, and motors required to control the sequence. Set, ricket and go. Also, signals from sensor detection switches, etc. are manually input to perform sequential operations.

MC2 is mainly a pulse motor, in the case of a copying machine that controls a servo motor, two to three pulse motors may be used, but it is commonly used for lens movement, feeding one sheet of paper, moving the document platen, etc. Servo motors are used in photoreceptor drums and optical scanners.

MCs is a processor that controls analog input/output, including temperature, light intensity, humidity, and surface potential. It also performs a rough diagnosis of the entire device. Since these signal inputs are input in analog form, they are input digitally by an A/D converter on the chip.

MC4 mainly controls the operation display section, including display element control, CED, and LCD.

Controls the lighting of the fluorescent display tube. Furthermore, it controls the input from the key switch.

Such a multiprocessor system is characterized by high cost performance when using a one-chip microcomputer, but the drawback is that the protocols and communication software between chips become complex. Therefore, since the speed of these on-chip serial I10s is not necessarily high, there is a lot of idling time, and communication between the microcomputers may not work properly. This is because when the serial I10 of each chip tries to send data from the host microcontroller to the specified slave microcontroller, all the slave microcontrollers stop working when the slave microcontroller receives data from the host microcontroller. Interrupt and start decoding the address. Therefore, in the control system shown in Fig. 8, for example, when the MC is performing fine control of the servo, it is the same as if an interrupt occurs and the state is interrupted, so the control during that time is interrupted and the accurate result is not accurate. I can't get it. In the case of a digital copying machine scanner that performs precise positioning, even an error of several tens of microns causes image blur, making it impossible to obtain a good image. Such a multi-CPU u is highly cost effective, but problems arise when performing such communication because synchronization must be achieved. Therefore, commercially available software real-time operating systems for real-time processing, such as those found in CPs of 16 bits or more, are often used. Real-time processing refers to a function that selects and executes the optimal program to respond to various changes in the external or internal state of the system within the required time. That is, real-time processing is characterized by performing immediate processing in response to a processing request, rather than performing corresponding processing at predetermined fixed time intervals, regardless of the processing request, as in time-sharing processing (TSS). Conventionally, the processing function was low and the number of tasks was naturally small, so it was possible to deal with it with a simple interrupt processing program for the CPU. However, the system functions of current OA equipment have improved, and the number of processing tasks has become larger and more complex. Therefore the processing program,
In other words, it becomes difficult to judge in what order tasks should be given priority and executed, and the basic software that effectively makes this judgment is a real-time operating system. The main job of a real-time operating system is to respond to changes in the system by quickly selecting and executing the optimal program from among the processing units, that is, tasks. Generally, in such application systems, the execution conditions of each task are mutually limited until the processing differs depending on the processing results of other tasks.

Therefore, the real-time operating system that controls these functions has a synchronization function that waits for execution between tasks, a communication function that supports the exchange of data and messages between tasks, and a function that selects the highest priority task from among executable tasks. , it is required to have abundant functions for ordering.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to provide an equipment control device that processes a plurality of tasks in parallel and can easily manage each task.

(Example) FIG. 1 shows a conceptual diagram of a control device (hereinafter referred to as controller) of this example.

There is an apex CPU (main control unit), which is a CPU for management that oversees the entire system, and does not normally execute tasks as applications.

Its main work is to manage the co-processor (sub-control unit hereinafter referred to as COP) and to manage the execution of O5 (monitor). In addition, when the COP is busy with processing, it will assist in executing high-speed calculations that cannot be performed by the CoP, depending on the request. The second layer is the 002 group. This is a COP multi-channel layer, and in the example of a copying machine, 10 channels are prepared. This 0
The 01 group executes predetermined tasks under the control of the CPU. CoPm may be fixed and correspond to tasks, but it may also be made to flexibly correspond to tasks that occur one after another under the control of the CPU. Layer 3 is CPU.

1'tAM and bus for communication with COP and external I10 memory. The S-bus is the normal system bus for memory, as in a normal microprocessor.

This is the address and data path line for I10.

■The bus is directly connected to the CPU and runs as an ICE (emulator)
This is a special bus for As will be described later, the 0 bus of the I10 bus is a dedicated bus for expanding the I10 port, and this bus allows the COP managed by the CPU to exclusively interface with a specific register. μ-LAN is a serial communication line that exchanges data using a certain protocol. DPRAM (dual port RAM) is mainly used for CPU
It is used for exchanging data between and COP. In an emergency, the COP may interrupt the CPU and call it to fetch the data, but the program (OS) may also periodically search the RAM area and check the data. The RAM is a normal scratchpad memory and can be accessed by both the COP and CPU. Layer 4 is peripheral I10 equipment necessary for mechatronics control.
PWM (Pulse Width Modulation), ADDC Motor PC is a phase comparator for servo motors and can support PLL of programmable frequency, and can be used for variable speed PLL controlled DC motors.

The reference signal for this phase comparator is supplied from an internal 16-bit timer/counter.

Additionally, there is a 16-bit timer/counter PC-1 which generates the aforementioned PLL reference signal, generates a square wave, generates a one-shot pulse, and has a counter for external pulse input.

External triggers include a zero-cross pulse detector, a counter start by external pulse input, and an A/D converter start. This layer 4 peripheral I10 device can be combined with the COP to control mechatronics during organic operation. FIG. 2 is a diagram showing the relationship between COP and tasks, and shows that tasks 1 to nm are controlled by the 002 group based on silicon O3. As shown in FIG. 2, there is no correspondence between tasks and specific COPs, and the COPs correspond flexibly based on the configuration of the CPU.

FIG. 3 shows a block diagram of the controller and shows its relationship with the outside. In the figure, IBUS is a dedicated bus for an ICE (in-circuit emulator) that is directly connected to the CPU and is used when depacking the system. C
Since the PU mainly performs a job specific to O5 as a silicon monitor, it is possible to output the contents of the ACC (accumulator) and each register to the outside through the I BUS in real time. In this system, the actual tasks are performed by the COP, and the CPU has sufficient margin for the work of O3, so unlike conventional ICE, real-time emulation is possible.

The S bus is no different from the conventional system bus, but the C bus
The feature of COP is that it can be accessed in addition to PU.
Although the PU and CoP are apparently separate CPUs that operate completely independently, they actually use a bus by time sharing. The relationship is shown in FIG. Bus to CPI
This is a schematic diagram of a time chart used alternately by J and COP. In reality, the COP cycle is inserted into an empty cycle of the CPU, so the COP instruction is
Compared to Pu, it has a relatively simple set of instructions. As mentioned above, this is the reason why instructions that perform complex operations (multiplication and division) are executed by the CPU. Figure 5 shows CO
This figure shows the execution order of the H.210 channel, and shows how the buses are used in order. Compared to CPtJ, COPs alternately share the bus in this way, so as the number of COPs increases, the execution speed becomes slower. Therefore, when a high execution speed is required, it is sufficient to use only two channels, for example, copo and 1, only when processing that task, and then suspend the remaining COP for an unavoidable amount of time.

The CPU should manage whether or not to operate the COP, and activate it depending on the processing status of the external load.

The explanation will be returned to the block diagram of FIG. 3.

0BUS is a bus dedicated to Ilo expansion elements and is directly connected to COP. Therefore, depending on the organization of tasks, COP
can independently operate the I10 element. For example, the PCLKn input to the CoP is manually inputted as a 4-channel clock, and this is input to a counter attached to each CoP. These pulses are counted and used for sequence timing and control of external devices. μ-CAN is a serial line, and this can be managed by determining a certain protocol in the system, allocating one of the CoPs, for example. The baud rate generator has a 16-bit timer, and various baud rates can be generated by setting the value of this timer register. A specific cop may manage these baud and rate generation.

INO~2 are connected to 3 channels of external interrupts or the CPU. These have priority and increase from 0 to 2.

The MCUO connected to μ-CAH is synchronized with another microcontroller using serial I10.

FIG. 6 is a memory map inside the controller and shows the address relationship between the CP and the word processor copo~n channels. This relationship will be explained.

Each COP is a group of independent processors similar to a CPU.
Each channel has a "local space" and a common "global space". Global space refers to all address spaces that cop can access, including local space, external I1
0 is also included. A program counter for each COP, various flags, a 16-bit counter, etc. are allocated to the local space. FIG. 6 shows the relationship. The local space is allocated to internal RAM, and the global space other than the local space is allocated to on-chip peripheral registers, RAM, and external I10 space. External I10
The space is physically connected to the external expansion boat bus, and accessing this space allows data access to Ilo connected to the external I10 port.

The CPU can also access this area through the "window" (see Figure 7).

The accessible range is that a COP can access its own local base and global space, and a COP can access its own local base and global space.
U is local space and global space of all channels.
I can access the space.

The C0P(7) memory space and address as seen from the CPU/COP is shown in FIG.

The feature is that both the CPU and COP can access the space, and the local space is a space exclusive to each COP. I10 expander space is CP
U is accessed through a register called window,
CoP can access this directly, and input/output to Ilo can be done with read and write commands here.

FIG. 7 is a diagram showing the communication relationship between the CPU and COP. Internal data RAM allocated on DPRAM (dual port RAM) and CPU from CoP
In addition, it can be done by interrupt. I10
Regarding the expander, as mentioned earlier, the CP can be accessed via a register called a window, and the COP can be accessed directly.

In addition, the movement of the CoP can be known by monitoring the registers in the global space in the memory map shown in FIG. In addition, CoP requests an interrupt from the CPU according to the COP program, and reports state changes to the CPU.
Inform PU. The feature here is that both the CPU and the coP are independent and separate processors, operate asynchronously with each other, and can access the same memory.

This shows that there is a possibility that both processors write data to the same location at the same time, which is a problem in a shared memory multiprocessor system, but as explained in Figures 4 and 6, this problem occurs in hardware. Collisions are avoided.

A device control method using the newly proposed real-time multitasking processor as described above will be described below.

FIG. 9 shows a control example.

In the following, task management, such as task priority and scheduling, will be explained in detail. Normally, as shown in FIG. 10, the priority range of tasks under control is determined. If the number of tasks is 256, their priorities can be determined from 0 to 255. The scheduler executes READ when an event occurs as shown in Figure 10.
The CPU execution right is assigned to the task with the highest priority among the Y tasks. As for the priority, 0 is the highest and 255 is the lowest. If there are multiple tasks with the highest priority, CPU execution rights are assigned to them in the order in which they appear in the queue, that is, in FIFO order.

Usually commercially available O3 is O3゜TSS for batch processing.
O3 for (time sharing), real-time O8 (are given to three). Batch processing OS executes one job sequentially, and O3 for TSS
It is also called a land solven, which is time-divided and processes are carried out at regular intervals. The real-time O3 performs processing immediately when a data processing request occurs, and is also called event-driven. O of this proposal
5 is composed of a CPU and a group of COPs (coprocessors) that actually control tasks, as described above, and apparently multiple COPs execute under the control of the CPU.

Therefore, the feature is that real-time multitasking control is possible in a simpler form than the conventional O3 structure. FIG. 11 shows task scheduling according to this proposal, where the current task is O~255. That is, a model is shown in which there are 256 tasks and they are processed in parallel by 10 processors of coprocessor C0PONCOP9. 10 tasks are processed in parallel, and tasks are switched by CPU (0, S
control). The organization and scheduling of tasks is done by the CPU. Suppose that the CPU executes tasks in a fixed order, but due to the occurrence of some event, it becomes necessary to urgently execute a specific task. If the occurrence is notified to the CP by an interrupt from the coprocessor to the CPU or by an interrupt from outside the controller, it can be detected by executing a predetermined task.
A message requesting the CPU to switch tasks or execute a specific task may be placed in a mailbox in the PRAM (dual port RAM). FIG. 12 shows a model in which messages are sent from the co-processor COP to the CPU. This is done via f) PRAM (Dual Port RAM) in the controller. In this way, there are cases where execution of a specific task is requested urgently, and cases where the CPU is notified via the mailbox.

For example, taking a copying machine as an OA device as an example, a case will be described in which drum clock pulses are counted and predetermined tasks are sequentially executed.

Within its task, the COP that controls the fuser heater
Temperature control becomes impossible, and the temperature continues to rise. Since this is urgent, it is necessary to interrupt the CPU to execute the waiting diagnostic task. The CPU that receives the interrupt stops all currently executing COPs and assigns the diagnostic task to a specific COP for execution.

If a temperature sensing element such as a thermistor is malfunctioning,
Immediately shut off power to the machine and issue a display warning of abnormal mode. In addition, such an abnormality can be caused by a temperature detection element outside the controller (which turns ON or OFF when the temperature exceeds a predetermined temperature or below a predetermined temperature) directly interrupting the CPU and requesting a task switch. Also good. FIG. 13 shows a diagram in which tasks are switched by interrupts. In this example, there is a heater temperature switch and an external switch. This external switch is used when the operator wants the machine to do a different job, for example, in the case of a copying machine.For example, in a multicolor copying machine, it changes from the black mode to the red mode. It is convenient to use when you want to. You can quickly switch between tasks. FIG. 14 shows a model for changing the priority order of COPs by switching tasks. FIG. 14 is a diagram in which C0PIO channels are executed sequentially under the control of the CPU. As mentioned earlier, since the path line between CP IJ and COP is shared, CoP appears to have multiple channels running at the same time, or the apparent execution of parallel processing because they share the bus. becomes late. 1 COP
If it takes 8μsec execution time, then C0POC
It takes 80μSeC to execute all the steps up to 0P9. That is, C
The apparent execution of oP is 80 μsec. When fast processing is required due to the occurrence of some event, for example, C
If priority is given to 0PO, C0P2, C0P4, and C0Pa, the four coprocessors will be executed in 24 μsec.

FIG. 14(b) is a diagram showing this.

(c) 0) Yoni COP If O and cop6°C are given priority, only two COPs will be executed in 16 μsec. By switching between (a)=(b) and (a)-(C), it is possible to give priority to the execution of faster tasks. As mentioned above, this embodiment uses C
Using a controller in which the PU and two-processor 002 group integrate multiple channels, task organization and scheduling are performed via internal and external interrupts, and the mailbox provided in the DPRAM, and the priority order of the cops is changed and the tasks are quickly executed. It is possible to organize tasks in response to external changes.

〔effect〕

As described above, according to the present invention, simultaneous processing of a plurality of tasks and task switching can be quickly handled in accordance with various events.

In addition, the main control section can concentrate on managing tasks, and can also create a library of programs, allowing effective use of software. Furthermore, there are many benefits such as improved efficiency in task management for processes that require multiple simultaneous processes such as mechatronics.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the architecture of the controller of this embodiment, Figure 2 is a diagram showing the relationship between the co-processor and tasks, Figure 3 is a block diagram of the controller, and Figure 4 is the exclusive time of the bus for the CPU and COP. Figure 5 is a diagram showing the execution order of COP, Figure 6 is a diagram showing the exclusive memory map of COP, Figure 7 is a diagram showing the interface between CoP and CPU, and Figure 8 is a block diagram of a conventional control system. Figure 9 is a diagram showing a control example of this embodiment, Figure 10 is a diagram showing task priorities, Figure 11 is a diagram showing task schedule (organization), and Figure 12 is a message between cop and CPU. FIG. 13 is a diagram showing task switching due to an interrupt, and FIG. 14 is a diagram showing changing COP allocation. (O) Cb) (C> d) fjc

Claims (5)

[Claims] (1) In an equipment control device that integrates a main control unit and a plurality of sub-control units that execute parallel processing under the control of the main control unit, the main control unit controls a plurality of tasks executed by the sub-control unit. An equipment control device characterized in that the main control unit organizes the tasks in the main control unit and assigns priorities to the plurality of tasks. (2) The device control device according to claim 1, characterized in that the task organization is switched in response to an external request. (3) The equipment control device according to claim 1, characterized in that the switching of task organization is performed in response to a request from a sub-control unit. (4) The equipment control device according to claim 1, wherein assignment of task priorities is executed in response to a request from the sub-control unit. (5) The device control device according to claim 1, characterized in that assignment of task priorities is executed in accordance with an external request.