JPS63191404A - Clock generator - Google Patents

Abstract

PURPOSE:To generate a high-frequency clock with simple constitution by providing a gate to the output of a crystal oscillator and also providing a DC bias voltage adjusting circuit which adjusts the threshold voltage of the gate. CONSTITUTION:A gate circuit 3 to which the DC bias voltage adjusting circuit 2 is added on its input side is connected to the output of the crystal oscillator 1 and the gate circuit 3 outputs a rectangular wave. Therefore, if there is deviation in duty ratio due to the distortion of the waveform of the crystal oscillator 1, variation in the threshold voltage of the gate circuit 3, etc., a bias voltage is adjusted by the DC bias voltage adjusting circuit 2 to easily obtain a rectangular wave of 50 % in duty ratio at the frequency of the crystal oscillator 1. Consequently, an inexpensive, high-frequency clock generator of high quality is obtained.

Description

[Detailed Description of the Invention] [Summary] In order to keep the duty ratio of the output waveform of a high-frequency crystal oscillator constant, a gate is provided at the output of the crystal oscillator, and a DC bias voltage is used to adjust the threshold voltage of the gate. By providing an adjustment circuit, it is possible to start a high frequency clock with a simple configuration.

[Industrial application field]

The present invention relates to improvements in high-speed, high-quality clock generators used in electronic communication equipment and the like.

In recent years, as electronic devices have become faster, the lock generators required for these devices are increasingly required to be faster and of higher quality.

Here, the quality of the clock signal is generally determined by the ratio TI/' of the clock cycle time T and the pulse width T1, as shown in FIG.
! It is evaluated that the duty ratio expressed by `` is as close as possible to 50% and the period (frequency) is stable.

Crystal oscillators are exclusively used as oscillators with stable frequencies, but even those using a Heas-grounded Colpitts circuit, which is suitable for high frequencies, have a maximum frequency of 200 M.
It is about Hz.

Therefore, there is currently a demand for an inexpensive lock generator that outputs a high quality square wave clock with a frequency of 200 MHz.

[Conventional technology]

A conventional example will be explained below using figures.

FIG. 5 is a block diagram of a conventional example.

A known method of obtaining a high-quality square wave clock with a duty ratio very close to 50% is to use a flip-flop at the output of an oscillator, but in this case, the output frequency is equal to or lower than the oscillation frequency. It becomes 1/2.

Conventionally, as shown in Fig. 5, the output of a 200MH2 crystal oscillator 1 using a Colpitts circuit with a common base is
The frequency is set to 400 MHz using a multiplier 4 which can obtain a frequency twice this 200 MHz and has less waveform distortion, and a flip-flop 5 is connected to its output to generate a square wave with a stable frequency and a duty ratio very close to 50%. I was getting the clock.

In the crystal oscillator 1 of the Colpitts circuit shown in FIG. 5, XL is a crystal resonator, and LL and R2 are inductances.

TR is a transistor, and C1 to C4 are capacitors.

R1 to R3 are resistors.

[Problems to be solved by the invention] However, in the conventional method, the duty ratio is reduced to 50%.
Since a flip-flop is used for this purpose, a multiplier 4 that doubles the frequency is required, which causes the problem that the circuit becomes expensive and complicated.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

A gate circuit 3 having a DC bias voltage adjustment circuit 2 added to the input side is connected to the output of the crystal oscillator 1, and a rectangular wave is output from the output of the gate circuit 3.

[Effect]

According to the present invention, a gate circuit 3 having a simple circuit configuration and an inexpensive DC bias voltage adjustment circuit 2 added to the input side is connected to the output of a crystal oscillator 1 having a stable frequency, and the waveform of the crystal oscillator 1 is adjusted. Even if the duty ratio varies due to distortion or variations in the threshold voltage of the gate circuit 3,
By adjusting the bias voltage with the DC bias voltage adjustment circuit 2, the duty ratio can be adjusted to 5 at the frequency of the crystal oscillator 1.
A 0% square wave is easily obtained.

Therefore, an inexpensive, high-frequency, high-quality clock generator can be obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a diagram showing the relationship between a threshold voltage and a duty ratio with respect to an input signal waveform.

In Figure 2, 20
The output of the 0MHz crystal oscillator 1 is input to the NAND circuit 3', which is a gate circuit, via a resistor R4 that reduces the effect of addition and a DC cant capacitor C5, and a rectangular wave is generated from the output of the NAND circuit 3'. I'm trying to get an a-trick.

At this time, a variable resistor RV for bias adjustment is used to adjust the threshold voltage of the NAND circuit 3'.

In FIG. 2, R5 is a resistor for supplying bias voltage, C6 is an AC bypass capacitor, D is a voltage protection diode, and the power supply voltage is normally -5.2V.

If you do as shown in Figure 2, the output waveform of crystal oscillator l will be
As shown in figure (A), in the normal case, if the threshold voltage of the NAND circuit 3° is set to -1.35V,
(B) (7) A square wave with a duty ratio of 50% as shown in V to is obtained, but if there is distortion in the output waveform or variations in the threshold voltage of the NAND circuit 3, the duty ratio will be 50%. At this time, the bias adjustment variable resistor RV is used to raise and lower the threshold voltage of the NAND circuit 3' to adjust the duty ratio to 50%.

In the case of FIG. 3, if the threshold voltage is set in one direction, the duty ratio decreases, and if it is set in one direction, the duty ratio increases, so the duty ratio can be easily adjusted to 50%.

In this case, NAND circuit 3'', bias adjustment variable resistor R■, resistors R4, R5, capacitor C6゜diode D
is inexpensive, so an inexpensive 200Mitz clock generator can be obtained.

Although the above description has been made using a NAND circuit as a gate circuit, the gate circuit is of course not limited to a NAND circuit.

〔Effect of the invention〕

As will be explained in detail below, the present invention has the effect of providing an inexpensive, high-speed, and high-quality clock generator.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a diagram showing the relationship between threshold voltage and duty ratio with respect to the input signal waveform, and Fig. 4 is a diagram showing the relationship between the threshold voltage and the duty ratio. -Explanatory diagram of Tey ratio. FIG. 5 is a block diagram of a conventional example. In the figure, 1 is a crystal oscillator, 2 is a DC bias voltage adjustment circuit, 3 is a gate circuit, 3 is a NAND circuit, 4 is a multiplier, 5 is a flip-flop, and RV is a variable resistor for bias adjustment.

Claims (1)

[Claims] A gate circuit (3) is connected to the output of the crystal oscillator (1), and a DC bias voltage adjustment circuit (2) is provided to adjust the threshold voltage of the gate circuit (3). A clock generator characterized in that the duty ratio of a wave is adjustable.