JPS63187701A - Microwave line converter - Google Patents

Abstract

PURPOSE:To match impedances between input and output microwave lines and to improve electric separation between input and output by cascading a first grounded-gate field effect transistor FET and a second grounded-drain FET. CONSTITUTION:The first grounded-gate FET 2 which has the source electrode connected to an input microwave line 1 and the second grounded-drain FET 4 which has the gate electrode connected to the drain electrode of the first FET and has the source electrode connected to an output microwave line 5 are provided. Thus, the first grounded gate FET and the second grounded-drain FET are cascaded, and various characteristic impedances between input and output microwave lines are matched by these two cascaded FET circuits, and in this state, different microwave lines are connected.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microwave line conversion device for connecting different microwave lines. Below, what is a microwave line?
In general, IGI- (a line for transmitting signals with a frequency of z or higher, and refers to a coplanar line such as a coplanar line or a slot line, a microstrip line, etc.).

[Prior art] FIG. 9 (Δ) shows a lot line 16 that takes a coplanar line 12.
FIG. 9B is a perspective view of a microwave line conversion circuit (hereinafter referred to as the first conventional example) that performs line conversion between It is a front view.

In Figures 9(A) and (B), conductor summers 3 to 15
() The coplanar line 12 formed is connected to the dielectric substrate 11.
On the other hand, a slot line 16 composed of conductors 13 and 14 is formed on the right side of the dielectric substrate 11 in the figure. Here, in the coplanar line 12, a conductor 15 having a width I21 is formed far apart from the conductors i3 and 14 at predetermined intervals, while the slot line! 6, the conductor 13 is spaced from the conductor 14 by a predetermined distance (1, li
Formed separately. Also, at the connection point between the Koblely line 12 and the output slot line 16, the outer conductor 1
3 and 14 are connected by a shorting wire 18. Further, a predetermined width and a length of 1.5 mm are provided from the connection point of the short circuit line 18 to the slot line 16 side.
A slot line 17 having a length of /4 wavelength is connected to the conductor 14 and! Formed by 5. Here, the slot line 17 is 1/
Since it is short-circuited with a length of four wavelengths, it is electrically released at the connection point of the short-circuit wire 18. By configuring as above, the coplanar line 12 and the slot line 1G
In this line conversion circuit,
The signal input to the coplanar line 12 is line-converted and output to the slot line i6, while the slot line 16
The signal input from the line is converted to the coplanar line 1.
2 is output. Therefore, the main line conversion circuit is a reciprocal circuit.

FIG. 1O is a perspective view of a microwave line conversion circuit (hereinafter referred to as a second conventional example) of a field effect transistor (hereinafter referred to as F'ET) proposed in Japanese Patent Application Laid-open No. 153602/1982. be. In Figure 1O, Figure 9 (
Components that are the same as A) and (113) are given the same reference numerals. This second conventional circuit differs from the first conventional circuit described above because, instead of the slot line 17 having a length of 1/4 wavelength, an FE'r 19 enclosed in a package is used as the input. The electrical board at the connection between the coplanar line 12 and the output slot line 1G! 1. Here, the gate terminal 24 of the FET 19 is connected to the center conductor 15 of the input coplanar line 12 and the bias supply terminal 26, and the source terminal 22 of the FET 19 is
and 23 is the outer ground conductor 13 of the input coplanar line 12
and 14. Further, the drain terminal of the FET 19 is connected to the conductor 21 and bias terminal 27 of the output slot line 16, and the output slot line 16 is constituted by the conductors 14 and 21.

With the above configuration, line conversion is performed between the input coplanar line 12 and the output slot line 16, and the signal input to the input coplanar line 12 is line converted and output to the output slot line 1G.

[Problems to be Solved by the Invention] However, the line conversion circuit of the first conventional example described above has the following problems:
Since it is necessary to use the 1/4 wavelength short-circuited slot line 17, it is impossible to configure the line conversion circuit to be shorter than about 1/4 wavelength, making it difficult to miniaturize the line conversion circuit. Furthermore, since this circuit is a reciprocal circuit as described above, it is not possible to electrically separate the input and output lines 12 and 16. For example, if there is reflection from the circuit connected to the output slot line 16, , the reflected waves appear as they are on the input coplanar line 12. In order to remove this reflected wave, there is also the problem that it is necessary to further provide an isolator.

Since the line conversion circuit of the second conventional example does not require a short-circuited line of 1/4 wavelength, it can be made smaller compared to the circuit of the first conventional example, and moreover, both Since the output lines 12 and 1f3 are connected, the signal input to the input coplanar line 12 as described above is output to the output slot line in one direction, and therefore the input/output lines 12.
16 can be electrically isolated. However, in this second conventional circuit, the input/output line 12
Since impedance matching between 16 and 16 is not achieved,
It is necessary to add a matching circuit to obtain good electrical characteristics. Therefore, there is a problem in that the entire line conversion circuit becomes large.

The purpose of the present invention is to solve the above-mentioned problems, and to provide a microwave line that is smaller than the conventional example, can electrically isolate input and output lines, and can achieve impedance matching between human output lines. The purpose of the present invention is to provide a conversion device.

[Means for Solving the Problems] The present invention provides a microwave line conversion device for connecting different microwave lines, which includes a first field effect transistor with a common gate whose source electrode is connected to an input microwave line; and a second field effect transistor whose gate electrode is connected to the drain electrode of the first field effect transistor and whose drain is grounded and whose source electrode is connected to the output microwave line.

[Operations] By configuring as above, the first field effect transistor with a common gate and the second field effect transistor with a common drain are cascade-connected, and this cascade-connected 2p field-effect transistor is connected in cascade.
By using the field effect transistor circuit I, different microwave lines can be connected with each characteristic impedance between the input microwave line and the output microwave line being matched.

[Embodiment] Basic Circuit FIG. 1 is a circuit diagram of a basic circuit of a microwave line conversion circuit using a field effect transistor (hereinafter referred to as FET), which is an embodiment of the present invention. In FIG. 1, the characteristic impedance, SZ. Input microwave line 1 with l
is a gate-grounded F with transconductance gra+
The drain of the FET 2 is connected to the ground via a gain adjustment resistor 3 having a resistance value R, and the drain is connected to the gate of the ET4 with a mutual conductance gm. Ru. moreover,
The source of the FE'r4 has a characteristic impedance Z. , is connected to the output microwave line 5 having the following.

Here, F E'! '2 and 4 are ideal F E '1'' that can be described only by mutual conductance, then the S parameter of the circuit in Figure 1 is S as shown in the following equation.
+t-0・・・・・・・・・・・・・・・・・・
・・・・・・・・・(2) Furthermore, gm+Zo+=gm
The gate is grounded so that tZot=I;' E
When T2 and each gate width of the FET 4 with a common drain are set, each of the above S parameters becomes as shown in the following equation.

5ll=Sl! =S, =0 ・・・・・・・・・・・・
・・・・・・・・・(5)521=□ ・・・・・・・
・・・・・・・・・・・・(6) 2(τ=7−− In this way, r'ET2 with a gate common and FET71 with a common drain set as gffi+Zo+=gmtZo*=1 are connected in cascade. This has the following effects.

(1) Input end reflection coefficient S II and output end reflection coefficient 82
2 becomes zero, impedance matching between the human output lines can be achieved.

(2) Since the reverse transfer coefficient S12 becomes zero, electrical equalization 61 between input and output lines can be performed.

(3) Since the positive direction transfer coefficient St+ can be expressed as in the above equation (6), the amplification gain can be adjusted by changing the resistance value R of the resistor 3. Note that the resistor 3 is provided for gain control and broadband expansion, and even if the resistance value R of this resistor 3 is set to infinity, that is, even if the resistor 3 is removed, this microwave line conversion circuit will still not perform as described in (1) above. and(
It has the effect of 2). Therefore, this microwave line conversion circuit can connect different input and output microwave lines in an impedance matching state and in an electrically isolated state between the input and output.

Furthermore, the distance between the input and output lines l and 2 does not require the length of I/4 wavelength as in the first conventional example, and the distance between F E 'r
By downsizing the circuit constituted by 2, 4 and the resistor 3, the microwave line conversion circuit can be downsized compared to the first conventional example.

First Embodiment FIG. 2 is a plan view of a hybrid integrated circuit for line conversion between an input coplanar line 12 and an output slot line 16, which is a first embodiment of the present invention. Items in Part B that are the same as those in the drawings are given the same reference numerals.

In FIG. 2, an input coplanar line 12 and an output slot line 16 are arranged on the upper surface of the dielectric substrate II.
．． 16 are formed at predetermined intervals in the longitudinal direction. Here, the input coplanar line 12 has a center conductor 1 with a width ff.
5 and an outer conductor 13.14, the outer conductor 13.
14 is formed in a spaced apart and coplanar relationship with the center conductor 15 by a predetermined distance Q, while the output slot line 16 is composed of conductors 14 and 21 separated by a predetermined distance Q3. In order to obtain good electrical isolation between input and output lines +2 and 10, the part of conductor 13 on the conductor 2I side and the part of conductor 21 on the conductor 13 side are cut so that conductors 13 and 21 are as far apart as possible. It is shaped like this. A substantially square conductor 9 is placed on the substrate 11 between the lines 12 and 16.
Conductors 9I and 92 are formed apart from each other by a predetermined interval, and conductors 9I and 92 are connected via a DC cutting chip capacitor 33. Substrate II between line 12 and conductor 91
A FET 31 enclosed in a package is placed on top,
Furthermore, a FET 32 sealed in a package is placed on the substrate II between the conductor 92 and the line 16.

Conductors 93 and 94 are formed on the substrate 1 at the bottom of the drawing of the conductors 91 and FET 32, respectively, and the ground conductor 14 having recesses 14a and 14b at the positions where the conductors 93 and 94 are formed is connected to the FETs 31 and 32 and The conductors 93 and 94 are formed on the substrate 11 on the lower side in the drawing. Further, drain bias supply terminals 38 and 39 are connected to the conductors 93 and 94, respectively.

The source terminal of FE'r31 is connected to the end of center conductor 15 of line I2, the drain terminal of FET31 is connected to conductor 91, and the two gate terminals of FET31 are connected to ground conductors 13 and 14, respectively. Ru. conductor 9
1 is connected to the conductor 93 via the chip resistor 3G, and the conductor 93 is connected to the ground conductor 14 via the high frequency bypass chip capacitor 34. Further, the conductor 91 is connected to the conductor 92 via the DC cut chip capacitor 33. Furthermore, the conductor 92 is connected to the protrusion +4c between the recesses 14a and 14b of the ground conductor 14 via the chip resistor 37, and the conductor 94 is connected to the chip capacitor 35 for high frequency bypass.
It is connected to the ground conductor 14 via.

A gate terminal of FET 32 is connected to conductor 92, and
The drain terminal of the r;'ET 32 is connected to the conductor 94, and the source terminal of the F'ET 32 is further connected to the end of the conductor 21 of the line 16.

With the above configuration, the drain terminal of the FET 31 is grounded at high frequency via the chip resistor 36 and the chip capacitor 34, and the drain terminal of the FET 32 is grounded at high frequency via the chip capacitor 35. The signal input to the input coplanar line 12 is FE
It is output to the output slot line 16 via T31, chip capacitor 33, and FET32. Here, the high frequency equivalent circuit of the hybrid integrated circuit of FIG. 2 becomes as shown in FIG. 1, and by setting the mutual conductance of FET31 and FET32 as glLZo+=gllltZo*=1, as described above, Input/output line 12
The different input/output lines 12 and 16 can be connected while impedance matching between the input and output lines 12 and 16 is achieved. In addition, between the input and output lines 12 and 16, there are two FETs that transmit signals in only one direction.
Since the circuit is inserted, a microwave line conversion circuit with good electrical separation between the human output lines 12 and 16 can be obtained.

Furthermore, since the interval between the human output lines 12, 16 in this circuit does not require a quarter wavelength length as in the first conventional example, FE'l'31, 32. Chip capacitor 3
By downsizing the circuit constituted by 3 and conductors 91 to 9a, the microwave line conversion circuit can be downsized compared to the first conventional example.

Note that in this embodiment, the FET 31 and the FET 32 are arranged close to each other and connected in a lumped constant manner, but the microphone C1
It is possible to connect via a wave line. This also applies to Example 6 below.

Second Embodiment FIG. 3A is a plan view of a monolithic integrated circuit for line conversion between an input coplanar line 12 and an output slot line 16 according to a second embodiment of the present invention. ) is a vertical cross-sectional view taken along the r3-[1' line in Figure 3 (Δ), Figure 3 (C
) is a vertical cross-sectional view taken along line cc' in FIG. 3(A). In FIGS. 3(A), (I3), and (C), the same reference numerals are given to the same parts as those in the above-mentioned drawings.

In FIGS. 3(Δ), (B), and (C), a metal-semiconductor field effect transistor (hereinafter referred to as
It is called MESFET. ) 41 is formed (1%2), impurity ions are implanted from the upper surface of the semiconductor substrate 40 to form an active layer 45.

The gate electrode 42 of the MESFET 41 is the active layer 45
The gate electrode 42 is formed integrally with the ground conductors 61a and 61b at approximately the center of the gate electrode 42, and the planar shape of the gate electrode 42 is a rectangle whose two sides are the longitudinal gate width W1 and the gate length g1. Furthermore, the source electrode 43 and the drain electrode 44 are
Input coplanar lines are placed on the active layer 45 at a predetermined distance from the gate electrode 42 with the gate electrode 42 in between! 2 conductor 15 and conductor 62
It is formed integrally with. Here, each of the source electrode 43 and the drain electrode 44 has a rectangular planar shape, and the sides in the longitudinal direction of the electrodes 43 and 44 are parallel to the side in the gate width direction of the bipedal gate 4tt pole 42. ing.

The MESFE'll' 41 is formed by the gate electrode 42, source electrode 43, and drain electrode 44 formed on the active layer 15 in the semiconductor substrate 40 by a known method as described above.
It consists of

Further, on the active layer 55 of the semiconductor substrate 40 at the lower right side of the figure of the MIDSFET 41, there is an M E S F E '1'.
41, an MES["ET51 is formed which includes a gate electrode 52, a source electrode 53, and a drain electrode 54.Here, the planar shape of the gate electrode 52 has two sides of the long gate width and the gate length g. It has a rectangular shape with
The source electrode 53 and the drain electrode 54 are respectively arranged on the conductor 71 and the conductor 6 of the output slot line 16 on the active layer 55.
It is formed integrally with G.

Hereinafter, the semiconductor substrate 40 on which the MESFE'r41 will be formed.
The left side in the figure is called the input side of the board 40, and the MESF
The right side in the figure of the semiconductor substrate 40 on which E'r 51 is formed is referred to as the output side of the substrate 40.

Conductor 15 of input coplanar line I2 is MESFE'r4
The conductor 15 is formed integrally with the source electrode 43 on the upper side of the source electrode 43 in the figure, and the planar shape of this conductor 15 is the same as the gate width w.
It has a rectangular shape with a width Ql in one direction and a long side. Here, one side of the width i21 of this conductor 15 or the source? ut&
It is connected to the central part of the side in the direction of gate radius W of 43.

The ground conductor 61a is located on the left side of the center conductor 15 in the figure, MESP
At the upper left side and bottom of the gate electrode 42 and drain electrode 44 of E'r41, and at the edge of the semiconductor substrate 40 below the drain electrode 54 of MESFET 51, integrally with the gate electrode 42 and the ground conductor 61b, It is formed coplanar with the center conductor 15 and the ground conductor 61b.

Further, a ground conductor 61b is formed on the semiconductor substrate 40 on the right side of the center conductor 15 in a coplanar relationship with the gate electrode 42 and the ground conductor Gla, and the planar shape of the ground conductor 61b is approximately rectangular. The ground conductor 61b is formed apart from the conductor 71 by a predetermined distance. Here, the ground conductor 61
a and 61. b is formed on the semiconductor substrate 40 at a predetermined distance Q from the center conductor 15 and in a coplanar relationship;
The ground conductors 61a, 61b and the center conductor 15 constitute an input coplanar line 12.

A conductor 62 is formed integrally with the drain electrode 71i on the semiconductor substrate 40 on the upper and lower sides of the drain electrode 44 and on the lower right side in the figure. The planar shape of this conductor 62 is an L-shape formed by combining rectangles of 20 and ξ1, and +1 is formed from the rectangular part G2a on the MESFET 51 side and the rectangular part G2b on the MESFET 51 side, which increases the width of the gate width w1. The ground conductor 6 on the upper and lower sides of the rectangular portion 62a of the conductor 62 in the figure
1aJ= and the semiconductor substrate 4 in the vicinity of the ground conductor Gla
0, an insulator layer 64 made of a rectangular dielectric material is formed, and the insulator layer 64 and the rectangular portion G of the conductor 62 are further formed.
2a of the semiconductor substrate 40 in the vicinity of the insulator layer 64.
A conductor 63 is formed on the second layer and the insulator layer 64.

The conductor 63, the insulator layer 64, and the ground conductor Gla form a metal-insulator-metal capacitor (hereinafter referred to as M I M
It's called a capacitor. )68.

A bias supply terminal 38 is connected to this conductor 63.

From the end G3a of the conductor 63 on the semiconductor substrate 40 to the conductor 62
Impurity ions are implanted in advance into the semiconductor substrate 40 up to the upper and lower ends 62aa of the rectangular portion 62a in the figure, thereby forming the resistor 46.

Therefore, the conductor 62 is the resistor 46, the conductor 63, and the insulator layer 6.
4 to the ground conductor 61a.

A rectangular conductor 65 is located below the end of the rectangular portion 62b of the conductor 62 and located on the semiconductor substrate 40''.
Here, the conductor 65 is connected to one side of the gate length g of the gate electrode 52. An insulating layer (not shown) made of a dielectric material is formed between this conductor 65 and the rectangular portion 62b of the conductor 62, and this insulating layer and the conductors 62 and 65 constitute an MIM capacitor 70. Therefore, conductor 62 is connected to conductor 65 via the insulator layer.

The semiconductor substrate 40 from the upper and lower ends of the conductor 65 (i5a to the portion 61aa near the end 65a of the ground conductor 61)
Impurity ions are implanted in advance into the resistor 47, thereby forming the resistor 47. Therefore, the conductor 65 is connected to the ground conductor 61a via the resistor 47.

On the ground conductor 61a on the upper and lower sides of the drain electrode 5a of the MESFET 51, and between the ground conductor 61a and the drain electrode 5a.
An insulator layer 67 made of a dielectric material is formed on the semiconductor substrate 40 between the semiconductor substrate 40 and the gate width W! A rectangular conductor 66 is formed integrally with the drain electrode 54 on the insulating layer 67. This conductor 66, insulator layer 6
7 and the ground conductor 61a form an MIM capacitor 69, whereby the drain electrode 54 of the MESFET 51 is connected to the ground conductor 61g via the conductor 66 and the insulator layer 67. Further, a bias supply connection terminal 39 is connected to this conductor 66 .

The conductor 71 of the output slot line 16 is connected to the source electrode 5 on the semiconductor substrate 40 on the upper and upper right sides of the source electrode 53 in the figure.
It is formed integrally with 3. Here, the planar shape of the conductor 71 is a substantially rectangular shape with a sufficiently wide gate length g and width in the direction compared to the interval Q3, and the conductor 71 is a ground conductor (3
1a and are spaced apart from each other by a predetermined distance a3 and coplanar with each other. Therefore, conductor 7! is connected to the source electrode 53, and the output slot line 16 is connected by the conductor 71 and the ground conductor 61a.
It consists of

As described above, by forming 1v1, it is possible to configure a line conversion circuit between the input coplanar line 12 and the output slot line 16, and the high frequency equivalent circuit of the monolithic integrated circuit of this second embodiment is as follows. As shown in the figure, it has the same effect as the first embodiment described above.

Third Embodiment FIG. 4(A) is a plan view of a monolithic integrated circuit for line conversion between an input slot line 16 and an output coplanar line 12, which is a third embodiment of the present invention. (B
) is a longitudinal sectional view taken along line DD' in FIG. 4(A). The vertical cross-sectional view taken along line nn' in FIG. 4(A) is the same as FIG. 3(t3) except that the conductor 15 becomes the conductor 73 and the ground conductor 01a becomes the ground conductor 72a. In FIGS. 4(A) and 4(B), the same parts as in the above-mentioned drawings are designated by the same reference numerals.

The circuit of this third embodiment is different from the circuit of the second embodiment as follows: (1) The input Cacobrenner line 12 is replaced by the input slot line 16.
In addition, the output slot line 16 is connected to the output coplanar line 1.
(2) MES F IE'r
51 has replaced the MESFE'r 51a having two gate electrodes 52a, 52b, two drain electrodes 54a, 54b and a source electrode 52a; (3) the conductor 15 has replaced the conductor 73 according to (1) above; In addition, the conductor 71 replaced the conductor 74, and the ground conductor 61a replaced the ground conductor 72a and 72b, and (4) due to the above (2),
Two Mr~1 capacitors 69a and 69b connected to the train electrodes 54a and 54b, respectively, are formed.

The above differences will be explained in detail below.

A conductor 73 is disposed on the semiconductor substrate 4θ on the upper and upper left sides of the source electrode 43 of the MESFET 41 in the figure, at a predetermined distance a distance from the ground conductor 72a, and integrally with the source electrode 43 and coplanar with the ground conductor 72a. It is formed. The planar shape of this conductor 73 is a substantially rectangular shape that has a width in the gate length g+ direction that is sufficiently wider than the above-mentioned interval Q.
A part of the side in the gate width w+ direction of No. 3 is connected to the source 71 pole 43.

Further, the ground conductor G of the second embodiment is different from that of the second embodiment except that the ground conductor 72a is not formed on the upper left edge of the substrate 40 in the figure.
The ground conductor 72a is formed in the same manner as the MESFET 51 on the left side of the diagram, and is spaced apart from the center conductor 74 of the output slot line 12 by a predetermined distance. The ground conductor 72a and the conductor 73 constitute the input slot line 16.

The ground conductor 72bh<MESFET 51a is formed on the semiconductor substrate 40 on the upper and upper right sides of the figure, spaced apart from the conductor 73 by a predetermined distance. The ground conductor 72b has a substantially rectangular planar shape with a gate length g and a width in the direction that are sufficiently wider than the width A and the interval g, and the ground conductor 72b is separated from the conductor 74 by a predetermined distance e. It is formed in a coplanar relationship with the conductor 74 and the ground conductor 72a.

After forming an active layer 55a+ by implanting impurity ions from the upper surface of the semiconductor substrate 40 at the same position as the MESFET 51 of the second embodiment, two gate electrodes 52 are formed.
a and 521. are formed integrally with the conductor 65 on the active layer 55a at a predetermined distance from the substantially central position of the active layer 55a where the source electrode 53a is formed. Here, each planar shape of the gate 7Ii poles 52a, 52b is a rectangular shape with a long side of the gate width W and a side of the gate length g, and the gate width W of the gate electrodes 52a, 52b. , are parallel to the longitudinal sides of the center conductor 74 of the output coplanar line 12, and each gate electrode 52
Each side of the gate length g and direction of a and 52b is the conductor 6 described above.
Connected to 5.

Furthermore, the source electrode 53a is connected to both gate voltages +'U3.
2a and 52b and are formed integrally with the conductor 74 on the active layer 55a at a predetermined distance apart. The shape of the 5II-plane of the source electrode 53a is a rectangular shape, and the longitudinal side of the electrode 53a is parallel to the gate 71 pole 5.
The gate width W of 2a and 52b is parallel to the side in the direction.

Further, two drain electrodes 54a and 54b are provided on the outside of the gate 410 poles 52a and 52b, which are opposite to the side on which the source electrode 53a is formed, and are arranged as "biped gate 7TI poles 52a and 52b, respectively". Conductors (i6a and 66b) are formed integrally with each other at intervals on the operating layer 55a.The planar shape of the drain electrodes 54a, 54b is rectangular, and the longitudinal sides of the electrodes 54a, 54b is the longitudinal gate width W of the gate electrodes 52a and 52b.

parallel to the direction edge.

The drain 71 of MESFET 51a and the ground conductors 72a and 72b on the upper and lower sides of the pole 54a and the upper side of 54b in the drawing, and the ground conductors 72a and 72b and each drain 7 [1
On the semiconductor substrate 40 between 1iu54a and 54b,
Insulators fi 67a and 67b made of dielectric material are formed, respectively, and rectangular conductors 66a and 66b having a gate width W are formed on insulator layers 67a and G, respectively.
The drain electrodes 54a and 54b are integrally formed on the drain electrodes 7b. The conductor 66a, the insulator layer 67a, and the ground conductor 72a form an MIM capacitor 69a, whereby the drain electrode 54a of the MES FET 51a is connected to the ground conductor 72a via the conductor 66a and the insulator layer 67a. . Similarly, a MIM capacitor 69b is formed, and the drain 71 pole 54b of the MESFE'I" 51a is connected to the ground conductor 72b via the conductor 66b and the insulator Ft67b. Note that the bias supply terminal 39 is connected to the conductor GCia. Connected.

Furthermore, the gate width of the gate electrodes 152a, 52b, the drain electrodes 54a, 54b, and the source 7IXt453a, the substantially central part in the direction and the conductor 66 in the vicinity
On a and f3Gb, an insulator Iil? made of, for example, Sin, X5iN, or phytoresist (in this case removed later). After forming I90, the connecting conductor 76, which is insulated from the goo 1 electrodes 52a, 52b and the source electrode 53a via the insulating layer 90, is connected to the astringent conductor G on the insulating layer 90.
6a and 66b near the insulator layer 90, and the conductors G6a and 661) are electrically connected via the connection conductor 76.

As described above, the drain electrodes 54a, 54b,
The gate electrodes 52a, 52b and the source electrode 53a constitute a MESFET 51a.

The conductor 74 is connected to the ground conductors 72a and 72b, respectively. MES 2b is integrally connected to the source electrode 53a and coplanar with the ground conductors 72a and 72b, separated by a predetermined interval sufficiently narrower than the width in the gate length g and direction of the MES 2b.
It is formed on the semiconductor substrate 40 on the right side of the PET 51a in the figure. The conductor 75 has a rectangular planar shape with a predetermined width. One side of the width g1 of the conductor 75 in the gate length g2 direction is connected to one side of the source electrode 53a in the gate length g2 direction.

This conductor 74 and ground conductors 72a and 72b constitute a coplanar line 12.

+11 as above? Assuming that a line conversion circuit between the input slot line 16 and the output coplanar line 12 can be constructed by constructing the following, the high frequency circuit of the monolithic integrated circuit of this third embodiment is as shown in FIG. This achieves the same effect as the first embodiment described above.

Fourth Embodiment FIG. 5 (Δ) is a plan view of a monolithic integrated circuit for line conversion between the input slot line 12 and the output microstrip line 75, which is the fourth embodiment of the present invention.
FIG. 5 (■) is a longitudinal cross-sectional view taken along the No. 1-E' line in FIG. 5 (Δ). In FIGS. 5(Δ) and ([1), the same parts as in the above-mentioned drawings are designated by the same reference numerals.

The circuit of the embodiment shown in FIG. 4 differs from the circuit of the second embodiment in that (1) the output slot line 16 has replaced the output microstrip line 75, and (2) the MES on the output side
The via pole 80 is formed on the ground conductor Gla on the lower left side of the figure of the FET 51; (3) the conductor 71 replaces the conductor 75 in ('1) above; and (4) the ground conductor 71 is placed under the semiconductor substrate 7IO. A ground conductor 60 is formed on the surface. The above differences will be explained in detail below.

In the ground conductor 61a, the ground conductor G of the second embodiment
In comparison with la, the ground conductor 61a is located at the lower left edge of the semiconductor substrate 40 in the figure and is on the left side of the MrM capacitor 69 in the figure.
part is not formed.

Further, a substantially cylindrical via hole 80 is formed in the ground conductor Gla, the semiconductor substrate 40, and the ground conductor 60 in the vicinity of the right side of the MIM capacitor 69 in the figure, and a conductor 80a is formed on the inner peripheral surface of the via hole 80. be done. Thereby, the ground conductor 61a is connected to the ground conductor 60 via the conductor 80a of the via hole 80.

A conductor 75 is formed integrally with the source electrode 53 on the semiconductor substrate 40 on the upper side and the upper right side of the M[diagram of the ESFET 51] plate. The planar shape of the conductor 75 is a substantially rectangular shape having a length g and a width ρ in the direction, and the upper left end of the conductor 75 in the figure is partially cut off. One side of the conductor 75 in the direction of gate width W is connected to one side of the source electrode 53 in the direction of gate width W. Ground conductor 6 on the bottom surface
Since the conductor 75 is formed on the semiconductor substrate 40 on which 0 is formed, the conductor 75 operates as an output microstrip line.

By configuring as described above, it is possible to configure a line conversion circuit between the human horn coplanar line 12 and the output microstrip line 75, and the high frequency circuit of the monolithic integrated circuit of this fourth embodiment is As shown in the figure, it has the same effect as the first embodiment described above.

In the fourth embodiment described above, the ground conductor 61a is connected to the ground conductor 60 through the conductor 80a of the via hole 80, but the present invention is not limited to this. You may also connect it.

FIG. 6 is a plan view of a monolithic integrated circuit for line conversion between an input slot line 16 and an output microstrip line 75, which is a fifth embodiment of the present invention. , the same numbers as those in the above-mentioned drawings are given the same reference numerals. Note that the longitudinal cross-sectional view taken along line EE' in FIG. 6 is the same as that in FIG. 5(B) except that the ground conductor (ila) has replaced 72a.

In the circuit of this fifth embodiment, the input side of the semiconductor substrate 40 is configured in the same manner as the input end of the semiconductor substrate 40 of the third embodiment (FIG. 4(A)), and the output side of the semiconductor substrate 40 is The output side of the semiconductor substrate 40 of the fourth embodiment (FIG. 5(A)) is constructed in the same manner as the output side of the semiconductor substrate 40 of the fourth embodiment (FIG. 5(A)).

By configuring as above, the input slot line I
6 and the output microstrip line 75, and the high frequency circuit of the monolithic integrated circuit of this fifth embodiment is as shown in FIG. 1, which is different from that of the first embodiment described above. Has a similar effect.

Figure 7 is a plan view of a monolithic integrated circuit for line conversion between an input microstrip line 81 and an output coplanar line 12, which is a sixth embodiment of the present invention.
In the figures, the same numbers as in the above-mentioned drawings are given the same numbers.

The circuit of this sixth embodiment is the circuit of the third embodiment (
The difference from FIG. 4 (Δ) and (+3)) is that the (+) input slot line 16 has replaced the input microstrip line 81, (2) the ground conductor 60 is a semiconductor
(formed on the lower surface of the plate 40, and (3) due to the above (1), the conductor 73 replaces the conductor 81, and the ground conductor 7 on the left side of the figure of MESFE'r4+
2a, a via hole 82 is formed in the semiconductor substrate 40 and the ground conductor 60 in the same manner as the via hole 80 described in ``U''. The above differences will be explained in detail below.

A conductor 81 is formed integrally with the source electrode 43 on the semiconductor substrate 40 above the source electrode 43 of the MESPET 41, and the shape of the conductor 81 has a gate width, a width in the direction, and a long side. It has a rectangular shape. Here, one side of the width g4 of the conductor 73 is connected to the center portion of the side of the source electrode 43 in the direction of the gate width. As described above, the via pole 82 is formed, and the conductor 82a is formed on the inner peripheral surface of the via pole 82. As a result, the ground conductor 7
2 a is connected to the ground conductor 60 via a conductor 82 a of the via hole 82 . Since this conductor 81 is formed on the semiconductor J, No. 40 having the ground conductor 60 on the lower surface, the conductor 81 operates as a microstrip line.

By configuring as described above, a line conversion circuit between the input microstrip line 81 and the output coplanar line 12 can be constructed. The circuit is as shown in FIG. 1, and has the same effect as the first embodiment described above.

Seventh Embodiment FIG. 8 shows a seventh embodiment of the present invention. 8 is a plan view of a monolink integrated circuit for line conversion between an input microstrip line 81 and an output slot line 16;
In the figures, the same parts as in the above-mentioned drawings are designated by the same reference numerals.

In the circuit of the seventh embodiment, the input end of the semiconductor substrate 40 is configured in the same manner as the input end of the semiconductor substrate 40 of the sixth embodiment (FIG. 7), while the output side of the semiconductor substrate 40 is ,
The structure is similar to the output side of the semiconductor substrate 40 in the second embodiment (FIGS. 3A and 3C).

By configuring as described above, it is possible to configure a line conversion circuit between the input microstrip line 81 and the output slot line 16, and the high frequency circuit of the monolithic integrated circuit of this seventh embodiment is as shown in FIG. Thus, it has the same effect as the first embodiment described above.

Other Embodiments In the above embodiments, MESPET is used as an active element for line conversion and impedance matching.
The present invention is not limited to this, and other types of FETs may be used.

Further, although a microstrip line, a slot line, or a coplanar line is used as the input/output line, the present invention is not limited thereto, and other microwave lines may be used.

[Effects of the Invention] As detailed above, according to the present invention, the first gate grounding
By cascade-connecting a field effect transistor and a second field effect transistor with a common drain, impedance matching can be achieved between the input and output microwave lines, and electrical isolation between the input and output can be achieved. A line conversion device can be realized. Furthermore, since the device of the present invention has the function of an isolator between input and output, and can be made extremely small compared to conventional devices, it is extremely effective in application to various monolithic microwave/millimeter wave integrated circuits. .

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a basic circuit of a line conversion circuit using FET, which is an embodiment of the present invention. Fig. 2 is a circuit diagram of a line between an input coplanar line and an output slot line, which is a first embodiment of the invention. FIG. 3(A) is a plan view of a monolithic integrated circuit for line conversion between an input coplanar line and an output slot line, which is a second embodiment of the present invention; Figure 3 (B) shows Figure 3 (Δ
), FIG. 3(C) is a longitudinal sectional view taken along line c-c' of FIG. 3(A), and FIG. A plan view of a monolithic integrated circuit for line conversion of an example input slot line and an output coplanar line, FIG. 4(r3) is shown in FIG.
) is a vertical cross-sectional view taken along the line DD' of FIG. , FIG. 5(13) is a longitudinal cross-sectional view taken along the line EE' in FIG. 5(A), and FIG. FIG. 7 is a plan view of a monolithic integrated circuit for line conversion between an input microstrip line and an output coplanar line, which is a sixth embodiment of the present invention; The figure is a plan view of a monolithic integrated circuit for line conversion between an input microstrip line and an output slot line, which is a seventh embodiment of the present invention. A perspective view of a microwave line conversion circuit that performs line conversion between a coplanar line and a slot line, which is a conventional example of FIG. FIG. 1θ is a perspective view of a second conventional FET microwave line conversion circuit. 1... Input microwave line, 2.4... Field effect transistor (r;'ET), 3
...Resistance, 5...Output microwave line. Patent applicant: A.T.R. Optical Radio Communication Research Institute Co., Ltd. Representative: Patent attorney: Maeda Hoshi and two others Figure 9 (A)
Figure 9 (B) Meat figure 10

Claims (1)

[Claims] (1) In a microwave line conversion device that connects different microwave lines, a first field effect transistor whose source electrode is connected to the input microwave line and whose gate is grounded, and a drain electrode of the first field effect transistor. 1. A microwave line conversion device comprising: a second field effect transistor having a grounded drain and having a gate electrode connected to the output microwave line and a source electrode connected to the output microwave line.