JPS63186363A - Memory area setting circuit for multi-cpu system - Google Patents

Abstract

PURPOSE:To share and protect a memory by adding the offset values of different numbers to the memory addresses outputted from a CPU and producing the access address of a shared memory from the memory address and the offset value. CONSTITUTION:An offset setting part 4 sets the offset values at every CPU in response to the different numbers. An offset adding circuit 5 adds the 2-bit offset value 8 of the part 4 to an output memory address 9 of a CPU 6 and sends it to a common bus 3 in the form of an access address 7. Therefore the area of a common memory 1 is divided into four pieces in response to four processors 2a-2d. Thus the processors 2a-2d have the equivalent effects as those of an exclusive local memory starting at an address 0. Then these processors can share the memory 1 and the access area of the CPU is specified. Thus the memory 1 is easily protected.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a multi-CPU system in which one memory is shared by multiple CPUs, and in particular, the present invention relates to a multi-CPU system in which one memory is shared by multiple CPUs.
The present invention relates to a memory area setting circuit that divides and sets each memory area.

(Prior Art) Conventionally, in this type of multi-CPU system, when one memory is shared by a plurality of CPUs, the area of the shared memory is set as the same area when viewed from all the CPUs.

That is, since the memory area was set using software, the system configuration was such that all CPUs shared the entire memory area.

(Problems to be resolved by the invention) The above-mentioned conventional method is applicable to multiple
This is because the purpose was to communicate between each CPU in the PU system and to store shared data.

By the way, in recent years, the load on the bus has been reduced due to the adoption of cache memory, etc., so that it has become possible to implement the memory that each CPU conventionally had as a dedicated local memory on a single memory.

In this case, in the conventional method, it became necessary for software to handle all divisions of areas on the shared memory. This required modifications to the program, especially the operating system. In addition, in the conventional method, not only the memory area accessed by a specific CPU but also the area for other CPUs is always accessible, which poses a problem in terms of memory protection. was there.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory area setting circuit for a multi-CPU system that can divide and set the area of one memory for each of a plurality of CPUs with a simple configuration. With the goal.

(Means for Solving the Problems) Means provided by the present invention in order to solve the above-mentioned problems and achieve the above object is to connect a plurality of processing devices each including a CPU and one memory to a common unit. interconnected by a bus,
A multi-CP that shares one memory among the plurality of processing devices.
The U system includes an offset setting means for setting mutually different offset values according to the total number of processing units, and a means for adding the offset value to a memory address output by the CPU to access the memory. The present invention is characterized in that it includes an access address setting means for outputting as an access address.

(Example) Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a conceptual diagram of address translation.

In FIG. 1, a common bus 3 is connected to a common memory 1 and a plurality of processing devices 2a, 2b, 2c, and 2d. Each processing device 2a, 2b, 2c
, 2d includes a CPU 6, an offset setting section 4, and an offset adding circuit 5. To explain the processing device 2a as a representative, the CPU 6 is an offset adding circuit 5.
The offset adding circuit 5 is connected to the common bus 3. The offset setting section 4, which has a built-in switch for setting the number of the CPU 6 assigned in advance, sets the offset value according to the CPU number, which differs for each CPU, and outputs this offset value to the offset adding circuit 5. The internal configurations of the processing devices 2b to 2d' are also the same as the processing device 2a.

As shown in FIG. 2, the offset adding circuit 5 is connected to the CPU 6
Offset setting section 4 to memory address 9 that has been output from
Add an offset value 8 consisting of 2 pits set in ,
It is sent to the common bus 3 as the access address 7. As a result, the area of the common memory 1 is divided into four areas corresponding to the four processing devices 2a, 2b, 2c, and 2d as shown in FIG.
2b, 2c, and 2d each have the effect of holding dedicated memory starting from each location in O and rl11.

Note that the number of bits of the offset value 8 is not limited to 2 bits, but is formed with an appropriate number of bits depending on the number of processing devices, and a different offset value is set for each CPU.

(Effects of the Invention) As explained above, according to the present invention, a different number corresponding to each CPU is added as an offset value to the memory address that has been output from each CPU, and this memory address and offset value are common. By generating a memory access address, an effect equivalent to having a dedicated local memory for each CPU can be obtained.

Further, the programs of each CPU do not need to be aware of the fact that they share a common memory.

That is, since each CPU is equivalent to holding a dedicated memory starting from address O, each processing device can share memory without changing the operating system.

Furthermore, since the area that can be accessed by each CPU is specified, memory protection for each CPU is easy and reliable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a conceptual diagram of address translation in this embodiment. 1... Common memory, 2a, 2b, 2c,
2d... Processing device, 3... Common bus, 4... Offset setting section, 5... Offset addition circuit, 6...
CPU, 7...Access address, 8...Office toy direct, 9...Memory address.

Claims (1)

[Scope of Claims] A multi-CPU system in which a plurality of processing devices each having a built-in CPU and one memory are interconnected through a common bus, and the one memory is shared by the plurality of processing devices, comprising: an offset setting means for setting mutually different offset values in accordance with the total number of processing units; and an access address for adding the offset value to a memory address output by the CPU and outputting the result as an access address for accessing the memory. A memory area setting circuit for a multi-CPU system, comprising a setting means.