JPS63179614A - Cmos boosting signal generating circuit - Google Patents

Abstract

PURPOSE:To boost a level at a high speed without causing any latchup with simple structure and low power consumption by inserting a 2nd N-MOSFET in series between a 1st N-MOSFET and a P-MOSFET. CONSTITUTION:The 2nd N-MOSFETQN2 is inserted in series between a drain of a P-MOSFETQP1 and a boosted node N1, and a gate of the 2nd N- MOSFETQN2 is connected to the gate/source connected in common of a 3rd N-MOSFETQN3 whose drain is connected to a power supply and to the source of a 4th N-MOSFETQN4 whose drain and gate are connected to the power supply. Thus, the drain of the P-MOSFETQP1 is always cut off from the potential of a power voltage (VCC) or over. Thus, it is possible to boost a signal at a high speed without a care of causing latchup.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a CMOS circuit mainly composed of CMOS circuits.
This relates to an S boost signal generation circuit.

[Prior art] MOS devices, especially MOS dynamic RAM (D
- RAM), the power supply voltage (
For example, in a read operation of a D-RAM, which may require a potential higher than VCC), as shown in FIG. The charge is read out to the bit line 13 and sent to the sense amplifier 1.
5 to distinguish between "1" and "0". Before reading, the bit line 13 is normally set to ■. At this time, as shown in the potential diagram shown in FIG. 6, even if the word line 12 signal Vo is applied to the gate of the access transistor 11, the channel 16 under the gate The potential of is (Vcc-V)
Therefore, if the memory cell capacity is C8, only the charge of Cs
It can be seen that the data cannot be read out, and the read margin is lost. Further, in the case of a write operation, the potential of the bit line 13 is set to VCC or ground potential (Vss) by an external input signal, and a high potential or a low potential is written to the charge storage node N3 through the access transistor 11. When writing a high potential, the word line signal is V
If it is a CC level, only the level of vcc-1 is written to N for the same reason as explained in the above read operation, which deteriorates refresh characteristics and soft error resistance characteristics. In order to eliminate such losses, the word line signal must be set to V8. It is necessary to boost the voltage to more than +V.

Conventionally, internal signals ■. In order to boost the voltage above
A circuit consisting only of a capacitor and an N-MOS transistor has been used. However, if the circuit is constructed using only N-MOS (N-MOS) transistors, there are disadvantages in that the circuit becomes complicated, a large number of transistors are used, and power consumption becomes large.

In order to reduce power consumption with a simple circuit, 0MOS
However, if the potential of the source or drain of the P-MOS transistor constituting the CMOS inverter rises above VCC, a so-called latch-up phenomenon will occur and the device will be destroyed.

FIG. 7 shows a conventional CMOS boost signal generation circuit that is configured with 0MOS and can avoid rough drop.
FIG. 8 shows its operation timing chart. In both figures, φ is a trigger signal, QPI is a P-MOS) transistor, QNI, QNz, Q■ is an N-MOS) transistor, C is a MOS capacitor, D, , D are delay circuits, Nl, N2. N3 and N4 are nodes.

The operation of the circuit shown in FIG. 7 will be briefly explained below with reference to FIG.

When the trigger signal φ is at “H” level, the transistor QP
1 is off, transistor QNI is on, and the potential of node N1 is VSS, so transistor QN2 is on.

Next, when the trigger signal φ becomes "L" level, the transistor QPI is turned on and the transistor QNI is turned off. At this time, the transistor Q□ is initially in the on state due to the delay circuit D1, so the node N1 begins to be charged through the transistors Q, , Q, , and at the same time, the node N
Since the potential of node N1 rises to VCC+α by self-boosting, the node N1 is eventually charged to VCC. At this time, the VCC level of the node N1 is not transmitted to the node N3 because of the delay circuit D2, and the node N3 is 8. level, and the capacitor C1 is ■. , is charged. φt
falls to “L” and after a while, node N2 becomes VSS.
, and the transistor Q■ turns off. As a result, the drain node N4 of the transistor QP is connected to the transistor QN! It is cut off from node N1 by , and no rough rise occurs even if node N1 rises above VCC. A while after node N2 drops to VSS, node N3 drops to V. C, the charge stored in the capacitor C1 is released to the node N1, and the potential of the node N1 is boosted to more than VCC.

[Problem that the invention seeks to solve]

Since the conventional CMOS boost signal generation circuit is configured as described above, in order to prevent latch-up, the delay time Δt2 from the falling edge of the trigger signal φ to the rising edge of the node N3 is set as shown in FIG. It is necessary to take a delay time greater than Δ1° from the fall of the trigger signal φ until the potential of the node N2 falls to VCC, which causes the problem that the timing of raising the potential of the node Nl from VCC to VCC+ΔV is delayed. Ta. Due to this problem, for example, the rise of the D-RAM word line signal to VCC+ΔV is delayed, which is a disadvantage in use, such as the inability to speed up the access time of the D-RAM. It was something that would come out.

This invention was made in order to solve the above-mentioned conventional problems, and uses a CMOS circuit, which has the advantages of a simple structure, low power consumption, and high speed without the need for a latch amplifier. An object of the present invention is to obtain a CMO8 boost signal generation circuit that can generate a boost signal higher than the power supply voltage.

[Means for solving problems]

The CMOS boost signal generation circuit according to the present invention is a P-MO
A second N-MOSFET is inserted in series between the drain (source) of the SFET and the node to be boosted, and the second
The gate of the N-MOSFET was connected to the commonly connected gate and source of a third N-MOSFET whose drain was connected to the power supply, and to the source of a fourth MOSFET whose drain and gate were connected to the power supply. It is something.

[Effect]

In the CMOS boost signal generation circuit according to the present invention, P-
A second N-MOSFET inserted between the drain of the MOSFET and the node to be boosted allows the P-MO
Since the drain of the SFET is always cut off from a potential higher than VCC, it is possible to boost the signal at high speed without worrying about ruff-up.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of a CMOS boost signal generation circuit according to an embodiment of the present invention.

QH, are the same first P-MOS FE as in Fig. 7, respectively.
T, the first N-MOSFET. QMz is the first P
A second N-MOSF inserted in series between the drain of MOS FET Q p + and the node to be boosted which is the drain of the first N-MOSFETQ□
E T , QH3 is a third N-MOSFET whose drain is connected to the power supply and whose gate and source are connected to the gate of the second N-MOSFET, and QH4 is a third N-MOSFET whose drain and gate are connected to the power supply and whose source is connected to the above-mentioned second N-MOSFET. 2 N-MOS
A fourth N-MOSFET connected to the gate of the FET.

FIG. 2 shows a timing chart of the operation of the circuit shown in FIG. 1 above.

Next, the operation will be explained. At time t0, the trigger signal φ,
is at "H" level, transistor 0 is off, Q,
, is on, so node Nl.

Both N3 are at VSS level. Further, the node N2 is charged to VCc-V by the transistor QN4. Here, ■4 is the threshold voltage of Q□.

Transistor Q,1 is on, Q□ is off, transistor QNz is not related to φ1 (because it is on, node N1
The potential of begins to rise. At the same time, the potential of node N2 also rises above VCC due to self-boosting, but VCC+Vtk! It will never go higher than that. Here, V tk2 is the threshold voltage of Qo, and QNI
The threshold voltages of and C8 are set to be the same. When node N2 rises to vcc+vtht, node Nl is charged to VCC.

At this time, the potential of the node N3 is set to VS by the delay circuit D3.
Therefore, the MOS capacitor C1 is also charged to VCC. At time t2, the vec level of node N1 is transmitted to node N3 through delay circuit D3, and node N3
The potential of increases to VCC.

Therefore, the charge stored in the MOS capacitor C1 is released to the node N1, and the potential of the node N1 becomes VCC+
It increases to ΔV. At this time, the potential of the node N4 does not rise above VCC because of the transistor QN2.

A circuit diagram of another embodiment of the present invention is shown in FIG. 3, and a timing chart of its operation is shown in FIG.

In this embodiment, the boosting means for boosting the potential of the node N1 includes three N-MOSFETQNs, QNilQ
Two MOS capacitors C2, CI (capacitance C
2<capacitance CI) and a delay circuit D2. φ
Reference numeral 11 denotes a trigger signal substantially synchronized with the trigger signal φ.

In this embodiment, the MOS capacitor C1 is connected to the transistor Q at time 1. At the time of VC, -V
stomach? (v) is QN? Since the capacitance of MOS capacitor C2 is much smaller than that of MOS capacitor C1, the time it takes for the potential of node N1 to rise to VCC after the trigger signal φ starts to fall is (1g −1+ ) can be shortened, and the timing at which the trigger signal φt2 falls can be made earlier, making it possible to further speed up the boosting of the node N1.

〔Effect of the invention〕

As described above, according to the present invention, in the CMOS boost signal generation circuit, the second N-MOSFET is replaced with the P-MOS
By inserting the P-MOSFET in series between the FET and the first N-MOSFET, the drain of the P-MOSFET is always canted off from a potential higher than vce, resulting in a simple structure, low power consumption, and no latch-up. This has the effect of providing a CMOS boost signal generation circuit that can boost the voltage at high speed without causing any problems.

[Brief explanation of the drawing]

1 is a circuit diagram of a CMOS boost signal generation circuit according to an embodiment of the present invention, FIG. 2 is a timing chart diagram for explaining the operation of FIG. 1, and FIG. 3 is a circuit diagram of a CMOS boost signal generation circuit according to another embodiment of the present invention. 4 is a timing chart for explaining the operation of the circuit in FIG. 3, FIG. 5 is a diagram showing a general RAM memory cell, and FIG. 6 is for explaining the read operation of the memory cell. potential diagram, Figure 7 is the conventional CMOS
FIG. 8 is a diagram showing an example of a boost signal generating circuit, and is a timing chart diagram for explaining the operation of the circuit shown in FIG. 7. φ is a trigger signal, and Q□ is a P-MOS FET. Q N l , Q N t , Q N s + Q
Na is N-MOSFET, C1 is MOS capacitor, QNS, QNil QNq is 5th degree, 6th degree. 7th
+7) N-MOSFET, C2 is MOS capacitor, φ
t2 is a trigger signal almost synchronized with φ, QNI is N-M
OSFET, D3 is a delay circuit composed of an inverter array with several stages of four teeth.

Claims (3)

[Claims] (1) It has a first P-MOSFET and first, second, third, and fourth N-MOSFETs, the source of the first N-MOSFET is connected to the ground power supply, and the drain is connected to the second N-MOSFET. The source of the first P-MOSFET is connected to the power supply, the drain is connected to the drain of the second N-MOSFET, and the gate of the first N-MOSFET and the first P-MOSFET are connected to the source of the first P-MOSFET. M.O.
The gates of the SFETs are both connected to the trigger signal line, and the drain of the third N-MOSFET is connected to the power supply.
The source and gate of the fourth N-MOSFET are both connected to the gate of the second N-MOSFET, the drain and gate of the fourth N-MOSFET are both connected to the power supply, and the source of the fourth N-MOSFET is connected to the gate of the second N-MOSFET. The threshold voltages of the second MOSFET and the third MOSFET are set equal, and the drain of the first N-MOSFET and the second N-MOSFET are set equal.
1. A CMOS boosted signal generation circuit comprising boosting means for boosting the output voltage of a node connected to the source of an OSFET to a voltage higher than a power supply voltage. (2) The step-up means includes a plurality of MOSFETs whose input terminals are connected to the nodes.
and a MOS capacitor whose first terminal is connected to the node and whose second terminal is connected to the output terminal of the delay circuit. The CMOS boost signal generation circuit described. (3) The boosting means includes a fifth N-MOSFET whose drain is connected to the node and whose gate is connected to the power supply, and a first capacitor whose first terminal is connected to the source of the fifth -MOSFET. a second MOS capacitor with a small capacity; and a sixth N-MOS whose drain is connected to the node and whose gate is connected to the source of the fifth N-MOSFET.
FET, a first MOS capacitor whose first terminal is connected to the source of the sixth N-MOSFET, whose drain and gate are connected to a power supply, and whose source is connected to the sixth N-MOSFET.
- a seventh N-MOSF connected to the source of the MOSFET;
ET; and a delay circuit whose output terminal is connected to the second terminal of the first and second MOS capacitors and whose input terminal is connected to the second trigger signal.
The CMOS step-up signal generation circuit described in .