JPS63175913A - Clock supplying system - Google Patents

Abstract

PURPOSE:To prevent increase of the number of signal lines for supplying a clock among processor units, even if the number of processor units increases, by supplying the clock through a clock bus to processors of all processor units from a clock generator of the processor unit being a master. CONSTITUTION:When a fault occurs in a clock generator C of a processor unit 1, a fault detecting circuit D of this system informs a fact that the fault has occurred, to a controller 5. The controller turns off a control signal Sc1, and also, selects one of processor units 2-4, as a master inn accordance with the procedure determined in advance. For instance, when the controller 5 selects the processor unit 2, the controller 5 turns on a control signal Sc2, and sets the processor unit 2 as a master. Also, by opening an AND gate A of this system, a clock CLK2 outputted from the clock generator C is sent onto a clock bus 6, and supplied to processors P of other processor units 1, 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application: This invention relates to a clock supply system for an information processing device comprised of a plurality of processors.

[Prior Art] Information processing apparatuses that aim to improve system reliability by operating a plurality of processor units in parallel are well known. Figure 2 shows two processor units 10.20
This shows an example of this type of information processing device configured with the following.

Each processor unit 10.20 has a clock generator C
, a fault detection circuit, a processor P, and a selector S for selecting a clock. The selector S of the processor unit IO is supplied with its own clock CLK1 through the signal line &10, and is also supplied with the clock CLK2 of the processor unit 20 through the signal line 1220. Similarly, the selector S of the processor unit 20 is supplied with its own clock CLK2 through the signal line e20, and the clock CLK2 of the processor unit lO is supplied through the signal line QlO.
K1 is supplied.

In this state, when the processor unit 1O is operated as a master and the processor unit 20 is operated as a slave, the selector S of each processor unit 10.20 is set to the signal line 1.
210 side, and each processor P is operated by the master side clock CLK1. Further, when a failure occurs in the clock generator C on the master side, each failure detection circuit reports the failure to each selector S. As a result, the selector S switches the master to the slave and the slave to the master, and switches the clock C applied through the signal line 1220.
LK2 is supplied to each processor P, and this clock CLK
Perform operation according to 2.

[Problems to be Solved by the Invention] By the way, in the conventional device described above, each selector S has a
Clocks from all processor units are supplied via signal lines. Therefore, as the number of processor units increases, the number of signal lines for supplying clocks increases, and the size and quantity of the selector S also increase.

This invention was made against this background, and even if the number of processor units increases, the number of signal lines for supplying the clock does not increase, and the scale and quantity of selectors of the processor units also decrease. The purpose of this invention is to provide a clock supply method that does not increase in number.

[Means for Solving the Problems] In order to solve the above problems, the present invention includes a plurality of processor units each having a clock generator and a processor, and a controller that controls switching of the processor units. In the information processing apparatus configured, a clock bus that transmits the clock output from each of the clock generators to all of the processors, and a connection between each of the clock generators and the clock bus are configured according to instructions from the controller. the controller designates one processor unit as a master, designates all other processor units as slaves, and selects a clock generator of the processor unit designated as the master; The gist is to output the clock on the clock bus.

Further, if a failure occurs in the clock generator of the processor unit designated as the master, the controller changes the master to a slave, selects a new master according to a predetermined procedure, and The clock of the clock generator of the processor unit designated by the processor unit is output onto the clock bus.

[Operation] According to the above configuration, a clock is supplied from the clock generator of one processor unit designated as a master to the clock bus, and this clock is supplied to each processor.

Therefore, even if the number of processor units increases, the number of signal lines for transmitting clocks does not increase. Also,
The scale of the selection means within each processor unit can also be small.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 1 to 4 are the same processor units. Each of these processor units 1 to 4 includes a processor P, a clock generator C, a fault detection circuit, and an AND gate A. The clocks CLK I to 4 outputted from each clock generator C are supplied to the first input terminal of the AND gate A in its own system and to the fault detection circuit. Further, a control signal 5cl=Sc4 from the controller 5 is supplied to the second input terminal of each AND gate A of the processor units 1 to 4, and the AND gate A of any one of the processor units 1 to 4 is opened. . The clock output from the opened AND gate A is then supplied to the clock bus 6. Further, the clock ends of each processor P are respectively connected to the clock bus 6 via signal lines ρI to ρ4. Furthermore, a failure notification is sent from each failure detection circuit to the controller 5.

In such a configuration, when operating the processor unit 1 as a master and the other processor units 2 to 4 as slaves, the controller 5 turns on the control signal Scl and opens the AND gate A of the processor unit 1. As a result, the clock CLKI output from the clock generator C of the processor unit 1 is transmitted on the clock bus 6, and is supplied to the processors P of the processor units 2-4 through the signal lines ρ2-ρ4, respectively. Then, with this clock CLK t,
All processors P are operated.

In this state, the clock generator C of processor unit 1
When a failure occurs in the system, the failure detection circuit of this system notifies the controller 5 of the occurrence of the failure. The controller 5 turns off the control signal Scl and turns off the processor units 2 to 2 according to a predetermined procedure.
4 as the master. For example, if the controller 5 selects the processor unit 2, the controller 5 turns on the control signal Sc2 and makes the processor unit 2 the master. Furthermore, the AND gate A of this system is opened, and the clock CLK2 outputted from the clock generator C is sent onto the clock bus 6, and is supplied to the processor P of the other processor unit 1.degree. 3.4.

In this way, the clock can be supplied to all processor units via the clock bus 6 from the processor unit designated as the master by the controller 5.

[Effects of the Invention] As explained above, the present invention enables a clock bus to be transmitted from the clock generator of the master processor unit to the processors of all the processor units in an information processing device composed of a plurality of processor units. Since the clock is supplied through the processor unit, even if the number of processor units increases, there is no need to increase the number of signal lines for supplying the clock between processor units, or reduce the size and quantity of selectors within the processor unit. It becomes possible to supply clocks to all processors from the clock generator of the processor unit specified by the controller without increasing the number of clocks.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of a conventional information processing apparatus configured with two processor units. 1 to 4... Processor unit, 5...
・Controller, 6...Clock bus, A...
...AND gate (selection means), C...clock generator, D...fault detection circuit, P...processor.

Claims (2)

[Claims] (1) In an information processing device comprising a plurality of processor units each having a clock generator and a processor, and a controller that performs switching control of the processor units, the clock output from each of the clock generators is The controller includes a clock bus for transmitting data to all of the processors, and selection means for turning on/off the connection between each of the clock generators and the clock bus according to instructions from the controller, and the controller is configured to control one of the processor units. A clock supply method characterized in that a processor unit is designated as a master, all other processor units are designated as slaves, and the clock of the clock generator of the processor unit designated as the master is output onto the clock bus. (2) If a failure occurs in the clock generator of the processor unit designated as the master, the controller changes the master to a slave, selects a new master according to a predetermined procedure, and selects a new master according to a predetermined procedure. 2. The clock supply system according to claim 1, wherein a clock from a clock generator of a processor unit designated as a master is output onto the clock bus.