JPS63174308A - Manufacture of semiconductor thin film crystal layer - Google Patents
Manufacture of semiconductor thin film crystal layerInfo
- Publication number
- JPS63174308A JPS63174308A JP506987A JP506987A JPS63174308A JP S63174308 A JPS63174308 A JP S63174308A JP 506987 A JP506987 A JP 506987A JP 506987 A JP506987 A JP 506987A JP S63174308 A JPS63174308 A JP S63174308A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- semiconductor thin
- layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 52
- 239000010409 thin film Substances 0.000 title claims abstract description 39
- 239000013078 crystal Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010408 film Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000002844 melting Methods 0.000 claims abstract description 4
- 230000008018 melting Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 25
- 239000010410 layer Substances 0.000 abstract description 50
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 15
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract description 7
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 7
- 229910052682 stishovite Inorganic materials 0.000 abstract description 7
- 229910052905 tridymite Inorganic materials 0.000 abstract description 7
- 239000000377 silicon dioxide Substances 0.000 abstract description 6
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 6
- 230000001590 oxidative effect Effects 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 1
- 238000000137 annealing Methods 0.000 description 6
- 238000010894 electron beam technology Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910007258 Si2H4 Inorganic materials 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、絶縁膜上に半導体薄膜結晶層を成長させる方
法に係わり、特に絶縁膜に設けた開口部をシードとして
用いる半導体薄膜結晶層の製造方法に関する。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method of growing a semiconductor thin film crystal layer on an insulating film, and particularly relates to a method of growing a semiconductor thin film crystal layer on an insulating film, and in particular, a method of growing a semiconductor thin film crystal layer on an insulating film, and in particular, a method of growing a semiconductor thin film crystal layer on an insulating film, and in particular, a method of growing a semiconductor thin film crystal layer on an insulating film. The present invention relates to a method for manufacturing a semiconductor thin film crystal layer.
■ 単結晶薄膜を島状に分離し或いは誘電体により分離
することによって、′素子間の分離が容易且つ完全とな
る。(2) By separating the single-crystal thin film into islands or using a dielectric material, separation between elements becomes easy and complete.
■ 単結晶薄膜上にＭＯＳインバータ回路を作るときは
、基板バイアス効果がないことからスイッチング速度が
速い。■ When creating a MOS inverter circuit on a single crystal thin film, the switching speed is fast because there is no substrate bias effect.
■゛ 寄生浮遊容量が小さく、高速化をはかり得る。■゛ Parasitic stray capacitance is small, allowing for faster speeds.
等の利点を有する。It has the following advantages.
ところで、ＳＯ８では下地基板として単結晶すファイア
が必要となるため、価格が高くなることが問題点として
残っている。そこで、溶融水晶板やＳｉウェハを酸化し
て形成した非晶質５ｔｏ２膜或いはＳｉウェハ上に堆積
したＳｉＮ。However, since SO8 requires a single-crystal sulfur as a base substrate, the problem remains that it is expensive. Therefore, an amorphous 5to2 film formed by oxidizing a fused quartz plate or a Si wafer, or a SiN deposited on a Si wafer.
５ｉ０２膜上に半導体膜を更に堆積したものを使用する
試みがある。このようなＳＯＩ （絶縁膜上のシリコン
）構造は、最近発達したビームアニール法によって部分
的に可能になっている。即ち、Ｓｉを例にとると、単結
晶Ｓｉ基板を酸化し、５ｉ０２膜を形成した後、この一
部分を除去することによって開口し、次に多結晶Ｓｉ膜
を全面に長によって単結晶化し、さらにビームの走査方
向に沿って５ｉ０２膜上の多結晶Ｓｉ膜もそれに引続き
単結晶化されると云うものである。There have been attempts to use a semiconductor film further deposited on the 5i02 film. Such SOI (silicon-on-insulator) structures are made possible in part by recently developed beam annealing techniques. That is, taking Si as an example, a single crystal Si substrate is oxidized to form a 5i02 film, a portion of this is removed to form an opening, then a polycrystalline Si film is made into a single crystal by length over the entire surface, and then a 5i02 film is formed. The polycrystalline Si film on the 5i02 film is subsequently turned into a single crystal along the beam scanning direction.
しかしながら、この種の方法にあっては次のような問題
があった。即ち、開口部上に被着したＳｉを溶融せしめ
るのに必要なエネルギーは、５ｉ０２膜上でのそれと比
較して高くなる。これは、Ｓｔの熱伝導率が８１０２の
それよりも大きいため、Ｓｉ基板上のＳｉ膜では熱が基
板下方に伝導していく割合いが大きくなり、基板表面近
くの温度が５ｉ０２膜上のＳｉ膜よりも同一供給エネル
ギー条件の下では低くなるためである。これを解決する
ためにエネルギーを大きくすると、５ｉ０２膜上のＳｉ
膜表面の平滑性が失われる現象が見られ、従来の方法で
は絶縁膜上に表面平坦性の優れたＳｉ単結晶層を得るこ
とは困難であった。そして、３次元ＩＣを実現するには
、この欠点が解決すべき大きな問題となっている。However, this type of method has the following problems. That is, the energy required to melt the Si deposited on the opening is higher than that on the 5i02 film. This is because the thermal conductivity of St is higher than that of 8102, so the rate at which heat is conducted downwards in the Si film on the Si substrate increases, and the temperature near the substrate surface is lower than that of the Si film on the 5i02 film. This is because it is lower than that of a membrane under the same supply energy conditions. To solve this problem, if the energy is increased, the Si on the 5i02 film
A phenomenon was observed in which the smoothness of the film surface was lost, and it was difficult to obtain a Si single crystal layer with excellent surface flatness on the insulating film using conventional methods. In order to realize a three-dimensional IC, this drawback has become a major problem that must be solved.
（発明が解決しようとする問題点） 質の半導体単結晶層の成長を妨げる要因となっていた。(Problem to be solved by the invention) This was a factor that hindered the growth of a high quality semiconductor single crystal layer.
また、上記理由から、３次元ＩＣの製造等に用いる表面
平滑性の優れた半導体単結晶層を得ることは困難であっ
た。Furthermore, for the above-mentioned reasons, it has been difficult to obtain a semiconductor single crystal layer with excellent surface smoothness for use in manufacturing three-dimensional ICs and the like.
本発明上記事情を考慮してなされたもので、その目的と
するところは、再結晶化する半導体薄膜のシード部上と
絶縁膜上との熱的条件を同等のものとすることができ、
絶縁膜上に表面平滑性の優れた良質の半導体単結晶層を
成長させることのできる半導体薄膜結晶層の製造方法を
提供することにある。The present invention has been made in consideration of the above circumstances, and its purpose is to make the thermal conditions on the seed part of the semiconductor thin film to be recrystallized and the insulating film the same,
It is an object of the present invention to provide a method for manufacturing a semiconductor thin film crystal layer, which can grow a high quality semiconductor single crystal layer with excellent surface smoothness on an insulating film.
［発明の目的〕
（問題点を解決するための手段）
本発明の骨子は、再結晶化する半導体薄膜のシード部と
なる下地半導体領域を絶縁膜で下地基板と分離し、シー
ド部から下地基板への熱伝導を小さくし、シード部上の
半導体薄膜と絶縁膜上の半導体薄膜との熱的条件を近付
けることにある。[Objective of the Invention] (Means for Solving the Problems) The gist of the present invention is to separate a base semiconductor region, which will serve as a seed portion of a semiconductor thin film to be recrystallized, from a base substrate by an insulating film, and to separate the base semiconductor region from the base substrate from the seed portion. The objective is to reduce heat conduction to the seed portion and bring the thermal conditions of the semiconductor thin film on the seed portion and the semiconductor thin film on the insulating film closer to each other.
即ち本発明は、半導体単結晶基板上に一部開口部を有す
る絶縁膜を形成したのち、全面に非晶質若しくは多結晶
の半導体薄膜を堆積し、次いでこの半導体薄膜上でエネ
ルギービームを走査して該薄膜を溶融・再結晶化せしめ
る半導体薄膜結晶層の製造方法において、前記再結晶化
せしめる半導体薄膜と前記開口部を介して接続している
下地半導体領域を、予め絶縁膜により前記基板とは分離
するようにした方法である。That is, in the present invention, after forming an insulating film having a partial opening on a semiconductor single crystal substrate, an amorphous or polycrystalline semiconductor thin film is deposited on the entire surface, and then an energy beam is scanned over this semiconductor thin film. In the method for manufacturing a semiconductor thin film crystal layer in which the thin film is melted and recrystallized using a semiconductor thin film, a base semiconductor region connected to the semiconductor thin film to be recrystallized via the opening is separated from the substrate by an insulating film in advance. This is a method that separates the two.
（作用）
上記方法であれば、シード部となる下地半導体領域が基
板とは絶縁膜で分離されるので、シード部領域から基板
への熱伝導が小さくなり、エネルギービーム照射時のシ
ード部上と絶縁膜上との半導体薄膜の温度差が小さくな
る。従って、半導体薄膜に照射するエネルギービームの
量を最適化することができ、絶縁膜上に良質の半導体単
結晶層を形成することが可能となる。(Function) According to the above method, the underlying semiconductor region that becomes the seed portion is separated from the substrate by an insulating film, so that the heat conduction from the seed portion region to the substrate is reduced, and the heat transfer on the seed portion during energy beam irradiation is reduced. The temperature difference between the semiconductor thin film and the insulating film becomes smaller. Therefore, the amount of energy beam irradiated to the semiconductor thin film can be optimized, and a high quality semiconductor single crystal layer can be formed on the insulating film.
（実施例） 以下、本発明の詳細を図示の実施例によって説明する。(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.
第１図（ａ）〜（ｇ）は本発明の第１の実施例方法に係
わる半導体薄膜結晶層の製造工程、を示す断面図である
。まず、第１図（ａ）に示す如く単結晶Ｓｉ基板１１に
ゲート電極１２及びソース・ドレイン１３．１４からな
るＭＯＳトランジスタを形成し、この上に第１の層間絶
縁膜としてのシリコン酸化膜（Ｓｉ０２膜）１５を平坦
に形成する。続いて、ＳｉＯ２膜１５の一部に後述する
ビームアニールの際のシード部となる開口部１６を形成
する。その後、第１図（ｂ）に示す如く、全面に第１の
多結晶Ｓｉ膜１７を堆積し、さらにニーの上にキャップ
層としての５ｉ０２膜１８を堆積する。FIGS. 1(a) to 1(g) are cross-sectional views showing the manufacturing process of a semiconductor thin film crystal layer according to the first embodiment method of the present invention. First, as shown in FIG. 1(a), a MOS transistor consisting of a gate electrode 12 and source/drain 13 and 14 is formed on a single crystal Si substrate 11, and a silicon oxide film ( A Si02 film) 15 is formed flat. Subsequently, an opening 16 is formed in a portion of the SiO2 film 15 to serve as a seed portion during beam annealing, which will be described later. Thereafter, as shown in FIG. 1(b), a first polycrystalline Si film 17 is deposited on the entire surface, and a 5i02 film 18 as a cap layer is further deposited on the knee.
次いで、第１図（ｃ）に示す如く、キャップ層１８を介
して多結晶Ｓｉ層１７に電子ビーム１９を照射し走査す
ることにより、多結晶Ｓｉ膜１７を溶融・再結晶化せし
め、単結晶Ｓｔ層１７′を形成する。ここで、上記電子
ビーム１９のビーム径は１００［μｍφ］、走査速度は
１０［ＣＭ／ｓｅｅ ］とした。さらに、ビーム走査の
際に、該ビームを走査方向と直交する方向に高速偏向（
周波数５０ＭＨｚ、振幅４１ｍ）することにより、電子
ビーム１９を疑似線状ビームとした。Next, as shown in FIG. 1(c), the polycrystalline Si film 17 is melted and recrystallized by irradiating and scanning the polycrystalline Si layer 17 with an electron beam 19 through the cap layer 18 to form a single crystal. A St layer 17' is formed. Here, the beam diameter of the electron beam 19 was 100 [μmφ], and the scanning speed was 10 [CM/see]. Furthermore, during beam scanning, the beam is deflected at high speed in a direction perpendicular to the scanning direction (
The electron beam 19 was made into a pseudo-linear beam by setting the frequency to 50 MHz and the amplitude to 41 m.
次いで、第１図（ｄ）に示す如くキャップ層１８を除去
した後、単結晶Ｓｔ層１７′にゲート電極２２及びソー
ス・ドレイン１３．１４からなるＭＯＳトランジスタを
形成する。さらに、次に形成すべきＳｉ層のシード部と
なるべき部分２１を残し、単結晶Ｓｉ層１７′を酸化し
て５ｉ０２膜２２を形成する。この状態で、単結晶Ｓｔ
からなるシード部２１は、５ｉ０２膜１５．２２により
覆われたものとなり、基板１１とは分離されることにな
る。Next, as shown in FIG. 1(d), after removing the cap layer 18, a MOS transistor consisting of a gate electrode 22 and source/drain 13, 14 is formed on the single crystal St layer 17'. Furthermore, a 5i02 film 22 is formed by oxidizing the single crystal Si layer 17', leaving a portion 21 that will become a seed portion of the next Si layer to be formed. In this state, single crystal St
The seed portion 21 consisting of the 5i02 film 15.22 is covered with the 5i02 film 15.22 and is separated from the substrate 11.
く全面に第２の多結晶Ｓｉ膜（半導体薄膜）２７を堆積
し、さらにこの上にキャップ層としての５ｔｏ２膜２８
を堆積する。A second polycrystalline Si film (semiconductor thin film) 27 is deposited on the entire surface, and a 5to2 film 28 is further deposited on this as a cap layer.
Deposit.
次いで、先と同様に第１図（ｇ）に示す如く、電子ビー
ム２９を照射走査し、多結晶Ｓｉ層２７を溶融・再結晶
化することによって、５ｉ０２膜２５上に単結晶Ｓｔ層
２７′が形成・されることになる。Next, as shown in FIG. 1(g) in the same manner as before, by scanning the electron beam 29 and melting and recrystallizing the polycrystalline Si layer 27, a monocrystalline St layer 27' is formed on the 5i02 film 25. will be formed and done.
このように本実施例方法によれば、絶縁膜としての５ｉ
０２膜２５上に単結晶Ｓｔ層２７′を形成することがで
きる。そしてこの場合、多結晶Ｓｉ膜２７をビームアニ
ールする際には、シード部２１となる下地Ｓｉ領域が５
ｉ０２膜１５゜２５により基板１１と分離されているの
で、シード部２１上と５ｉ０２膜２５上とにおける熱的
条件は略等しいものとなる。このため、ビームアニール
の際に多結晶Ｓｉ膜２７をシード部２１上及び５ｉ０２
膜２５上とで略同じ温度に加熱することができ、良質の
単結晶Ｓｔ層２７′を形成することができる。また、シ
ード部２１上及び５ｉ０２膜２５上における多結晶Ｓｉ
層２７のビームアニール時の温度を略等しくできるので
、ビシムエネルギーを低く抑えることが可能となり１、
ｆ
次いで、第２図（ｃ）に示す如く、先の実施例と同様に
全面に多結晶Ｓｉ層２７及びキャップ層２８を形成し、
電子゛ビーム２９の照射により多結晶Ｓｉ層２７を溶融
・再結晶化する。In this way, according to the method of this embodiment, 5i as an insulating film
A single crystal St layer 27' can be formed on the 02 film 25. In this case, when beam annealing the polycrystalline Si film 27, the underlying Si region that will become the seed portion 21 is
Since they are separated from the substrate 11 by the i02 film 15°25, the thermal conditions on the seed portion 21 and on the 5i02 film 25 are approximately equal. Therefore, during beam annealing, the polycrystalline Si film 27 is
The film 25 can be heated to substantially the same temperature as the film 25, and a high quality single crystal St layer 27' can be formed. Moreover, the polycrystalline Si on the seed part 21 and the 5i02 film 25 is
Since the temperature during beam annealing of the layer 27 can be made approximately equal, it is possible to keep the Visym energy low.
f Next, as shown in FIG. 2(c), a polycrystalline Si layer 27 and a cap layer 28 are formed on the entire surface as in the previous embodiment,
Polycrystalline Si layer 27 is melted and recrystallized by irradiation with electron beam 29.
このような実施例方法であっても、先の実施例と同様の
効果が得られる。また、開口部２６を予め単結晶Ｓｉ層
３１で埋込んでおくことにより、多結晶Ｓｉ層２７をよ
り平坦に形成することができる等の利点がある。Even with this embodiment method, the same effects as in the previous embodiment can be obtained. Further, by filling the opening 26 with the single crystal Si layer 31 in advance, there is an advantage that the polycrystalline Si layer 27 can be formed more flatly.
第３図（ａ）〜（ｄ）は本発明の第３の実施例方法を説
明するための工程断面図である。この実施例方法は、単
結晶ＳＬ基板のシード部を絶縁分離するようにしたもの
である。FIGS. 3(a) to 3(d) are process cross-sectional views for explaining the third embodiment of the method of the present invention. In this embodiment method, the seed portion of the single crystal SL substrate is insulated and separated.
まず、第３図（ａ）に示す如く、単結晶Ｓｉ基板４１上
にシリコン窒化膜（Ｓｉ２Ｈ４）膜４２を形成し、この
Ｓｉ３Ｎ４膜４２をレジスト４３をマスクとしてバター
ニングする。この状態でＢ÷イオン注入を行い、マスク
されていない領域１；ｐ十層４４を形成する。First, as shown in FIG. 3(a), a silicon nitride (Si2H4) film 42 is formed on a single crystal Si substrate 41, and this Si3N4 film 42 is patterned using a resist 43 as a mask. In this state, B÷ion implantation is performed to form an unmasked region 1; p layer 44.
次いで、第３図（ｂ）に示す如く、ＳＬ３Ｎ４４２を通
してプロンプトイオン注入を行い、４５０［”Ｃ］でＮ
２中の熱処理を行い注入層をドより、ｐ型層（基板１１
の表層及びｐ中層４４）は多孔質化するが、ｎ型層（ｎ
中層４５）はそのままである。さらに、９５０［”Ｃ］
の水蒸気酸化を行い、第３図（ｃ）に示す如く、多孔質
化したｐ型層を酸化し、５ｉ０２膜４６を形成する。こ
のとき、プロトン注入で発生したドナーは消滅し、絶縁
層（Ｓｉ０２膜４６）で完全に分離された単結晶領域（
シード部）４７が残ることになる。Next, as shown in FIG. 3(b), prompt ion implantation was performed through SL3N442, and N
2, the injection layer is heated, and the p-type layer (substrate 11
The surface layer and the p-middle layer 44) become porous, but the n-type layer (n
The middle layer 45) remains as it is. Furthermore, 950[”C]
Steam oxidation is performed to oxidize the porous p-type layer to form a 5i02 film 46, as shown in FIG. 3(c). At this time, the donors generated by proton injection disappear, and the single crystal region (
The seed portion) 47 will remain.
次いで、第３図（ｄ）に示す如く、全面に層間絶縁膜と
しての５ｉ０２膜４８を堆積し、この５ｉ０２膜４８の
前記シード部４７上に開口部４９を形成する。その後、
全面に多結晶Ｓｉ膜５０及び図示しないキャップ層を堆
積し、これをビームアニールすることにより、先の実施
例方法と同様に単結晶Ｓｔ層が形成されることになる。Next, as shown in FIG. 3(d), a 5i02 film 48 as an interlayer insulating film is deposited over the entire surface, and an opening 49 is formed on the seed portion 47 of this 5i02 film 48. after that,
By depositing a polycrystalline Si film 50 and a cap layer (not shown) on the entire surface and beam annealing them, a single crystal St layer is formed in the same manner as in the previous embodiment.
なお、本発明は上述した各実施例方法に限定されるもの
ではない。例えば、前記絶縁膜に設ける開口部は直線状
に開口してもよいし、点状に開口してもよい。さらに、
開口部の大きさ等は仕様に層の単結晶層形成の双方に本
発明を適用することも可能である。その他、本発明の要
旨を逸脱しない範囲で、種々変形して実施することがで
きる。Note that the present invention is not limited to the methods of each embodiment described above. For example, the opening provided in the insulating film may be linear or dotted. moreover,
It is also possible to apply the present invention to both the formation of a single crystal layer and the size of the opening, etc., depending on the specifications. In addition, various modifications can be made without departing from the gist of the present invention.
［発明の効果］
以上詳述したように本発明によれば、ビームアニールす
べき半導体薄膜に接触する下地半導体領域の基板への熱
伝導が抑えられるので、シード部及び絶縁膜上の半導体
薄膜の加熱温度を略等しくすることができる。従って、
シード部における半導体薄膜の溶融・再結晶化を容易に
することができ、絶縁膜上に良質の半導体単結晶層を形
成することか可能となる。[Effects of the Invention] As detailed above, according to the present invention, heat conduction to the substrate of the underlying semiconductor region in contact with the semiconductor thin film to be beam annealed is suppressed, so that the semiconductor thin film on the seed portion and the insulating film is The heating temperature can be made substantially equal. Therefore,
It is possible to facilitate melting and recrystallization of the semiconductor thin film in the seed portion, and it is possible to form a high quality semiconductor single crystal layer on the insulating film.
断面図、第２図（ａ）〜（ｃ）は本発明の第２の実施例
方法を説明するための工程断面図、第３図（ａ）〜（ｄ
）は本発明の第３の実施例方法を説明するための工程断
面図である。
膜（半導体薄膜）、１７’、２７’・・・単結晶シリコ
ン層、１８．２８・・・キャップ層、１９．２９・・・
電子ビーム（エネルギービーム）、２１．４７・・・シ
ード部、２２．４６・・・５ｔ０２膜（シード部分出願
人 工業技術院長 飯塚 幸三
第１図Cross-sectional views, FIGS. 2(a) to (c) are process cross-sectional views for explaining the second embodiment method of the present invention, and FIGS. 3(a) to (d)
) is a process sectional view for explaining the third embodiment method of the present invention. Film (semiconductor thin film), 17', 27'... Single crystal silicon layer, 18.28... Cap layer, 19.29...
Electron beam (energy beam), 21.47...Seed part, 22.46...5t02 film (Seed part Applicant Kozo Iizuka, Director General, Agency of Industrial Science and Technology Figure 1)
Claims (3)
形成したのち、前面に非晶質若しくは多結晶の半導体薄
膜を堆積し、次いでこの半導体薄膜上でエネルギービー
ムを走査して該薄膜を溶融・再結晶化せしめる半導体薄
膜結晶層の製造方法において、前記開口部に露出する下
地半導体層領域が前記基板とは絶縁膜により分離されて
いることを特徴とする半導体薄膜結晶層の製造方法。(1) After forming an insulating film with a partial opening on a semiconductor crystal substrate, an amorphous or polycrystalline semiconductor thin film is deposited on the front surface, and an energy beam is then scanned over this semiconductor thin film to form the thin film. A method for producing a semiconductor thin film crystal layer by melting and recrystallizing a semiconductor thin film crystal layer, wherein the underlying semiconductor layer region exposed in the opening is separated from the substrate by an insulating film. .
形成してなるものであることを特徴とする特許請求の範
囲第１項記載の半導体薄膜結晶層の製造方法。(2) The method for manufacturing a semiconductor thin film crystal layer according to claim 1, wherein the semiconductor single crystal substrate is formed by forming a single crystal layer on an insulating film.
単結晶半導体膜をエピタキシャル成長せしめることを特
徴とする特許請求の範囲第１項記載の半導体薄膜結晶層
の製造方法。(3) The method for manufacturing a semiconductor thin film crystal layer according to claim 1, characterized in that, before forming the semiconductor thin film, a single crystal semiconductor film is epitaxially grown within the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506987A JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP506987A JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63174308A true JPS63174308A (en) | 1988-07-18 |
| JPH0793259B2 JPH0793259B2 (en) | 1995-10-09 |
Family
ID=11601097
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP506987A Expired - Lifetime JPH0793259B2 (en) | 1987-01-14 | 1987-01-14 | Method for manufacturing semiconductor thin film crystal layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0793259B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
| US5356510A (en) * | 1991-10-08 | 1994-10-18 | Thomson-Csf | Method for the growing of heteroepitaxial layers |
| US5741733A (en) * | 1994-01-14 | 1998-04-21 | Siemens Aktiengesellschaft | Method for the production of a three-dimensional circuit arrangement |
-
1987
- 1987-01-14 JP JP506987A patent/JPH0793259B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5356510A (en) * | 1991-10-08 | 1994-10-18 | Thomson-Csf | Method for the growing of heteroepitaxial layers |
| US5308445A (en) * | 1991-10-23 | 1994-05-03 | Rohm Co., Ltd. | Method of manufacturing a semiconductor device having a semiconductor growth layer completely insulated from a substrate |
| US5741733A (en) * | 1994-01-14 | 1998-04-21 | Siemens Aktiengesellschaft | Method for the production of a three-dimensional circuit arrangement |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0793259B2 (en) | 1995-10-09 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |