JPS63169751U

JPS63169751U -

Info

Publication number: JPS63169751U
Application number: JP18800987U
Authority: JP
Priority date: 1987-12-10
Filing date: 1987-12-10
Publication date: 1988-11-04

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図、第２
図は本考案に使用するクロツク制御回路の一例を
示すブロツク図、第３図は本考案による受信記録
の一例を示す図である。１……主走査モータ、２……プーリー、３……
ベルト、４……給電板、５……記録針、６……記
録紙、７……スタートパルス発生器、８……記録
紙送りローラー、９……副走査用モータ、１０…
…アンテナ、２１，２２……受信回路、３１〜３
４……メモリ、４０……発振器、５１〜５６……
分周器、６１……クロツク制御回路、６２……ス
イツチ切替回路、７１〜７３……増巾器、８１〜
８９……リレー接点（電子スイツチ）、９１〜９
３……切替スイツチ、１０１，１０３……微分回
路、１０２，１０４……カウンタ。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram showing an example of a clock control circuit used in the present invention, and FIG. 3 is a diagram showing an example of a reception record according to the present invention. 1...Main scanning motor, 2...Pulley, 3...
Belt, 4... Power supply plate, 5... Recording needle, 6... Recording paper, 7... Start pulse generator, 8... Recording paper feed roller, 9... Sub-scanning motor, 10...
...Antenna, 21, 22...Reception circuit, 31-3
4...Memory, 40...Oscillator, 51-56...
Frequency divider, 61... Clock control circuit, 62... Switch switching circuit, 71-73... Amplifier, 81-
89...Relay contact (electronic switch), 91-9
3... Selector switch, 101, 103... Differential circuit, 102, 104... Counter.

Claims

[Claims for Utility Model Registration] 1 A plurality of receiving circuits are provided, a memory group for storing each of the plurality of reception signals received by the receiving circuits, a control circuit for controlling writing and reading to the memory, and a recording stylus that records and scans the recording paper N times (N is an integer of 1 or more) for each scanning period of the received signal, and records each of the plurality of received signals within a time equal to one scanning period of the received signal. A facsimile device is characterized in that signals for one scanning line are sequentially read out from a plurality of memories and recorded within the time that a recording stylus scans a recording paper, thereby simultaneously obtaining a plurality of facsimile images transmitted at the same time. 2. A practical device equipped with frequency dividers 51 and 52 that divide the output from an oscillator and generate write pulses for the memory, and a frequency divider 53 that generates read pulses and supplies them to the clock control circuit 61. A facsimile apparatus according to claim 1 of the patent registration claim. 3 Differential circuits 101 and 10 in FIGS. 1 and 2
3 and the counter circuit 102 of FIGS. 1 and 2,
104, the counter circuits 102 and 104 of FIGS. 1 and 2 alternately generate K clock pulses, and the memories 31 to 34
2. A facsimile apparatus according to claim 1, comprising a clock control circuit configured to supply a clock. 4 Practical use that allows switching between multiple recording and single recording by inserting or removing a 1/2 frequency divider in the middle of the read pulse generation circuit for the memory and the drive circuit of the sub-scanning motor using the changeover switches 91 to 93. A facsimile apparatus according to claim 1 of the patent registration claim.