JPS6316906B2 - - Google Patents

Info

Publication number
JPS6316906B2
JPS6316906B2 JP56117561A JP11756181A JPS6316906B2 JP S6316906 B2 JPS6316906 B2 JP S6316906B2 JP 56117561 A JP56117561 A JP 56117561A JP 11756181 A JP11756181 A JP 11756181A JP S6316906 B2 JPS6316906 B2 JP S6316906B2
Authority
JP
Japan
Prior art keywords
capacitor
chip
power supply
conductor
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56117561A
Other languages
Japanese (ja)
Other versions
JPS57126157A (en
Inventor
Fuirofusukiii Eriotsuto
Paakinson Waado
Uiruson Denisu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Avx Components Corp
Original Assignee
AVX Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AVX Corp filed Critical AVX Corp
Publication of JPS57126157A publication Critical patent/JPS57126157A/en
Publication of JPS6316906B2 publication Critical patent/JPS6316906B2/ja
Granted legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49589—Capacitor integral with or on the leadframe
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10161—Shape being a cuboid with a rectangular active surface
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    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/3011—Impedance

Abstract

In a decoupling arrangement for an integrated circuit device incorporating a lead frame of the sort which includes an elongate metallic web the lead frame provides an integral seat or platform (23, 24) whereon is mounted a decoupling capacitor (C) which is connected in shunting relation of the power supply inputs to the integrated circuit device, the capacitor (C) providing a convenient mounting platform for the integrated circuit chip 12 and also assuring minimal lead lengths between the capacitor and the power supply inputs of the integrated circuit chip. Due to the shortness of such lead lengths and consequent reduction of the inductance reactance of the power supply circuit, efficient dampening of switching transients is achieved with the use of capacitors of much smaller values, in less area than heretofore required in external dampening applications. <IMAGE>

Description

【発明の詳細な説明】 本発明は、集積回路（IC）装置の分野に関し、
特にメモリ回路として利用されるIC装置に関す
る。さらに詳しくいえば、本発明は、改良された
IC装置、および、これに対するリードフレーム
構体であつて改良された減結合特性を有し一層小
形のメモリアセンブリの形成を可能ならしめうる
リードフレーム構体に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the field of integrated circuit (IC) devices.
In particular, it relates to IC devices used as memory circuits. More specifically, the present invention provides an improved
TECHNICAL FIELD The present invention relates to IC devices and lead frame structures therefor that have improved decoupling characteristics and can enable the formation of more compact memory assemblies.

IC装置の利用、特にメモリ回路の要素として
の利用は、広く行なわれている。ICの１つまた
はそれ以上のスイツチング回路が作動せしめられ
ると、電流および電圧トランジエントが発生し、
このトランジエントはメモリシステムの他の要素
に関連をもつ給電回路に注入されることになる。
諸パルスのトランジエント・エネルギーが機能信
号の特性に近くなると、偽情報の偽読取または偽
伝送が起こつて、業界において「ソフトエラー」
として知られているものを生じる可能性がある。 The use of IC devices, particularly as elements of memory circuits, is widespread. When one or more switching circuits of an IC are activated, current and voltage transients occur;
This transient will be injected into the power supply circuitry associated with other elements of the memory system.
When the transient energy of the pulses approaches the characteristics of the functional signal, false readings or false transmissions of false information occur, known in the industry as "soft errors."
This can result in what is known as

ソフトエラーの発生例を減少させるためには、
ICの給電入力を橋絡する減結合または側路キヤ
パシタを用いて、トランジエント・エネルギー
（雑音）を吸収し、それが給電接続を経てIC回路
の残余部分へ伝送されないようにするのが通例で
ある。 In order to reduce the occurrence of soft errors,
It is customary to use a decoupling or shunting capacitor to bridge the power supply input of an IC to absorb transient energy (noise) and prevent it from being transmitted through the power supply connection to the rest of the IC circuitry. be.

従来は、リードフレーム形のICを用いた回路
においては、それぞれのICに隣接し且つその外
部にある印刷回路（PC）板上にキヤパシタを取
付け、該キヤパシタの導線が印刷回路配線を経て
ICの給電該子間に接続されるようにすることに
よつて減結合が行なわれてきた。導線の長さと配
線との直列合成によつてキヤパシタの実効インピ
ーダンスが増加せしめられるので、キヤパシタ
の、特に動的ICメモリ回路において特徴的に発
生する高周波電流トランジエントを分路する働き
は低下する。しかも、これらの回路においてはメ
モリ内に記憶されたデータを正しく保持するため
に、給電を±10％の範囲に維持することが要求さ
れる。そのため、従来は使用されるべきキヤパシ
タの値は0.1ないし2μFの程度のかなりの大きさの
ものであつた。 Conventionally, in circuits using lead frame type ICs, capacitors are mounted on a printed circuit (PC) board adjacent to and external to each IC, and the conductors of the capacitors are routed through the printed circuit wiring.
Decoupling has been accomplished by making connections between the IC's power supplies. The series combination of conductor length and wiring increases the effective impedance of the capacitor, thereby reducing its ability to shunt high frequency current transients, particularly those characteristic of dynamic IC memory circuits. Furthermore, in order to correctly retain data stored in the memory in these circuits, it is required to maintain the power supply within a range of ±10%. Therefore, conventionally, the value of the capacitor to be used has been quite large, on the order of 0.1 to 2 μF.

このような比較的大きい電気容量値をもつたキ
ヤパシタは、経費がかさむ上に大きさが大きくな
るので、所望の目的である回路の小形化を困難に
する。 Capacitors with such relatively large capacitance values are expensive and bulky, making it difficult to achieve the desired goal of circuit miniaturization.

要約すると、本発明は、穴あけまたは食刻した
細長い金属帯またはウエブから製造される形式の
改良されたリードフレーム構体であつて、該リー
ドフレームの金属フレーム要素が該リードフレー
ムの給電導体間を分路するキヤパシタを機械的に
支持するように構成されて配置されており、該キ
ヤパシタがICチツプの支持体として役立つよう
になつており、該ICチツプの給電端子が短い導
線部またはジヤンパまたはワイヤ・ボンド・スレ
ツドを経て前記給電導体に従来通りに接続されて
いることを特徴とするリードフレーム構体に関す
るものである。 In summary, the present invention provides an improved lead frame structure of the type manufactured from a perforated or etched elongated metal strip or web, wherein the metal frame elements of the lead frame provide separation between the feed conductors of the lead frame. The capacitor is configured and arranged to mechanically support a capacitor connected to the IC chip, the capacitor serving as a support for an IC chip, and the power supply terminal of the IC chip being connected to a short conductor section or a jumper or a wire. The lead frame structure is characterized in that it is conventionally connected to the feed conductor via a bond thread.

従来公知の減結合回路においては導線の長さが
長い導線によつて作り出される誘導リアクタンス
により発生せしめられる望ましくない給電パルス
またはトランジエントの大きさを不利に増大させ
る重要な因子であること、および、キヤパシタを
ICチツプの給電端子に極めて接近させて配置す
ることにより減結合回路内の導線の長さを減少せ
しめれば小さいキヤパシタンス値でパルス減衰を
行なうことができることは、すでに確認されてい
る事実である。例をあげると、特に制限なしに、
ICチツプに隣接してその給電端子間を内部で分
路するように0.05μFのキヤパシタンス値を挿入す
れば、これまで電流パルスの周波数に応じて0.1
ないし2μFの外部キヤパシタンスを必要としてい
た電流パルスの効果的減衰が可能になる。 that in previously known decoupling circuits the length of the conductor is an important factor that disadvantageously increases the magnitude of undesirable power supply pulses or transients caused by the inductive reactance created by the long conductor; and the capacitor
It is an established fact that pulse attenuation can be achieved with small capacitance values by reducing the length of the conductor in the decoupling circuit by placing it very close to the supply terminals of the IC chip. For example, without any particular restrictions,
By inserting a capacitance value of 0.05 μF adjacent to the IC chip and internally shunting between its power supply terminals, it is possible to
Effective attenuation of current pulses, which previously required an external capacitance of 2 to 2 μF, is now possible.

さらに詳細に述べれば、本発明は、最終的には
導体として作用する間隔をもつた金属要素の格子
形配列を画定するように穴あけされたウエブを包
含する形式のリードフレームであつて、該リード
フレームの諸要素のうちの少なくとも１つが該金
属ウエブの面から偏向せしめられてキヤパシタの
取付座を画定し該キヤパシタをその上に電気的に
も機械的にも支持するようになつているリードフ
レームに関する。該キヤパシタはICチツプの取
付台をなし、該ICチツプの給電端子は該リード
フレームの諸要素に電気的に接続され、該諸要素
は該キヤパシタの諸端子に電気的に接続されて該
諸端子を物理的に支持する。このような状況下に
おいては、減結合キヤパシタとチツプの給電端子
との間の導線の長さは極めて短くされるので、従
来の導線および印刷回路配線によつて通常付加さ
れる誘導リアクタンスは最小化される。 More particularly, the present invention relates to a lead frame of the type that includes a web that is perforated to define a grid-like array of spaced metal elements that ultimately act as conductors; a lead frame in which at least one of the frame elements is deflected from the plane of the metal web to define a mounting seat for a capacitor and to support the capacitor thereon both electrically and mechanically; Regarding. The capacitor serves as a mounting base for an IC chip, the power supply terminals of the IC chip are electrically connected to elements of the lead frame, and the elements are electrically connected to terminals of the capacitor to connect the terminals. physically support. Under these circumstances, the length of the conductor between the decoupling capacitor and the chip's power supply terminals is kept very short, so that the inductive reactance normally added by conventional conductors and printed circuit wiring is minimized. Ru.

このようにして本発明は、適当な回路担持シリ
コンチツプを付加することによりIC装置を形成
しうるようになつている改良されたリードフレー
ム構体であつて、キヤパシタが該チツプの物理的
支持体をなすように該リードフレームの金属性要
素と関連せしめられ、ICチツプの給電入力と該
キヤパシタとの間の導線の長さが最小ならしめら
れることを特徴とするリードフレーム構体を提供
することを目的とする。 The present invention thus provides an improved leadframe structure adapted to form an IC device by the addition of a suitable circuit-bearing silicon chip, the capacitor providing the physical support for the chip. It is an object of the present invention to provide a lead frame structure, characterized in that the length of the conductive wire between the power supply input of the IC chip and the capacitor is minimized. shall be.

本発明のもう１つの目的は、上述の形式のリー
ドフレーム構体を用いて製造されるIC装置を提
供することである。 Another object of the invention is to provide an IC device manufactured using a lead frame structure of the type described above.

本発明のもう１つの目的は、リードフレーム形
成のIC装置、すなわち、打抜かれた金属ウエブ
の骨格要素を用いて製造され且つ給電回路をスイ
ツチング・トランジエントの伝達に対して効果的
に減結合する内部キヤパシタ要素を包含したIC
装置であつて、該キヤパシタのキヤパシタンス値
が外部減結合を利用した場合に要するキヤパシタ
ンス値よりずつと小さくなつているIC装置を提
供することである。 Another object of the present invention is to provide a leadframe-forming IC device, i.e., manufactured using stamped metal web skeletal elements, which effectively decouples the power supply circuit from the transmission of switching transients. IC containing internal capacitor elements
An object of the present invention is to provide an IC device in which the capacitance value of the capacitor is gradually smaller than the capacitance value required when external decoupling is used.

本発明のさらにもう１つの目的は、上述の形式
のリードフレーム構体であつて、自動処理機械装
置によつて扱えるようになつている多数の相互接
続されたリードフレーム要素を包含しており、該
要素がシリコンチツプまたはこれに類するものの
機械的支持体としての機能をも有する内部減結合
キヤパシタを包含しているリードフレーム構体を
提供することである。 Yet another object of the present invention is a lead frame structure of the type described above, comprising a number of interconnected lead frame elements adapted to be handled by automated processing machinery. It is an object of the present invention to provide a lead frame structure in which the elements include an internal decoupling capacitor which also functions as a mechanical support for a silicon chip or the like.

これらの諸目的およびその他の目的を達成する
ための本発明を添付図面を参照しつつ以下詳細に
説明する。 The present invention for achieving these and other objects will be described in detail below with reference to the accompanying drawings.

第１図には、公知の方法によつて食刻または穴
あけされることにより多数の空白領域を形成され
た細長い金属ウエブ１０が示されており、該空白
領域Ｂの間に残存している金属要素Ｍは、内部的
にはICチツプ１２に接続され、外部的にはIC装
置と印刷回路板などとの間に接続される導体を形
成している。 FIG. 1 shows an elongated metal web 10 which has been etched or perforated by known methods to form a number of blank areas, with the remaining metal remaining between the blank areas B. Element M forms a conductor that is connected internally to the IC chip 12 and externally between the IC device and a printed circuit board or the like.

リードフレーム・ウエブ１０は自動処理装置と
係合するための複数の駆動孔すなわちスプロケツ
ト孔１３を包含し、これを利用してこの金属性格
子形配列を完成されたIC装置に仕上げるために
必要な後の各種諸段階を実行しうるようになつて
いる。 The leadframe web 10 includes a plurality of drive or sprocket holes 13 for engagement with automated processing equipment and is utilized to provide the necessary processing for finishing this metallic grid array into a complete IC device. The various subsequent steps can now be carried out.

このリードフレームは一連の導体部１４ａ，１
４ｂ，１４ｃ等および１５ａ，１５ｂ，１５ｃ等
を包含しているが、これらの部分は第６図に示さ
れている完成されたIC装置においては一塊の重
合体材料３６内に実質的に埋没している。 This lead frame has a series of conductor parts 14a, 1
4b, 14c, etc. and 15a, 15b, 15c, etc., but these parts are substantially buried within the mass of polymeric material 36 in the completed IC device shown in FIG. ing.

通常の場合と同様に、導体部１４ａ，１４ｂ，
１４ｃ等および１５ａ，１５ｂ，１５ｃ等は内端
子部１４′ａ，１４′ｂ，１４′ｃ等および１５′
ａ，１５′ｂ，１５′ｃ等を有し、これらに対して
はICチツプ１２の諸端子が後述のようにして接
続される。前記導体部はまた中間端子部１４″ａ，
１４″ｂ，１４″ｃ等および１５″ａ，１５″ｂ，１
５″ｃ等をも有し、これらの部分は、第６図に示
されている完成IC装置から外部回路への接続の
ために突出している外端子部１４ａ，１４ｂ
および１５ａ，１５ｂ等に連なつている。 As in the normal case, the conductor parts 14a, 14b,
14c etc. and 15a, 15b, 15c etc. are inner terminal parts 14'a, 14'b, 14'c etc. and 15'
a, 15'b, 15'c, etc., and various terminals of the IC chip 12 are connected to these as will be described later. The conductor portion also includes intermediate terminal portions 14″a,
14″b, 14″c, etc. and 15″a, 15″b, 1
5"c, etc., and these parts are external terminal parts 14a and 14b that protrude from the completed IC device shown in FIG. 6 for connection to an external circuit.
and 15a, 15b, etc.

以上に説明した範囲では、このリードフレーム
は従来のものと本質的に同じものである。 To the extent described above, this lead frame is essentially the same as the conventional lead frame.

本発明においては、最終的に給電回路への入力
を画定することになる導体部１４ａ，１５ａは、
最初中央橋絡部１６によつて連結されている内端
子端１４′ａ，１５′ａを有する。 In the present invention, the conductor portions 14a and 15a that will ultimately define the input to the power supply circuit are
It has inner terminal ends 14'a, 15'a which are initially connected by a central bridge 16.

本発明におけるリードフレーム構体製造の次の
段階では、中央橋絡部１６を実質的に第１図の中
央切断領域１７と共に切断して、２つの分離され
た金属要素１８，１９を画定する。次に、適宜の
整形機を用いて該要素１８，１９を屈曲し、垂直
脚２１，２２および水平脚２３，２４を画定す
る。 The next step in leadframe structure fabrication in accordance with the present invention is to cut central bridge 16 substantially along with central cut region 17 of FIG. 1 to define two separate metal elements 18,19. The elements 18, 19 are then bent using a suitable shaping machine to define vertical legs 21, 22 and horizontal legs 23, 24.

第４図および第５図から最もよくわかるよう
に、水平脚２３，２４は、好ましくは多層セラミ
ツク形のものであるキヤパシタＣに対する支持台
を画定する。このキヤパシタの終端２５，２６
は、垂直脚２１，２２および水平脚２３，２４に
はんだ付けなどにより電気的かつ機械的に接続さ
れる。 As best seen in FIGS. 4 and 5, the horizontal legs 23, 24 define a support for the capacitor C, which is preferably of multilayer ceramic type. The terminal ends 25, 26 of this capacitor
are electrically and mechanically connected to the vertical legs 21, 22 and the horizontal legs 23, 24 by soldering or the like.

キヤパシタＣは上部表面部分２７を有し、これ
がICチツプ１２の台すなわち支持体をなしてい
る。チツプ１２は随意に、しかし好ましくは、キ
ヤパシタＣの上部表面２７上に付けられたエポキ
シなどの接着剤層２８上に着座せしめられる。そ
の後内端子端１４′ａおよび１５′ａは、導線３０
により通常の様式によつてチツプ１２のそれぞれ
の給電端子Ｐに接続される。 Capacitor C has an upper surface portion 27 that provides a pedestal or support for IC chip 12. Chip 12 is optionally but preferably seated on an adhesive layer 28, such as epoxy, applied to top surface 27 of capacitor C. Thereafter, the inner terminal ends 14'a and 15'a are connected to the conductor 30.
are connected to the respective power supply terminals P of the chip 12 in the usual manner.

以上の説明から、外端子部１４ａが導体部１
４ａを経てキヤパシタＣの終端２６に電気的に接
続されることになるのは明らかである。同様にし
て、外端子部１５ａは導体部１５ａを経て該キ
ヤパシタの終端２５に電気的に接続されることに
なり、この結果、該キヤパシタはICチツプの給
電端子Ｐを橋絡するように配置されることにな
る。 From the above explanation, the outer terminal portion 14a is the conductor portion 1.
It is clear that it will be electrically connected to the terminal end 26 of the capacitor C via 4a. Similarly, the outer terminal portion 15a is electrically connected to the terminal end 25 of the capacitor via the conductor portion 15a, and as a result, the capacitor is arranged to bridge the power supply terminal P of the IC chip. That will happen.

次に、チツプ１２の他の端子Ｔが通常の様式で
導線３０′によりリードフレーム１０のそれぞれ
の内端子端１４′および１５′に接続され、導体間
の分路部Ｓ（第１図）を除去するために格子形配
列の切断が行なわれる。 The other terminal T of chip 12 is then connected in the conventional manner by conductor 30' to the respective inner terminal ends 14' and 15' of lead frame 10, creating a shunt S (FIG. 1) between the conductors. A grid-shaped array cut is made for removal.

リードフレーム、キヤパシタおよびICチツプ
１２を包含する構体が完成された後、この構体を
重合体塊３６内に埋込んでブロツクを形成する。
この重合体ブロツクは諸要素を密封し且つ導体部
を固定位置に保持する。次に、それぞれのユニツ
トを第１図の線３１，３１に沿つて切断し、それ
によつて導体部１４ａ，１４ｂ，１５ａ，１５ｂ
等をウエブの残余部分から分離して、導体部の端
部１４″ａ，１５″ａ等および口出線部１４ａ，
１５ａ等のみが重合体ブロツク１６から突出し
ているようにする。次に、口出線部１４ａ，１
５ａ等を屈曲して印刷回路板の取付孔に挿入で
きるようにする。 After the assembly including the lead frame, capacitor, and IC chip 12 is completed, the assembly is embedded within the polymer mass 36 to form the block.
This polymer block seals the elements and holds the conductors in a fixed position. Next, each unit is cut along lines 31, 31 in FIG.
etc. from the rest of the web, and conductor end portions 14''a, 15''a, etc. and lead wire portions 14a,
15a etc. are made to protrude from the polymer block 16. Next, the lead wire portions 14a, 1
5a etc. are bent so that they can be inserted into the mounting holes of the printed circuit board.

本技術分野に精通する者には知られているよう
に、１つまたは一連の相互接続されたリードフレ
ームであつてそれぞれがキヤパシタを取付けられ
ている該リードフレームを包含しているリードフ
レーム構体は、有用な製品として集積回路装置の
製造業者に供給される。製造業者は、これらのリ
ードフレーム構体を従来の通常の工程におけると
同様に処理する。しかし、従来の工程におけるよ
うにICチツプをリードフレームの金属部に取付
ける代わりに、ICチツプはエポキシ層２８上に
取付けられる。このエポキシ層２８はICチツプ
を取付ける直前にキヤパシタＣの表面２７に付与
されるもので、このエポキシはICチツプを固定
位置にしつかり固着させる手段をなす。製造業者
によつて行なわれるその後の処理工程は、現在そ
れぞれの通常のIC装置の製造において実施され
ている工程と全く同じものである。すなわち、
ICチツプを設置して固着させた後、金属リード
フレームの内端子１４′ａ，１４′ｂ，１４′ｃ等
および１５′ａ，１５′ｂ，１５′ｃ等の適当なも
のと、ICチツプ１２のそれぞれの端子Ｐおよび
Ｔとの間に、導線３０および３０′による種々の
接続が行なわれる。次に、このユニツトを重合体
塊中に埋込んでブロツクを形成した後、該ユニツ
トをウエブの残余部分から切離して口出線部が形
成される。 As is known to those skilled in the art, a leadframe assembly includes one or a series of interconnected leadframes, each having a capacitor attached thereto. , supplied as a useful product to manufacturers of integrated circuit devices. Manufacturers process these leadframe assemblies as in conventional conventional processes. However, instead of attaching the IC chip to the metal portion of the lead frame as in conventional processes, the IC chip is attached onto the epoxy layer 28. This epoxy layer 28 is applied to the surface 27 of the capacitor C immediately before mounting the IC chip, and this epoxy serves as a means to securely hold the IC chip in a fixed position. The subsequent processing steps carried out by the manufacturer are exactly the same as those currently carried out in the manufacture of each conventional IC device. That is,
After installing and fixing the IC chip, connect the inner terminals 14'a, 14'b, 14'c, etc. of the metal lead frame and appropriate terminals 15'a, 15'b, 15'c, etc. to the IC chip. Various connections are made between the respective terminals P and T of 12 by conductive wires 30 and 30'. The unit is then embedded in the polymer mass to form a block and then cut away from the remainder of the web to form the lead line.

以上の説明から、本発明においては、ICチツ
プを取付けるための改良されたリードフレーム構
体であつて、キヤパシタがICチツプおよびその
給電端子の極めて近くに包含されることを特徴と
するリードフレーム構体が開示されていることが
認識されたはずである。キヤパシタとチツプの給
電端子Ｐとの間の接続は、第７図の従来技術にお
ける装置の比較的長い導線３２，３３よりも短い
導線３０にのみ限られているので、回路の誘導成
分は最小限に減少せしめられ、それによつて発生
するスイツチングパルスを減衰させるのに必要な
キヤパシタンスは外部に配置された減結合キヤパ
シタの場合に比較すると実質的に減少せしめられ
る。 From the above description, the present invention provides an improved lead frame structure for mounting an IC chip, which is characterized in that a capacitor is included very close to the IC chip and its power supply terminal. It should have been recognized that it had been disclosed. Since the connection between the capacitor and the power supply terminal P of the chip is limited to a conductor 30, which is shorter than the relatively long conductors 32, 33 of the prior art device of FIG. 7, the inductive component of the circuit is minimized. The capacitance required to attenuate the resulting switching pulse is thereby substantially reduced compared to the case of an externally placed decoupling capacitor.

さらに、本発明においては、内部減衰キヤパシ
タを有し、外形寸法が通常に製造されたIC装置
の場合より大きくない改良されたIC装置を開示
していることを認識すべきである。 Furthermore, it should be appreciated that the present invention discloses an improved IC device having an internal damping capacitor and having external dimensions that are no larger than those of conventionally manufactured IC devices.

本技術分野に精通し本開示を理解した者にはわ
かるように、通常の金属リードフレーム装置にお
いて、該装置の回路担持要素すなわちICチツプ
に対する支持構造を画定し且つ減結合キヤパシタ
として働くキヤパシタ部材を用いるという原理に
存在すると考えられる本発明の精神から逸脱する
ことなく多くの変形および改変が行なわれうる。
従つて、本発明は特許請求の範囲内において広い
意味に解釈されるべきものである。 As will be appreciated by those skilled in the art and having understood the present disclosure, a typical metal lead frame device includes a capacitor member that defines the support structure for the circuit-carrying element or IC chip of the device and acts as a decoupling capacitor. Many variations and modifications may be made without departing from the spirit of the invention which is believed to lie in its principles of use.
Therefore, the present invention should be interpreted broadly within the scope of the claims.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、一連のICリードフレームを画定す
る細長いウエブの短い一部の平面図である。第２
図は第１図の２−２線における垂直断面図であ
る。第３図は、キヤパシタを組込んだ後のリード
フレーム構体の部分平面図である。第４図は、第
３図の４−４線における垂直断面図である。第５
図は、ICシリコンチツプを取付けたリードフレ
ームの拡大斜視図で、該チツプへ延長する接続を
示している図である。第６図は、完成された本発
明のIC装置の平面図である。第７図は、完成さ
れた従来技術のIC装置の平面図である。 １０……金属ウエブ、１２……ICチツプ、１
４ａ，１４ｂ，１４ｃ，１５ａ，１５ｂ，１５ｃ
……導体部、１４ａ，１４ｂ，１４ｃ，１
５ａ，１５ｂ，１５ｃ……外端子部、２
１，２２……垂直脚、２３，２４……水平脚、２
５，２６……キヤパシタの終端、２７……キヤパ
シタの上部表面、３０，３０′……導線、Ｃ……
キヤパシタ、Ｐ……ICチツプの給電端子。 FIG. 1 is a plan view of a short portion of an elongated web defining a series of IC lead frames. Second
The figure is a vertical sectional view taken along line 2-2 in FIG. FIG. 3 is a partial plan view of the lead frame structure after incorporating the capacitor. 4 is a vertical sectional view taken along line 4-4 in FIG. 3. FIG. Fifth
The figure is an enlarged perspective view of a lead frame with an IC silicon chip mounted thereon, showing connections extending to the chip. FIG. 6 is a plan view of the completed IC device of the present invention. FIG. 7 is a plan view of a completed conventional IC device. 10...Metal web, 12...IC chip, 1
4a, 14b, 14c, 15a, 15b, 15c
...Conductor part, 14a, 14b, 14c, 1
5a, 15b, 15c...external terminal section, 2
1, 22... Vertical leg, 23, 24... Horizontal leg, 2
5, 26... End of capacitor, 27... Upper surface of capacitor, 30, 30'... Conductor, C...
Capacitor, P...Power supply terminal for IC chip.

Claims (1)

【特許請求の範囲】 １ 一塊の重合体絶縁材料と、 前記重合体材料内に埋込まれた一体の金属ウエ
ブから形成された金属の格子形配列であつて、前
記格子形配列は前記重合体材料内に同一平面関係
で整列して配置された導体部分を有する複数の導
体部を含み、前記導体部は前記重合体材料から外
方へ延長する外端子部を含み、前記重合体材料内
の１対の前記導体部は支持台を画定する間隔を置
いた内端子部を有し、前記支持台は前記導体部分
の面から変位した１対の間隔を置いた取付部を含
み、前記取付部の各々は前記導体部分の前記面か
ら垂直に延びる垂直脚と、前記垂直脚から延びる
水平脚を含み、前記水平脚は相互に同一平面に整
列されかつ前記導体部分の前記面と平行な面内に
あり、 前記支持台上に取付けられたキヤパシタとIC
チツプの組合せサブアツセンブリであつて、前記
キヤパシタは相対向する平行な端部を含み、前記
端部は金属の終端を含み、前記キヤパシタは前記
端部の間に延びる上部表面と下部表面を含み、ま
た前記ICチツプは前記上部表面と前記ICチツプ
との間に介在する接着剤層により前記キヤパシタ
の前記上部表面に接着され、前記ICチツプは複
数の端子と１対の給電端子を含み、前記サブアツ
センブリは、前記キヤパシタの前記端部の各々が
前記垂直脚のそれぞれ１つと当接関係に配置され
かつ前記キヤパシタの前記下部表面が前記水平脚
上に配置されるように前記支持台上に取付けら
れ、前記接着剤層は前記サブアツセンブリが取付
けられた位置においては前記導体部の平面と整列
して配置され、前記キヤパシタの前記終端の各各
は前記支持台の前記取付部のそれぞれ１つに接続
され、 前記キヤパシタの表面から変位した前記取付部
を前記ICチツプの前記給電端子に接続する第１
の対の導体であつてこれにより、前記ICチツプ
の前記給電端子は前記キヤパシタにより分路が作
られ、 前記キヤパシタの表面から変位した前記ICチ
ツプの前記複数の端子を前記導体部の他の部分に
接続する追加の導線とからなる集積回路装置。Claims: 1. A lattice-like array of metal formed from a body of polymeric insulating material and an integral metal web embedded within the polymeric material, the lattice-like arrangement comprising: a plurality of conductor portions having conductor portions aligned in a coplanar relationship within the material, the conductor portions including outer terminal portions extending outwardly from the polymeric material; A pair of said conductor portions have spaced-apart inner terminal portions defining a support base, said support base including a pair of spaced apart mounting portions displaced from a plane of said conductor portions; each includes a vertical leg extending perpendicularly from the surface of the conductor portion and a horizontal leg extending from the vertical leg, the horizontal legs being aligned in the same plane with each other and extending in a plane parallel to the surface of the conductor portion. and the capacitor and IC mounted on the support base.
a combination subassembly of chips, the capacitor including opposing parallel ends, the ends including a metal termination, and the capacitor including an upper surface and a lower surface extending between the ends; , the IC chip is adhered to the upper surface of the capacitor by an adhesive layer interposed between the upper surface and the IC chip, the IC chip includes a plurality of terminals and a pair of power supply terminals, and the IC chip includes a plurality of terminals and a pair of power supply terminals; a subassembly is mounted on the support such that each of the ends of the capacitor is disposed in abutting relationship with a respective one of the vertical legs and the lower surface of the capacitor is disposed on the horizontal leg; attached, said adhesive layer being disposed in alignment with the plane of said conductor section in the attached position of said subassembly, and each of said terminal ends of said capacitor being attached to a respective one of said attachment sections of said support base. a first one connected to the power supply terminal of the IC chip and connecting the mounting portion displaced from the surface of the capacitor to the power supply terminal of the IC chip;
a pair of conductors, whereby the power supply terminal of the IC chip is shunted by the capacitor, and the plurality of terminals of the IC chip displaced from the surface of the capacitor are connected to other parts of the conductor portion. an integrated circuit device consisting of additional conductors connected to the
JP56117561A 1981-01-12 1981-07-27 Integrated circuit device Granted JPS57126157A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22412781A 1981-01-12 1981-01-12

Publications (2)

Publication Number Publication Date
JPS57126157A JPS57126157A (en) 1982-08-05
JPS6316906B2 true JPS6316906B2 (en) 1988-04-11

Family

ID=22839370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56117561A Granted JPS57126157A (en) 1981-01-12 1981-07-27 Integrated circuit device

Country Status (5)

Country Link
JP (1) JPS57126157A (en)
CA (1) CA1156771A (en)
DE (1) DE3130072A1 (en)
FR (1) FR2499768B1 (en)
GB (1) GB2091035B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5954249A (en) * 1982-09-22 1984-03-29 Fujitsu Ltd Semiconductor device
JPS5966157A (en) * 1982-10-08 1984-04-14 Fujitsu Ltd Semiconductor device and manufacture thereof
FR2550009B1 (en) * 1983-07-29 1986-01-24 Inf Milit Spatiale Aeronaut ELECTRONIC COMPONENT HOUSING PROVIDED WITH A CAPACITOR
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JPH0828447B2 (en) * 1983-10-05 1996-03-21 富士通株式会社 Method for manufacturing semiconductor device
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Also Published As

Publication number Publication date
GB2091035A (en) 1982-07-21
DE3130072A1 (en) 1982-08-05
FR2499768B1 (en) 1985-12-20
JPS57126157A (en) 1982-08-05
GB2091035B (en) 1985-01-09
CA1156771A (en) 1983-11-08
FR2499768A1 (en) 1982-08-13

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