JPS6316737A - Time division device for packet signal - Google Patents

Abstract

PURPOSE:To reduce a required transmission capacity, and to use a surplus transmission capacity for another use, by providing a packet dividing and integrating unit, an additional information signal generator, and a synthesizer, and outputting the output of the synthesizer to a time divisional multiplexing device. CONSTITUTION:The packet signal dividing and integrating unit 7 consists of a packet signal detector 1 which detects the presence/absence of a packet signal, a packet signal length detector 2 which measures the signal length of the packet signal, a storage circuit 4, and a read signal generator 3. The packet signal dividing and integrating unit 7 divides or integrates the packet signal in a constant length less than a time slot, and generates a partial packet. The additional information signal generator 5 outputs a bit of additional information which represents relation in the division or the integration of the partial packets, for example, the bit of additional information such as a bit of data completion information which connects the packet to a preceding packet, or a bit of data length information. The synthesizer 6 synthesizes the partial packet outputted from the storage circuit 4, with an additional information signal outputted from the additional information signal generator 5, and outputs it to a time divisional multiplexing device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal converting device for sending packet signals to a time division multiplexing device used for wireless communications, and particularly to a packet signal time division device.

[Conventional technology]

Traditionally, packet signals have been used for time division multiple access (TDMA) in wireless communications.
(Time Division Multiple A
A method of transmitting data using [ccess )] has been considered. A packet signal is a small signal,
While there is no packet signal, a certain pattern called a flag is always sent. A conventional time division multiplexing device (TDMA device) performs time division multiplexing by regarding a signal including this flag as a type of continuous signal.

[Problem that the invention seeks to solve]

In the conventional technology, the entire data (even the meaningless and wasteful flag) is sent along with the actual data, so there is a problem that the transmission efficiency is poor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a packet signal time division device that can reduce the required transmission capacity by removing the flag and transmitting the signal, and can use the remaining transmission capacity for other purposes. It is in.

[Means for solving problems]

The present invention provides a packet signal time division device provided upstream of a time division multiplex device that time division multiplex transmits packet signals of undefined length and random arrival times in a plurality of predetermined periodic time slots. a packet divider/integrator that divides or integrates the packet signal into a fixed length that does not exceed a time slot to create partial packets; an additional information signal generator that outputs an additional information signal indicating the division/integration relationship of the partial packets; ; a combiner for combining the partial packet and the corresponding additional information signal; and the output of the combiner is output to the time division multiplexing device.

[Operation] According to the present invention, the flag is removed and only the packet signal is stored in the storage circuit in a continuous state, and the stored packet signal is divided into fixed lengths that do not exceed the time slot of the time division multiplexer. - Integrate to form partial packets. On the other hand, an additional information signal indicating the division/integration relationship of each partial packet is formed. Then, the partial packet and the additional information signal are combined to form a signal to be input to the time division multiplexer.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention. This packet signal time division device is provided upstream of a time division multiplex device (time division multiplex transmitter) that performs time division multiplex transmission in a plurality of predetermined periodic time slots. The packet signal divider/integrator 7 includes a packet signal detector 1 that detects the beginning of a packet signal, that is, detects the presence or absence of a packet signal, a packet signal length detector 2 that measures the signal length of the packet signal, and a storage circuit. 4 and a read signal generator 3. This packet signal divider/integrator 7 divides or integrates the packet signal into a fixed length that does not exceed the time slot to create partial packets.

The additional information signal generator 5 outputs additional information indicating the division/integration relationship of partial packets, such as the end of data to be connected to the previous packet, data length, etc.

The synthesizer 6 synthesizes the partial packet output from the storage circuit 4 and the additional information signal output from the additional information signal generator 5, and outputs the combined signal to the time division multiplexer.

Next, the operation of this embodiment will be explained with reference to the signal timing chart of FIG.

The signal a inputted from the terminal 11 includes packet signals 100, 101, and 102 each having an individual length, and the spaces between the packet signals are usually filled with a specific pattern of flags (F in the figure) 600. This signal a is transmitted to the packet signal detector 1
and is input to the memory circuit 4. The packet signal detector 1 identifies the presence or absence of a packet signal by detecting the beginning of the packet signal, and outputs a signal as the identification result. This signal is input on the one hand to the storage circuit 4 as a write signal, and on the other hand to the packet signal length detector 2 for measuring the packet signal length. In the storage circuit 4, since the signal a is stored by the write signal, the flag 600 is removed and the packet signals 100, 101, 102
only is stored. The state of the signal in the memory circuit 4 is the second
As shown in Figure C, each packet signal 100, 101.10
2 are in close contact with each other with the flag F removed. The packet signal length detector 2 measures the signal length of each packet signal 100, 101, 102 from the signal source, and the information is sent to the read signal generator 3.

The readout signal generator 3 further receives a time-division multiplexed frame signal f and a slot gate signal d used as slot allocation information (a signal is sent while on) from terminals 12 and 13, respectively, and outputs the signal to the storage circuit 4. The readout signal g is output as an additional information output signal to the additional information signal generator 5.

The read signal g has the time slot length of time division multiplexing and all (unrelated packet signals 100, 101, 102,
The partial packet signal i is divided and integrated to match the time slot of time division multiplexing, that is, by a constant length not exceeding the time slot, and outputted from the storage circuit 4 to a predetermined position.

In the example of FIG. 2, the packet signal 100 includes the signals 400,
The signal 402 is further divided into a signal 403, which is a part of the packet signal 101, to have a constant length.

On the other hand, the additional information output signal is generated by the additional information signal generator 5 in order to insert into the slot the information necessary for reproducing the partial packet signal i into a packet signal on the receiving side.
generates an additional information signal j. In FIG. 2, additional information corresponding to each partial packet is indicated by 500, 501, and 502.

These partial packet signal i and additional information signal j are combined by a combiner 6 and sent out from a terminal 14 to a time division multiplexer as an assigned slot signal e.

〔Effect of the invention〕

The present invention has the following two effects. First, it removes flags that can be considered wasteful, improving transmission efficiency, and second, since additional information is inserted into the slot signal, it can also be applied to conventional TDMA equipment (time division multiplexing equipment). It is possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment of FIG. 1...Packet signal detector 2...Packet signal length detector 3...Read signal generator 4...Storage circuit 5...Additional information signal generator 6...Synthesizer

Claims (1)

[Claims] (1) In a packet signal time division device provided upstream of a time division multiplex device that time division multiplex transmits packet signals of undefined length and random arrival times in a plurality of predetermined periodic time slots, A packet division/integration device that divides or integrates a packet signal into a fixed length that does not exceed a time slot to create partial packets; An additional information signal generator that outputs an additional information signal indicating the relationship between division and integration of the partial packets; A packet signal time division device comprising: a combiner for combining the partial packet and the corresponding additional information signal, and outputting an output of the combiner to the time division multiplexing device.