JPS63164270A - Laminated type solid-state image sensing device - Google Patents
Laminated type solid-state image sensing deviceInfo
- Publication number
- JPS63164270A JPS63164270A JP61308282A JP30828286A JPS63164270A JP S63164270 A JPS63164270 A JP S63164270A JP 61308282 A JP61308282 A JP 61308282A JP 30828286 A JP30828286 A JP 30828286A JP S63164270 A JPS63164270 A JP S63164270A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- pixel
- dummy electrode
- picture element
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 4
- 238000003384 imaging method Methods 0.000 claims description 26
- 238000006243 chemical reaction Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims 1
- 230000005693 optoelectronics Effects 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 206010034972 Photosensitivity reaction Diseases 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000036211 photosensitivity Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- 241000269821 Scombridae Species 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 235000019688 fish Nutrition 0.000 description 1
- 230000001965 increasing effect Effects 0.000 description 1
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- 235000020640 mackerel Nutrition 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14665—Imagers using a photoconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は，固体撮像素子チップに光導体膜を積層して構
成される積層型固体撮像装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a stacked solid-state imaging device configured by stacking a photoconductor film on a solid-state imaging element chip.
（従来の技術）
固体撮像素子チップに光導電体膜を積層した２階建て構
造の固体撮像装置は，感光部の開口面積を広くすること
ができるため，高感度且つ低スミアという優れた特性を
有する。このためこの固体撮像装置は各種監視用ＴＶや
高品位ＴＶなどのカメラとして有望視されている。この
種の固体撮像装置の光電変換部は画素電極の配列の上に
光導電体膜を積層し，その上全面に透光性のある材料に
より透明電極を形成するという構造となっている。(Prior technology) A solid-state imaging device with a two-story structure in which a photoconductor film is laminated on a solid-state imaging device chip has excellent characteristics of high sensitivity and low smear because the aperture area of the photosensitive section can be widened. have For this reason, this solid-state imaging device is seen as promising as a camera for various surveillance TVs, high-definition TVs, and the like. The photoelectric conversion section of this type of solid-state imaging device has a structure in which a photoconductor film is laminated on an array of pixel electrodes, and a transparent electrode made of a light-transmitting material is formed on the entire surface thereof.
したがって各画素の感光部の領域を決定しているのは画
素電極の面積である。ところが透明電極と光導電体膜は
画素電極の配列をおおう様に全面に形成されているため
，画素電極の配列の外側に入射した光によって生成され
た電荷担体の一部が。Therefore, it is the area of the pixel electrode that determines the area of the photosensitive portion of each pixel. However, since the transparent electrode and photoconductor film are formed over the entire surface of the pixel electrode array, some of the charge carriers generated by the light incident on the outside of the pixel electrode array.
端部の画素電極上部より外側に広がっている光導電体膜
中の電界によって走向し端部の画素電極に流れ込む。従
って画素の配列の端部の画素の感光部の領域は他の部分
の画素に比べて実質的に太きくなる。これは画像で考え
ると画像の端部が明るくなってしまう。また特に入射光
の照度の大きな場合には画素電極の配列の外側に発生し
た多量の電荷担体が画素配列の端部の数画素の画素電極
に流れ込む事によりブルーミングを生じる。従って画素
配列の端部の数画素からの出力信号を映像信号として用
いる事が出来ない。The electric field in the photoconductor film that spreads outward from the upper part of the pixel electrode at the end causes it to strike and flow into the pixel electrode at the end. Therefore, the area of the photosensitive area of the pixel at the end of the pixel array becomes substantially thicker than the area of the pixel at the other portion. Thinking about this in terms of an image, the edges of the image become brighter. In addition, especially when the illuminance of the incident light is high, a large amount of charge carriers generated outside the pixel electrode array flow into the pixel electrodes of several pixels at the ends of the pixel array, causing blooming. Therefore, output signals from several pixels at the ends of the pixel array cannot be used as video signals.
（発明が解決しようとする問題点）
以上述べてきたように従来の積層型固体撮像装置では、
画素配列の外側で発生した電荷担体が画素配列の端部に
流れ込むために画素配列の端部の数画素からの出力信号
を映像信号として用いる事ができないという欠点があっ
た。本発明は、上記の点に鑑み、端部の画素からの出力
信号を有効に映像信号として利用する積層型固体撮像装
置を提供する事を目的とする。(Problems to be solved by the invention) As mentioned above, in the conventional stacked solid-state imaging device,
There has been a drawback that the output signals from several pixels at the ends of the pixel array cannot be used as video signals because charge carriers generated outside the pixel array flow into the ends of the pixel array. In view of the above points, it is an object of the present invention to provide a stacked solid-state imaging device that effectively utilizes output signals from pixels at the edges as video signals.
〔発明の構成〕
（問題点を解決するための手段）
本発明による積層型固体撮像装置は撮像素子チップ上の
画素配列の端部の画素の画素電極に隣接してダミー電極
を形成した事を特徴とする。このダミー電極には直接あ
るいは半導体基板に形成されたドレイン部を通して、一
定の電圧が印加される。[Structure of the Invention] (Means for Solving the Problems) The stacked solid-state imaging device according to the present invention is characterized in that a dummy electrode is formed adjacent to the pixel electrode of the pixel at the end of the pixel array on the imaging element chip. Features. A constant voltage is applied to this dummy electrode directly or through a drain portion formed on the semiconductor substrate.
（作用）
積層型固体撮像装置ではｊＩＩＴ素電極の配列上を光導
電膜及び透明電極が画素電極をおおっているために１画
素配列の端部の画素の感光部領域が他の部分の画素に比
べて大きくなる。この端部の画素の画素電極に降接して
ダミー電極を形成し、このダミー電極に画素電極に印加
される電圧と同程度の電圧を印加する事で、この端部の
画素の感光部領域が実質的に大きくなる効果を消失させ
る事ができる。すなわちダミー電極がない場合には画素
配列の外側に入射した光が吸収されて、生成した電荷担
体の一部が画素配列の端部の画素の画素電極に流れ込む
がダミー電極を形成してダミー電極と透明電極間に適当
な電圧を印加する事で、この画素配列の外側に生成した
電荷担体をダミー電極に流し込み、画素電極に流れ込む
事を防ぐ事ができる。従って、端部の画素電極に余計な
電荷担体が流れ込む事がなくなるために端部の画素でも
他の部分の画素と同じ一定の光感度が得られる。(Function) In a stacked solid-state imaging device, since a photoconductive film and a transparent electrode cover the pixel electrodes on the array of jIIT element electrodes, the photosensitive region of the pixel at the end of one pixel array is exposed to the pixels of other parts. becomes larger in comparison. A dummy electrode is formed by descending to the pixel electrode of the pixel at this end, and by applying a voltage comparable to the voltage applied to the pixel electrode to this dummy electrode, the photosensitive area of the pixel at this end is It is possible to substantially eliminate the increasing effect. In other words, if there is no dummy electrode, light incident on the outside of the pixel array will be absorbed, and some of the generated charge carriers will flow into the pixel electrode of the pixel at the end of the pixel array, forming a dummy electrode. By applying an appropriate voltage between the pixel array and the transparent electrode, charge carriers generated outside the pixel array can be flowed into the dummy electrode and prevented from flowing into the pixel electrode. Therefore, unnecessary charge carriers do not flow into the pixel electrodes at the ends, so that the pixels at the ends can have the same constant photosensitivity as the pixels at other parts.
また画素配列の端部でのブルーミングも抑制できる。Blooming at the ends of the pixel array can also be suppressed.
（実施例）
以下１本発明の実施例を図面を参照して詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は一実施例による積層型固体撮像装置の画素配列
の端部の２画素を含む部分の断面構造である。ｐ型Ｓ１
基板１１にｐウェル１２が形成されたウェーハを用いて
、インターライン転送型ＣＣＤ撮像素子チップｌが構成
されている。即ち信号電荷を蓄積する蓄積ダイオード１
３がマトリクス状に形成され、蓄積ダイオード１３の列
に隣接してｎ型の埋め込みチャンネルＣＣＤからなる垂
直ＣＣＤ １４が形成されている。１５はチャンネルス
トッパとしてのｐ型ノ惜であり、これにより分離されて
同様の構成の蓄積ダイオード列と垂直ＣＣＤの組が繰り
返し配列形成される。１６ｔ、１６會は垂直ＣＣＤ１４
の転送ゲート電極であり、その一部は蓄積ダイオード１
３からＣＯＤチャンネルへの電荷転送ゲート電極を兼ね
ている。転送ゲート電極１６．．１６．が形成された基
板上は層間絶縁膜１８ｓ、１８１に覆われ、且つ蓄積ダ
イオード１３に接続される多結晶シリコン電極１フが形
成されて、平担化されている。第１の眉間絶縁膜１８．
は例えばＣＶＤ法により形成されるＳｉｎ、膜であり、
第２の眉間絶縁膜１８鵞は例えばプラズマＣＶＤ法によ
り形成されるＢＰＳＧ膜である。この構造は、＠ｌの層
間絶縁膜１８１に開口形成後、多結晶シリコン膜電極１
７を各蓄積ダイオード１３上に形成した後、ＢＰＳＧ膜
１Ｂ雪を被着してこれを溶融し１反応性イオンエツチン
グ法でＢ Ｐ ８ Ｇ膜をエツチングして多結晶シリコ
ン電極１７の表面を露出させることで得られる。FIG. 1 is a cross-sectional structure of a portion including two pixels at the end of a pixel array of a stacked solid-state imaging device according to an embodiment. p-type S1
An interline transfer type CCD image sensor chip l is constructed using a wafer in which a p-well 12 is formed on a substrate 11. That is, a storage diode 1 that stores signal charges.
3 are formed in a matrix, and a vertical CCD 14 consisting of an n-type buried channel CCD is formed adjacent to a column of storage diodes 13. Reference numeral 15 denotes a p-type capacitor serving as a channel stopper, which separates the storage diode array and vertical CCD to form a repeating array. 16t, 16th is vertical CCD14
transfer gate electrode, part of which is the storage diode 1
It also serves as a charge transfer gate electrode from No. 3 to the COD channel. Transfer gate electrode 16. ．． 16. The substrate on which is formed is covered with interlayer insulating films 18s and 181, and a polycrystalline silicon electrode 1f connected to the storage diode 13 is formed and flattened. First glabellar insulating film 18.
is, for example, a Sin film formed by the CVD method,
The second glabellar insulating film 18 is, for example, a BPSG film formed by plasma CVD. In this structure, after forming an opening in the interlayer insulating film 181 of @l, the polycrystalline silicon film electrode 1
7 is formed on each storage diode 13, a BPSG film 1B is deposited and melted, and the BP8G film is etched using a reactive ion etching method to expose the surface of the polycrystalline silicon electrode 17. It can be obtained by letting
このように表面が平担化されたＣＣＤ撮像素子チップ１
上に各多結晶シリコン電極１７に接続される画素電極１
９とダミー電極２０が形成されている。ダミー電極は端
部の画素電極１９に隣接して、垂直方向に垂直ＣＣＤ１
４と平行して伸びている。画素電極１９とダミー電極２
０はスパッター法によりＣｒをｘｏｏｏｕ程度被着し１
反応性イオンエツチング法によりエツチングして所定の
形状に形成される。ダミー電極２０と端部の画素電極１
９の距離ａは各画素電極１９の間の距離すが等しくなる
ように形成されている。CCD image sensor chip 1 whose surface is flattened in this way
A pixel electrode 1 connected to each polycrystalline silicon electrode 17 on the top
9 and a dummy electrode 20 are formed. The dummy electrode is adjacent to the pixel electrode 19 at the end and extends vertically to the vertical CCD 1.
It extends parallel to 4. Pixel electrode 19 and dummy electrode 2
0 is coated with xooou Cr by sputtering method and 1
It is etched into a predetermined shape using a reactive ion etching method. Dummy electrode 20 and end pixel electrode 1
The distance a of 9 is formed so that the distance between each pixel electrode 19 is equal.
こうして画素電極１９及びダミー電極２０が形成された
チップ基板上に光導電体膜２が積層形成されている。光
導電体Ｍ２は、正孔注入阻止層としてのｉ型のａ−８ｉ
Ｃ：Ｈ（水素化アモルファスシリコン・カーバイド）１
９２１．主として光電変換が行なわれる高抵抗のａ−８
ｉ：Ｈ膜２２．および電子注入阻止層となるｐ型層−８
ｉＣ：Ｈ膜２３の３層構造からなる。これらの膜は８ｉ
Ｈ４ガスを主成分とするガスのグロー放電分解法により
形成される。ａ−８ｉＣ：Ｈ膜２１は室温での暗導電率
σ。〜１０１４（ｒｋＰＩＭ）−” テ厚サバ１００
Ａ程ｇ トスル。A photoconductor film 2 is laminated on the chip substrate on which the pixel electrodes 19 and dummy electrodes 20 are formed. The photoconductor M2 has an i-type a-8i as a hole injection blocking layer.
C:H (hydrogenated amorphous silicon carbide) 1
921. High resistance A-8 where photoelectric conversion is mainly performed
i:H film 22. and p-type layer-8 which becomes an electron injection blocking layer.
It consists of a three-layer structure of an iC:H film 23. These membranes are 8i
It is formed by a glow discharge decomposition method of gas whose main component is H4 gas. The a-8iC:H film 21 has a dark conductivity σ at room temperature. ~1014(rkPIM)-” Te Atsushi Mackerel 100
A degree g tossuru.
高抵抗ａ−８ｉ：Ｈ膜２２は６〜ＩＱ （Ｑｃｙ＋ｓ
） ’？’光電変換に必要な十分な厚さとする。可視
光に十分な光感度を持つためには０．５μｍ以上の膜厚
が必要である。ｐ型層−８ｉＣ：Ｈ膜２３は約２００Ｘ
程度とする。この様に形成された光導電体膜２上に透明
電極２４が例えばＩ ＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ ０
ｘｉｄｅ）により形成されている。ａｔ図には示してい
ないがダミー電極２０上の光導電体膜２及び透明電極２
４の一部がエツチングにより除去されダミー電極露出部
を通して外部よりダミー電極２０に所望の電圧が印加さ
れる。High resistance a-8i: H film 22 is 6~IQ (Qcy+s
) '? 'The thickness should be sufficient for photoelectric conversion. In order to have sufficient photosensitivity to visible light, a film thickness of 0.5 μm or more is required. The p-type layer-8iC:H film 23 is approximately 200X
degree. A transparent electrode 24 is formed of, for example, ITO (Indium Tin 0) on the photoconductor film 2 formed in this manner.
xide). Although not shown in the at figure, the photoconductor film 2 and transparent electrode 2 on the dummy electrode 20
4 is removed by etching, and a desired voltage is applied to the dummy electrode 20 from the outside through the exposed portion of the dummy electrode.
この実施例の撮像装置の光感度の測定を行った。The photosensitivity of the imaging device of this example was measured.
ＣＣＤ撮像素子チップは２０万画素、２／３吋サイズの
ものである。撮像装置の受光面の照度が１．５ルクスと
なるように白色光を入射した。光導電体ｇ２で光電変換
され蓄積ダイオード１３に蓄積された電荷担体は転送グ
ー）１６．に印加される読み出しパルス電圧によって垂
直ＣＣＤ１４に移される。従って蓄積ダイオード１３と
電気的につながっている画素電極１９の電位は転送ゲー
ト１６．に印加される読み出しパルス電圧の電位に等し
くなる。この読み出しパルスを＋５ｖに、透明電極２４
をグランドにショートして測定した。従って画素電極２
０と透明電極２４の間に印加された電圧は５Ｖである。The CCD image sensor chip has 200,000 pixels and is 2/3 inch in size. White light was applied so that the illuminance on the light receiving surface of the imaging device was 1.5 lux. The charge carriers photoelectrically converted by the photoconductor g2 and stored in the storage diode 13 are transferred (Goo)16. is transferred to the vertical CCD 14 by a read pulse voltage applied to the vertical CCD 14. Therefore, the potential of the pixel electrode 19 electrically connected to the storage diode 13 is the same as that of the transfer gate 16. is equal to the potential of the read pulse voltage applied to. This readout pulse is set to +5V, and the transparent electrode 24
Measured by shorting to ground. Therefore, pixel electrode 2
The voltage applied between 0 and the transparent electrode 24 is 5V.
次表にダミー電極２０に画素電極１９と等しい５■の電
圧を加えた場合の光感度の測定の結果を次表に示す。結
果は端部の画素からの出力電圧ｖ１を端部から１０画素
めの画素の信号電圧ｖ茸で割り算して示した。The following table shows the results of measuring photosensitivity when a voltage of 5 cm, which is equal to that of the pixel electrode 19, is applied to the dummy electrode 20. The results are shown by dividing the output voltage v1 from the pixel at the edge by the signal voltage v of the 10th pixel from the edge.
またダミー電極のない従来の積層型固体撮像装置の場合
の結果を参考のためあわせて示した。この積層型固体撮
像装置はダミー電極を形成していない魚身外は実施例と
まったく同じ構造の積層型固体撮像装置である。ダミー
電極のない従来例では端部の画素の信号電圧が他の画素
に比べて大きくなっている事がわかる。これは端部の画
素電極１９の外側の領域Ａに入射して生成した電子が端
部の隣接する画素電極１９に流れ込むためである。In addition, results for a conventional stacked solid-state imaging device without dummy electrodes are also shown for reference. This stacked solid-state imaging device is a stacked solid-state imaging device having exactly the same structure as the embodiment except for the fish body in which no dummy electrodes are formed. It can be seen that in the conventional example without dummy electrodes, the signal voltage of the pixels at the edge is larger than that of the other pixels. This is because electrons generated upon entering the area A outside the pixel electrode 19 at the end flow into the adjacent pixel electrode 19 at the end.
ダミー電極を設けた実施例の場合ではダミー電極２０と
透明電極２４の間にある垂直方向の電界によって領域Ａ
で生成した電子がダミー電極２０に流れ込み、余計な電
子が端部の画素電極１９に流れ込む事が防がれる。従っ
て端部の画素の出力信号電圧が他の部分の画素と等しく
なる事がわかる。In the case of the embodiment in which a dummy electrode is provided, the area A is
The generated electrons flow into the dummy electrode 20, and unnecessary electrons are prevented from flowing into the pixel electrode 19 at the end. Therefore, it can be seen that the output signal voltage of the pixels at the end is equal to that of the pixels at other parts.
また強い光を入射した場合に画素配列の端部でのブルー
ミングが抑制される事を確認した。We also confirmed that blooming at the edges of the pixel array is suppressed when strong light is incident.
以上の結果から明らかなように１画素配列の端部の画素
に隣接したダミー電極を形成した積層型固体撮像装置で
は１画素配列の端部の画素からの出力信号を有効に映像
信号として利用する事ができる。As is clear from the above results, in a stacked solid-state imaging device in which dummy electrodes are formed adjacent to pixels at the ends of a single pixel array, the output signals from the pixels at the ends of a single pixel array are effectively used as video signals. I can do things.
第２図は他の実施例の積層型固体撮像装置である。第１
図と対応する部分には第１図と同一符号を付して詳細な
説明は省略する。第１図と異なる点はＳｉ ウェハのｐ
ウェルにｎ型層のドレイン部２６を形成しこのドレイン
部２６上にダミー電極２０と電気的につながる多結晶シ
リコン電極２５を形成した事である。この実施例ではダ
ミー電極２０の電位をドレイン部２６に印加する電圧に
より第１図と同じく制御するものであり、先の実施例と
同様な効果が得られる。FIG. 2 shows a stacked solid-state imaging device according to another embodiment. 1st
Portions corresponding to those in the figures are given the same reference numerals as in FIG. 1, and detailed explanations will be omitted. The difference from Fig. 1 is that the p of the Si wafer is
A drain part 26 of an n-type layer is formed in the well, and a polycrystalline silicon electrode 25 electrically connected to the dummy electrode 20 is formed on this drain part 26. In this embodiment, the potential of the dummy electrode 20 is controlled by the voltage applied to the drain portion 26 in the same manner as in FIG. 1, and the same effects as in the previous embodiment can be obtained.
なお実施例では、ＣＣＤ撮像素子を用いたが。Note that in the example, a CCD image sensor was used.
ＭＯ８ＩＩやＢＢＤ型撮像素子チップを電荷転送部とし
て用い、これに光導体膜を積層する積層型固体撮像装置
の場合にも１本発明を同様に適用する事ができる。The present invention can be similarly applied to a stacked solid-state imaging device in which an MO8II or BBD type imaging element chip is used as a charge transfer section and a photoconductor film is laminated thereon.
以上述べたように本発明によれば画素配列の端部の画素
の画素電極に隣接してダミー電極を設け。As described above, according to the present invention, a dummy electrode is provided adjacent to the pixel electrode of the pixel at the end of the pixel array.
このダミー電極の電位を制御する事で、端部の画素でも
一様な光感度が得られ、端部の画素の出力信号をも有効
に利用する積層型固体撮像装置が得られる。By controlling the potential of this dummy electrode, uniform photosensitivity can be obtained even in the pixels at the edges, and a stacked solid-state imaging device can be obtained that effectively utilizes the output signals of the pixels at the edges.
第１図は本発明の一実施例の積層型固体撮像装置を示す
図、第２図は他の実施例の積層型固体撮像装置を示す図
である。図において。
１・・・ＣＣＤ撮像素子チップ、２・・・光導電体膜。
１１・・・ｐ型Ｓｔ基板、１２・・・ｐウェル、１３・
・・蓄積ダイオード、１４・・・垂直ＣＣＤ、１５・・
・ｐ型層。
１６１−１６１ ・・・転送グー）、１７・・・ｎｆ
ｉ多結晶シリコン電極、 １８１．１８ｎ・・・層間
絶縁膜、１９・・・画素電極、２０・・・ダミー電極、
２１・・・ｉ型層−８ｉＣ：Ｈａ、２２・ｉ型層−８１
： Ｈｇｉ、 ２３− ｐ型層−８ｉＣ：Ｈ膜、２４・
・・透明電極、２５・・・ｎ型多結晶シリコン電極、２
６・・・ｎｆｉドレイン部、２７・・・入射光、ａ・・
・端部の画素電極１９とダミー電極２０の間の距離、ｂ
・・・各画素電極１９の間の距離、Ａ・・・画素配列の
外側の領域。
代理人 弁理士 則 近 憲 佑
同 竹 花 喜久男
ミ 旭 おFIG. 1 is a diagram showing a stacked solid-state imaging device according to one embodiment of the present invention, and FIG. 2 is a diagram showing a stacked solid-state imaging device according to another embodiment. In fig. 1... CCD image sensor chip, 2... Photoconductor film. 11...p-type St substrate, 12...p well, 13.
...Storage diode, 14...Vertical CCD, 15...
・P-type layer. 161-161 ... transfer goo), 17 ... nf
i polycrystalline silicon electrode, 181.18n... interlayer insulating film, 19... pixel electrode, 20... dummy electrode,
21...i-type layer-8iC:Ha, 22-i-type layer-81
: Hgi, 23- p-type layer-8iC:H film, 24.
...Transparent electrode, 25...N-type polycrystalline silicon electrode, 2
6... nfi drain part, 27... incident light, a...
・Distance between the pixel electrode 19 and the dummy electrode 20 at the end, b
...Distance between each pixel electrode 19, A...A region outside the pixel array. Agent Patent Attorney Nori Chika Ken Yudo Takehana Kikuo Mi Asahi O
Claims (2)
号電荷読み出し部の配列が形成され、最上部に前記信号
電荷蓄積ダイオードと電気的に接続された画素電極の配
列が形成された固体撮像素子チップ上に光電変換部とし
て光導電体膜が積層された固体撮像装置において、前記
画素電極の配列の端部の画素電極に隣接してダミー電極
が形成された事を特徴とする積層型固体撮像装置。(1) A solid-state image sensor chip in which an array of signal charge storage diodes and an array of signal charge readout sections are formed on a semiconductor substrate, and an array of pixel electrodes electrically connected to the signal charge storage diodes is formed on the top. A stacked solid-state imaging device having a photoconductor film stacked thereon as a photoelectric conversion section, characterized in that a dummy electrode is formed adjacent to the pixel electrode at the end of the pixel electrode array. .
形成され、このドレイン部が前記ダミー電極と電気的に
接続された事を特徴とする前記特許請求の範囲第１項記
載の固体撮像装置。(2) The solid-state imaging device according to claim 1, wherein a drain portion made of a diffusion region is formed in the semiconductor substrate, and the drain portion is electrically connected to the dummy electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61308282A JP2509592B2 (en) | 1986-12-26 | 1986-12-26 | Stacked solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61308282A JP2509592B2 (en) | 1986-12-26 | 1986-12-26 | Stacked solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63164270A true JPS63164270A (en) | 1988-07-07 |
| JP2509592B2 JP2509592B2 (en) | 1996-06-19 |
Family
ID=17979155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61308282A Expired - Fee Related JP2509592B2 (en) | 1986-12-26 | 1986-12-26 | Stacked solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2509592B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000138363A (en) * | 1998-11-02 | 2000-05-16 | Hewlett Packard Co <Hp> | Image sensor array |
| JP2007324248A (en) * | 2006-05-31 | 2007-12-13 | Sanyo Electric Co Ltd | Photographic device |
| JP2013085164A (en) * | 2011-10-12 | 2013-05-09 | Panasonic Corp | Solid-state imaging device |
| JP2019135789A (en) * | 2019-04-22 | 2019-08-15 | キヤノン株式会社 | Solid-state imaging sensor and imaging system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387619A (en) * | 1977-01-13 | 1978-08-02 | Toshiba Corp | Solid pickup unit |
| JPS6149569A (en) * | 1984-08-17 | 1986-03-11 | Matsushita Electronics Corp | Solid-state image pickup device |
| JPS61127165A (en) * | 1984-11-24 | 1986-06-14 | Sharp Corp | Semiconductor device |
-
1986
- 1986-12-26 JP JP61308282A patent/JP2509592B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387619A (en) * | 1977-01-13 | 1978-08-02 | Toshiba Corp | Solid pickup unit |
| JPS6149569A (en) * | 1984-08-17 | 1986-03-11 | Matsushita Electronics Corp | Solid-state image pickup device |
| JPS61127165A (en) * | 1984-11-24 | 1986-06-14 | Sharp Corp | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000138363A (en) * | 1998-11-02 | 2000-05-16 | Hewlett Packard Co <Hp> | Image sensor array |
| JP2007324248A (en) * | 2006-05-31 | 2007-12-13 | Sanyo Electric Co Ltd | Photographic device |
| JP2013085164A (en) * | 2011-10-12 | 2013-05-09 | Panasonic Corp | Solid-state imaging device |
| JP2019135789A (en) * | 2019-04-22 | 2019-08-15 | キヤノン株式会社 | Solid-state imaging sensor and imaging system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2509592B2 (en) | 1996-06-19 |
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