JPS63163943A - Control method for writing into memory - Google Patents

Abstract

PURPOSE:To prevent errorneous data from being written into a memory by generating a prescribed write permission code every time before a writing access to the memory, comparing it with a decision code which has been stored, and prohibiting the writing of data if they disagree. CONSTITUTION:The write permission code is outputted from the output port 5 of a CPU1 just before the writing into the memory 3 starts, and a latch circuit 6 is set to hold the output as parallel data through a shift register 4. The code which has been latched and the initial code 8 which has previously been stored are compared in a digital comparator 7. The compared signals 7a are inputted to an AND circuit 9 and an illegal access detection circuit 11, and an address AD from the CPU1 is read in a decoder 10 and area signals beta are outputted to the circuit 9 and the circuit 11. If the signals 7a show disagreement, the circuit 11 outputs an interruption signal INT to the CPU1, and prohibits the writing of data.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a microcomputer system comprising a central processing unit (CPU) and a memory, and particularly relates to a microcomputer system comprising a central processing unit (CPU) and a memory.
+rs j! of data sent from PU to memory. J
The present invention relates to a memory write control method that prevents writing.

(Prior Art) When a CPU or a microprocessor (MPU) constituting a microcomputer system is executing normal processing, when noise occurs in input/output signals due to some external factor, the CPU.

Is there a situation where the MPU goes out of control and executes other programs instead of executing the blocks that should be processed, resulting in important data built in memory being lost or incorrect data being written? be. For this reason, it is customary to take some measure to prevent and protect important data stored in the memory immediately before the runaway from being lost.

For example, a detection means such as a watchdog timer is provided to detect runaway of the MPU, and when these detection means detect runaway, the MPU is reset to prevent such erroneous writing to memory. Alternatively, so-called memory management, ie, the address range for writing is specified by software, and the writing is controlled not to be executed when access is outside the specified address range.

(Problem to be solved by the invention) However, in the former case, it takes some time to reset the MPU after the detection means such as a watchdog timer detects the runaway. In the meantime, MPU or wrong data was written to memory,
The problem was that there was a high risk of losing important data.

In addition, the latter requires at least two or more registers that define the write address range, as well as two or more comparisons that serve as a means of determining whether or not the address is within the specified address range. The problem was that the hardware configuration of the small microcomputer system became complicated, and the circuit itself became large-scale.

This invention was made in order to solve the above problems. Immediately before data is written to the memory of a microcomputer, permission code data is generated to permit data writing, and the permission code data is generated to match a judgment code written in advance. By controlling data writing to memory based on the state, it is possible to prevent incorrect data from being written to memory due to a runaway microcomputer, and
The purpose of the present invention is to provide a memory write control method that allows a microcomputer to detect runaway and self-recovery.

(Means for Solving the Problems) A memory write control method according to the present invention is a code generation process that generates a predetermined write permission code every time a write access to memory is made while a microcomputer is executing a certain program. and a write determination process that compares the write permission code generated by this code generation process with a caulked and stored determination code to determine the authenticity of the data write request to the memory, and the result of this write determination process. , a signal notification process that interrupts and notifies the microcomputer that data writing to the memory is prohibited when the write permission code and the determination code do not match.

Further, a memory write control method according to another aspect of the present invention includes a code generation process of generating a predetermined write permission code immediately before starting each write access to the memory while a microcomputer is executing a certain program; A signal matching process compares and matches the write permission code generated by the code generation process with the preliminarily stored judgment code, and in parallel with this signal matching process, the input address signal is analyzed and the divided memory is The area determination process determines the write area of each specific memory space, and each area of the memory is Write judgment processing that determines the authenticity of a data write request to a specific memory space, and an interrupt notification to the microcomputer that data writing to memory is prohibited based on the result of this write judgment processing, and the program execution of the microcomputer is executed. It consists of a reset process.

(Operation) In the memory write control method of the present invention,
While the microcomputer is executing a certain program, a code generation process is executed to generate a predetermined write permission code immediately before the start of each write access to the memory;
The write permission code generated by this code generation process is compared with the pre-stored judgment code,
The authenticity of permission to write data to the memory is determined, and if the write permission code and the determination code do not match, an interrupt signal for prohibiting data writing to the memory is notified to the microcomputer.

Further, in the memory write control method according to another aspect of the present invention, a code generation process is executed to generate a predetermined write permission code immediately before each write access to the memory is started while the microcomputer is executing a certain program. , the write permission code generated by this code generation process is compared and verified with a pre-stored judgment code, and in parallel with this signal verification process, the input address signal is analyzed and each specific address signal of the divided memory is An area determination process is performed to determine the writing area of the memory space, and each specific memory of the memory is The authenticity of permission to write data into the space is determined, and based on the authenticity, an interrupt is notified to the microcomputer to reset the program execution of the microcomputer.

〔Example〕

FIG. 1 is a block diagram illustrating the hardware configuration of a memory write control method showing an embodiment of the present invention, where l is C
In PU, predetermined write permission code (fixed and not O)
is generated immediately before the start of each write access to the memory 3 and output to the output port 5. Further, the CPU writes the processed data to the memory 3 via the pass line 2, and reads the already written data. CPU
1 is connected to vi via an interface with an external device (not shown).
The computer is connected to the computer and executes a certain program stored in a storage device such as a ROM. 4 is a shift register, output port 5
For example, 8-bit serial data output via the 8-bit serial data is sequentially shifted and 8-bit parallel data is held. A latch circuit 6 reads out the 8-bit parallel data held in the shift register 4 in synchronization with a clock signal input to a clock terminal C.

7 is a digital comparator that compares all bits of the predetermined write permission code latched in the latch circuit 6 and the initial code 8 at once, and when both codes match, a signal 7a of a certain level is latched next. The signal is output to one end of the AND circuit 9 until the signal is reached. Note that the initial code 8 is set in advance to match a predetermined write permission code, and the two codes are configured to match unless an external noise such as noise occurs.

Reference numeral 10 denotes an address area decoder which decodes the address AD output from the CPU l, outputs an area signal β specifying an area of the memory 3 to the other end of the ant circuit 9, and also outputs an area signal β to the illegal access detection circuit 11. Output β. A signal 7a output from the digital comparator 7 is input to the illegal access detection circuit 11,
When the signal 7a is in the LO state, that is, the initial code 8 and the write permission code do not match (noise generation state), the CP
An interrupt signal INT for notifying U1 of this is output to the -13 interrupt port of the CPUI.

Next, the operation will be explained.

When starting each write access to the memory 3 while the CPU 1 is executing a certain program, a write permission code is generated according to a flowchart described later.

The generated serial permission code is output to the shift register 4 via the output port 5, and is then latched into the latch circuit 6 as parallel data. At this time, the digital comparator 7 compares the write fraud code latched in the latch circuit 6 with each hit data of the first or lower bit and the initial code 8 which is the judgment code, and if both code data match, is H to the AND circuit 9.
A signal 7a of I level (write permission) is output. In parallel with this operation, the CPUI uses the address area decoder 10
Since address AD is outputted to address AD, address area decoder 10 outputs area signal β obtained by analyzing address AD to the other end of AND circuit 9, and also outputs area signal β to illegal access detection circuit 11. Therefore, the AND circuit 9 is established and a signal for selecting the memory 3 is output to the chip select 1 to terminal C8 of the memory 3. Next, the write signal output from CPU1! Data is written from the lotus line 2 to a predetermined area of the memory 3 in synchronization with 7WR.

On the other hand, as a result of the comparison by the digital comparator 7, if the two code data do not match, the ant circuit 9 receives the LO
A level (write prohibited) signal 7a is output. Accordingly, from the illegal access detection circuit 11, the CP
An interrupt signal INT notifying U1 of the mismatch of code data is output to the CPUI.

Next, the data write control operation to the memory according to the present invention will be explained with reference to FIG.

FIG. 2 is a flowchart illustrating a memory write control operation procedure showing an embodiment of the present invention. In addition, 5T
(1) to 5T(11) indicate each step.

The CPU determines whether a data write request has been made (step 5T(1)), and if no, executes other processing (step 5T(2)), YES.
If so, a predetermined write permission code is generated (step 5T(3)), and serial write permission code data is transferred from the output port 5 to the shift register 4 (
Step 5T(4)). Next, the transferred serial write permission code data is latched in step 5T.
(5)) Once latched, it is necessary to judge whether the write permission code data latched in the digital comparator 7 or the latch circuit 6 and each bit of the initial code 8 all match, that is, the authenticity of the data write permission. Step 5T (6) ), if YES, CPU
Then, in step 5T (
7) ), send selection command 9a to select memory 3 to memory 3.
(Step 5T)
(8)). Next, predetermined data is written into the memory 3 via the pass line 2 in synchronization with the write signal WR output from the CPUI (step 5T(9)), and the control is ended.

On the other hand, if the determination in step 5T(6) is NO, that is, the illegal access detection circuit 11 determines that the CPU has gone out of control.In step 5T(10)), the CPU 1 is interrupted in order to notify the CPU 1 of this fact. Signal IN
T is output to interrupt the CPU program execution (step 5T(II)), and the control is terminated. Note that steps 5T(6) to 5T(8) may be performed by hardware.

Next, memory write control processing according to another invention will be described with reference to FIGS. 3 to 5.

FIG. 3 is a schematic diagram illustrating the memory space of the memory 3 shown in FIG. 1, where E is a normal data area defined by the area signal γ from the address area decoder 10. E2
is the a-base data area, which is defined by the area signal β from the address area decoder 10. E:l is a user data area defined by an area signal α.

As can be seen from this figure, the memory space of the memory 3 is divided into, for example, three areas, and each area stores data proportional to its importance.

FIG. 4 is a block diagram illustrating the hardware configuration of a memory writing control method illustrating an embodiment of another invention;
Components that are the same as those in FIG. 1 are designated by reference numbers.

In this figure, 21 is a protect switch, and only when this protect switch 21 is turned on, the area signal α is output from the CPU 1, and the write permission code and the initial code 8 match, the user data area E3 of the memory 3 is Data can be written to the state. 2
2 is an AND circuit, which outputs the signal 7 of the digital comparator 7.
When the area signal α and the protect switch 21 are on, a selection command 24a for selecting the memory 3 is output to the chip select terminal C8 of the memory 3 to the OR circuit 24. 23 is an AND circuit which outputs the signal 7a of the digital comparator 7;
By performing AND processing with the area signal α, it is possible to write data into the device data area E2 of the memory 3 and set it in the circuit state.

Next, the operation will be explained.

First, when the address AD output from the CPUI is output to the address area decoder 10, the address AD is analyzed. As a result, when the area signal γ indicating the normal data area E is output, the area signal γ is unconditionally transmitted to the OR circuit 2.
4 to H1 level pulse output is manually inputted to the chip select terminal C8 of the memory 3. Therefore, the memory 3 is selected, and in synchronization with the write signal WR from the CPUI, the data on the pass line 2 is transferred to the normal data area E of the memory 3.
will be written to. In this way, data is always written to the normal data area E1 without any determination of the abnormality of the CPU 1.

On the other hand, if the address AD output from the CPUI is output to the address area decoder IO, and as a result of the analysis of the address AD, the area signal β indicating the device data area E2 is output to the AND circuit 23, the CPU For example, a serial 8-bit write permission code is generated and transferred from the output port 5 to the shift register 4 bit by bit. Shift register 4 is the serial JF that is transferred.
The write permission signal is shifted bit by bit and the parallel write permission code is held, and the write data held in the shift register 4 is synchronized with the clock output when the CPU 1 finishes sending the write permission code. The permission code is latched by the latch circuit 6. When this latch operation is completed, the digital comparator 7 compares the initial code 8 and the write permission code latched in the latch circuit 6 simultaneously in parallel, and if all bits match, the CPU 1
outputs a signal 7a (Hl level) indicating that it is in a non-runaway state to the AND circuit 23, so the AND circuit 23 is established, the OR circuit 24 becomes HI level, and the selection command to select the memory 3 is issued as a chip select. It is input to terminal CS.

Therefore, the memory 3 is selected, and the data on the lotus line 2 (data necessary for the ffi used as the A device) is written into the normal equipment data area E2 of the memory 3 in synchronization with the write signal WR from the CPU 1.

However, if the digital comparator 7 or the initial code 8 and the write permission code latched in the latch circuit 6 are compared and matched, and even 1 bit does not match, it is assumed that the CPU has gone out of control and the data is not written. A signal 7a (LO level) is output to the AND circuit 23 to indicate that this is prohibited. Therefore, even if the address area decoder 10 outputs the area signal β indicating the device data area E2, the AND circuit 23 is not established and the selection command 24a for selecting the memory 3 is not output to the chip select terminal C8, and the pass line The data on the device data area E2 of the memory 3 is prevented from being written to the device data area E2, and alteration of important device data can be prevented. At this time, the address area decoder lO outputs the area signal β to the illegal access detection circuit 11, and the data write is prohibited W.
Since the signal 7a (LO level) indicating that the CPU is running is output, the interrupt signal INT, which notifies the CPU of the runaway state of the CPU, is output to the CPU interrupt port based on the state of both signals, so the program execution is immediately interrupted. Then, a predetermined interrupt process is executed to reinitialize the CPUI, and the CPU self-returns to a normal state.

Furthermore, if the address AD output from the CPUI is output to the address area decoder 10, and as a result of analysis of the address AD, an area signal α indicating the user data area E3 is output to the ant circuit 22, the CPU For example, a serial 8-bit write permission code is generated and transferred from the output port 5 to the shift register 4 bit by bit. The shift register 4 holds the parallel write permission code while shifting the transferred serial write permission signal one bit at a time, and shifts it in synchronization with the clock output from the CPU 1 when it finishes sending the write permission code. The write permission code held in the register 4 is latched by the latch circuit 6. When this latch operation is completed, the digital comparator 7 compares the initial code 8 with the write permission code latched in the latch circuit 6, and if all bits match, outputs an output signal indicating that the CPU 1 is in a non-runaway state. a (HI level) is output to the AND circuit 23, and the protect switch 21
Only when a HI level potential indicating an ON state is output to the AND circuit 22 (the CPU is in a normal state), the AND circuit 22 is established, the OR circuit 24 becomes HI level, and a selection command is issued to select the memory 3. 24a is input to the chip select terminal C8. Therefore, the memory 3 is selected, and the data on the lotus line 2 (the most important data used by the user) is written into the user data area E3 of the memory 3 in synchronization with the write signal WR from the CPUI.

However, if the lag permission code latched in the digital comparator 7 or the initial code 8 and the Sochi circuit 6 is compared and matched, and even the L bit does not match, it is assumed that the CPU 1 has gone out of control. , outputs a signal 7a (LO level) to the AND circuit 22 indicating that writing of data is prohibited. Therefore, even if the area signal α indicating the user data area E3 is output from the address area decoder lO, the AND circuit 22 is not established, and the selection command 24a for selecting the memory 3 is not output to the chip select terminal C8. , the digital comparator 7 or the initial code 8 and the write permission code latched in the latch circuit 6 are compared and verified, and even if all bits match, if the protect switch 21 is in the off state, the AND circuit 22 is not established, and the selection command 24a for selecting the memory 3 is not output to the chip select terminal C8.

Therefore, data on the lotus line 2 is prevented from being written to the user data area E3 of the memory 3, thereby preventing unnecessary alterations to the device data. At this time, the address area decoder 10 outputs the area signal α to the illegal access detection circuit 11, and also outputs a signal 7a (LO level) indicating that data loading is prohibited. CPU1 to CPU1 based on the signal status of both
The interrupt signal INT that notifies the runaway state of the CPU l
Therefore, the program execution is immediately interrupted, a predetermined interrupt process is executed to reinitialize the CPU 1, and the CPU 1 is returned to the normal state by itself.

In the above embodiment, the CPUI receives the interrupt signal INT from the illegal access detection circuit 11 to the interrupt port.
We have described the case where error recovery processing is executed to prevent runaway of the CPU 1 when the CPU 1 is input. If the error recovery processing is controlled to be executed only when the ant condition with the interrupt signal INT is satisfied,
Reliability can be significantly improved.

Next, a memory access control operation according to another invention will be described with reference to the flowchart shown in FIG.

FIG. 5 is a flowchart illustrating a memory write control operation procedure showing another embodiment of the invention. In addition, 5T
(1) to 5T(18) indicate each step.

First, the address area decoder IO analyzes the address AD output from the CPUI (step 5T(1)).
, to determine whether the area signal output as a result of the analysis is the area signal α (Step 5T(2)); If NO, further determine whether the area signal output as the result of the analysis is the area signal β (Step 5T) (3)), if NO, the area signal output as a result of further analysis is recognized as the area signal γ (step 5T (4)), and a selection command 24a for selecting the memory 3 is output to the chip select terminal C8 (step 5T). (S) ). Next, in synchronization with the write signal WR output from the CPUI, the write data on the pass line 2 is written into the normal data area E1 of the memory 3 (step 5T(6)), and the memory access is ended.

On the other hand, if the judgment in step 5T(3) is YES,
The digital comparator 7 compares the initial code 8 and the write permission code latched in the latch circuit 6, and determines whether all bits match. Step 5T (7)
)), if No, proceed to step 5T(lO) and onward; if YES, select memory 3. Selection command 24a
is output to the chip select terminal C8 (step 5T (
8) ). Next, the write data on the pass line 2 is written into the device data area E2 of the memory 3 in synchronization with the write signal WR output from the CPUI (step 5).
T(9)), terminates the memory access.

- If the judgment in step 5T (7) is NO,
Step 5T(to)) waits until the area signal β reaches the Hl level and the signal 7a of the digital comparator 7 becomes the LO level (step 5T(to)). Then, the area signal β reaches the IIl level and the output of the digital comparator Tough reaches the LO level. At this point, output the interrupt signal INT to the interrupt port of CPU 1 (Step 5T (If)), CPU
1 program execution is interrupted (step 5T (12
)), reinitialize the CPU in step 5T (
13)), restart the program (step 5T)
(14)).

On the other hand, if the judgment in step 5T(2) is YES,
Compare and check the digital comparator 7 or the initial code 8 and the write to the latch circuit 6; 5I permission code to determine whether all bits match (step 5T (Is)); if no, step 5T (10)
Returning to step 5T (15), if YES, it is further determined whether the protect switch 21 is in the on state.
, If No, return to step 5T (10).

If YES, a selection command 24a for selecting memory 3 is output to the chip select terminal C8 (step 5T (17)
). Next, the write signal WR output from the CPUI
The write data on the pass line 2 is written to the user data area E:I of the memory 3 in synchronization with the
(18)) Ends the memory access.

〔Effect of the invention〕

According to the present invention, while a microcomputer is executing a certain program, a predetermined write permission ti(
a code generation process that generates a code; a write determination process that compares the write permission code generated by the code generation process with a pre-stored determination code to determine the authenticity of the data write request to the memory;
As a result of this write judgment process, if the write permission code and the judgment code do not match, the process includes a signal notification process that interrupts the microcomputer to prohibit data writing to the memory. When starting to write data to a specific space above,
After checking whether the data write is valid or not, the CPU writes the original data, which causes the CPU to run out of control, causing incorrect data to be written to the memory until the runaway is detected. This can be prevented in advance, and alteration of data on memory can be prevented.

Further, according to another invention, a code generation process that generates a predetermined write permission tTf code immediately before the start of 6 write access to memory while a microcomputer is executing a certain program, and a code generation process that generates a predetermined write permission tTf code by this code generation process A signal matching process that compares and matches the write permission code with a pre-stored judgment code, and in parallel with this signal matching process, the input address signal is analyzed and each specific memory space of the divided memory is written. Data is transferred to each specific memory space of the memory while referring to the area determination process that determines the area, the area address signal obtained by this area determination process, the collation status signal obtained by the signal comparison process, and the protection switch setting status signal. A write determination process for determining the authenticity of a write request, and an interrupt notification to the microcomputer to prohibit data writing in the memory \ based on the result of this write determination process;
Since it consists of a reset process that resets the program execution of the microcomputer, the authenticity of the data read permission is judged for each specific area according to the importance of the data written on the memory, and the CPU This will prevent data modification in a specific area due to incorrect data writing due to runaway, and will strictly control the destruction of highly important data stored in memory. For example, if a series of important data is stored in a fixed address space of memory This makes it possible to make the computer resident permanently, and has excellent effects such as greatly simplifying the hardware configuration and read control.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the heart structure of a memory write control method according to an embodiment of the present invention, and FIG. 2 is a flowchart illustrating a memory write control operation procedure according to an embodiment of the present invention. 3 is a schematic diagram illustrating the memory space of the memory shown in FIG. 1, FIG. 4 is a block diagram illustrating the hardware configuration of a memory write control method illustrating an embodiment of another invention, and FIG. 7 is a flowchart illustrating a memory write control operation f-order showing another embodiment of the invention. In the figure, l is a CPU, 2 is a pass line, 3 is a memory, 4 is a shift l-register, 6 is a latch circuit, 7 is a digital comparator, IO is an address area decoder, 11 is an illegal access detection circuit, 9.22. 23 is an AND circuit, and 21 is a protect switch. (2 others) Figure 2 Figure 3

Claims (2)

[Claims] (1) In a microcomputer system in which a microcomputer executes a certain program while accessing memory, the microcomputer executes a predetermined write permission code every time it accesses the memory for writing while executing the certain program. a code generation process to generate a code; a write determination process to compare and match the write permission code generated by the code generation process with a pre-stored determination code to determine the authenticity of the data write request to the memory; Memory write control comprising a signal notification process for interrupting and notifying the microcomputer that data writing to the memory is prohibited when the write permission code and the judgment code do not match as a result of the write judgment process. Method. (2) It has a protect switch that divides the memory into multiple areas and allows access only to a predetermined divided memory space, and a specific program or data is stored in the memory space specified according to the state of this protect switch. in a microcomputer system that stores a program and executes a certain program, a code generation process that generates a predetermined write permission code immediately before starting each write access to memory while the microcomputer is executing a certain program; A signal matching process compares and matches the write permission code generated by this code generation process with a pre-stored judgment code, and in parallel with this signal matching process, an input address signal is analyzed and the memory is divided. while referring to the area determination process for determining the write area of each specific memory space, the area address signal obtained by this area determination process, the collation status signal obtained from the signal collation process, and the setting status signal of the protect switch. Write determination processing for determining the authenticity of a data write request to each specific memory space of the memory, and interrupt notification to the microcomputer to prohibit data writing to the memory based on the result of the write determination processing; A memory write control method comprising a reset process for resetting program execution of the microcomputer.