JPS63163100U - - Google Patents
Info
- Publication number
- JPS63163100U JPS63163100U JP5582687U JP5582687U JPS63163100U JP S63163100 U JPS63163100 U JP S63163100U JP 5582687 U JP5582687 U JP 5582687U JP 5582687 U JP5582687 U JP 5582687U JP S63163100 U JPS63163100 U JP S63163100U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- audio signal
- prefader
- terminal
- fader
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005236 sound signal Effects 0.000 claims 13
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Fittings On The Vehicle Exterior For Carrying Loads, And Devices For Holding Or Mounting Articles (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
第１図乃至第３図はこの考案に係るフエーダ回
路の実施例を示し、第１図は全体を示すブロツク
配線図、第２図および、第３図は要部の結線図で
あり、第４図は従来のフエーダ回路を示すブロツ
ク配線図である。
１：信号源、２：ボリユーム、３，３Ａ：プリ
フエーダ、３Ｂ，４：パワーフエーダ、５：パワ
ーアンプ、６：プリアンプ、７Ａ〜７Ｆ：スイツ
チ、８：プリアウト端子、９：パワーアンプ入力
端子、１０：アツテネータ、１３Ａ：フロントス
ピーカ用出力端子（プラス）、１３Ｂ：フロント
スピーカ用出力端子（マイナス）、１４Ａ：リヤ
スピーカ用出力端子（プラス）、１４Ｂ：リヤス
ピーカ用出力端子（マイナス）、１５：外部パワ
ーアンプ、１６：外部機器、１７：フロントスピ
ーカ、２４Ａ，２４Ｂ，２５Ａ，２５Ｂ，２６Ａ
，２６Ｂ：端子、１８：リヤスピーカ、１９：他
のリヤスピーカ、２０，２１，２７：出力端子、
２２：Ａ信号、２３：Ｂ信号。
1 to 3 show an embodiment of the fader circuit according to this invention, FIG. 1 is a block wiring diagram showing the whole, FIGS. 2 and 3 are wiring diagrams of main parts, and FIG. The figure is a block wiring diagram showing a conventional fader circuit. 1: Signal source, 2: Volume, 3, 3A: Pre-fader, 3B, 4: Power fader, 5: Power amplifier, 6: Pre-amplifier, 7A-7F: Switch, 8: Pre-out terminal, 9: Power amplifier input terminal, 10: Attenuator, 13A: Front speaker output terminal (plus), 13B: Front speaker output terminal (minus), 14A: Rear speaker output terminal (plus), 14B: Rear speaker output terminal (minus), 15: External power Amplifier, 16: External device, 17: Front speaker, 24A, 24B, 25A, 25B, 26A
, 26B: terminal, 18: rear speaker, 19: other rear speaker, 20, 21, 27: output terminal,
22: A signal, 23: B signal.
Claims (1)
プとプリアンプの入力に接続しそれぞれのオーデ
イオ信号の入力バランスを設定するプリフエーダ
回路と、 このプリフエーダ回路からのオーデイオ信号を
入力しその出力をプリアウト端子に供給するプリ
アンプ回路と、 上記プリフエーダ回路から入力されたオーデイ
オ信号を増巾するパワーアンプ回路と、 このパワーアンプからの出力をフロントスピー
カおよび、リヤスピーカに分配し、それぞれの音
量バランスを設定するパワーフエーダ回路からな
るフエーダ回路において、 上記信号源に接続された音量設定ボリユームか
らのオーデイオ信号を２分配し、一方のオーデイ
オ信号が供給されるアツテネータ回路と、もう一
方のオーデイオ信号をさらに２分配して接続され
たプリフエーダ端子からの一方の端子を経たオー
デイオ信号と上記アツテネータ回路からのオーデ
イオ信号をそれぞれ選択可能にした第１のスイツ
チ回路と、上記プリアウト出力端子に外部機器を
接続して得られたオーデイオ信号と上記プリフエ
ーダ端子からのもう一方のオーデイオ信号をそれ
ぞれ選択可能な第２のスイツチ回路とを連動スイ
ツチで形成するとともに、プリフエーダ回路およ
び、パワーフエーダ回路も連動型可変抵抗器で形
成したことにより、プリフエーダ回路とパワーフ
エーダ回路を同時操作、またはパワーフエーダ回
路のみ操作を行うかどうか選択可能に構成したこ
とを特徴とするフエーダ回路。[Claim for Utility Model Registration] A signal source consisting of an audio signal, a prefader circuit that connects the audio signal from this signal source to the inputs of a power amplifier and a preamplifier and sets the input balance of each audio signal, and this prefader circuit. a preamplifier circuit that inputs an audio signal from the prefader circuit and supplies its output to a preout terminal; a power amplifier circuit that amplifies the audio signal input from the prefader circuit; and a power amplifier circuit that amplifies the audio signal input from the prefader circuit; an attenuator circuit which divides the audio signal from the volume setting volume connected to the signal source into two parts, and to which one audio signal is supplied; A first switch circuit that further divides the other audio signal into two and makes it possible to select the audio signal that passes through one terminal from the connected prefader terminal and the audio signal from the attenuator circuit, and the pre-out output terminal. A second switch circuit that can select the audio signal obtained by connecting an external device to the prefader terminal and the other audio signal from the prefader terminal is formed by an interlocking switch, and the prefader circuit and power fader circuit are also interlocked. 1. A fader circuit characterized in that the fader circuit is formed of type variable resistors so that it is possible to select whether to operate the prefader circuit and the power fader circuit simultaneously or to operate only the power fader circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5582687U JPH046320Y2 (en) | 1987-04-13 | 1987-04-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5582687U JPH046320Y2 (en) | 1987-04-13 | 1987-04-13 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63163100U true JPS63163100U (en) | 1988-10-25 |
| JPH046320Y2 JPH046320Y2 (en) | 1992-02-20 |
Family
ID=30884088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5582687U Expired JPH046320Y2 (en) | 1987-04-13 | 1987-04-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH046320Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100402497B1 (en) * | 2000-11-30 | 2003-10-22 | 주식회사 엘지이아이 | Heating device for microwave oven |
-
1987
- 1987-04-13 JP JP5582687U patent/JPH046320Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH046320Y2 (en) | 1992-02-20 |
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