JPS63158571A - Image forming device having editing function - Google Patents

Abstract

PURPOSE:To quickly attain an operation for forming an image by giving a separate image to an original image which has passed through a memory, or a converted image, by giving separate data partially to a flow of image data from the memory in synchronization with an output of the image data. CONSTITUTION:Image data stored in an image memory 36 is outputted serially through a data bus line DB. It is executed by turning on a monitor key 65 or a copy key 60. A signal of an address bus line AB is brought to conversion control so that, for instance, picture element data is read out of the memory 36 in order of store of its data and an image is reproduced as it is, or said data is read out in reverse to the order of store and an image reverse by 180 deg. is reproduced. As for its conversion control and a selection of a conversion mode, a manual command of a mode key 61 of an operating part 102 is executed by an internal command of a CPU. In such a way, it can be executed quickly to form an image by giving a separate image to an original image which has passed through the memory, or a converted image.

Description

[Detailed description of the invention] (branch) The present invention relates to an image forming apparatus having an editing function.

(Prior Art) Conventionally, it has been considered that original image information is stored in a memory and printed by reading it from the memory. It is also conceivable to perform image conversion such as image rotation in the memory.

In this case, in order to add another image to the original image or converted image at a predetermined position and print it,
This is possible by writing the image information to be added to a memory address corresponding to the addition position.

(Problems to be solved) Moreover, writing original image information or image liquid 1! !
! In order to load another image information into the memory after processing, it is necessary to access the address of the memory again, which takes time, and therefore the throughput from the start of loading the image to the memory to the start of image formation decreases.

(Purpose) The present invention eliminates the above-mentioned drawbacks, and aims to quickly form an image by adding another image to the original image or converted image via memory. do.

(Structure, operation) That is, a means for outputting image data from a memory that stores image information, and a portion for the flow of image data from the output means to add different image information to a part of the image information from the memory. forming an image to which different image information is added based on the image data added by the data adding means and the image data in the memory; The present invention provides an image forming apparatus having a IIJA collection function.

(Example) This will be explained below with reference to the drawings.

FIG. 1-1 is a schematic sectional view of an example of a copying machine according to the present invention, and FIG. 1-2 is a plan view of an operation section of the copying machine.
Figure 3 is a perspective view of the optical image reading section of the copying machine.

7fb 1-1 In the figure, 1 is the platen on which the original is placed, 2
A lamp irradiates the original with light, and moves in the direction of arrow 101 together with mirror 3.4 to expose the original to slit light. Reference numeral 5 denotes a lens system for imaging the light reflected from the original through a mirror onto an image sensor 6 composed of an OOD, 7 a control unit for reading and processing the image signal of the sensor 6, and 8 a laser beam source. 23 is its oscillation drive unit, and 9 is a polygon mirror 2 for sweeping the beam from the laser source inward.
-110 is f-〇 lens for peripheral correction of the deflected beam, 1
1 is a photosensitive drum; 12 is a corona charger that charges the drum surface; 13 is a corona charger that eliminates static electricity from the drum surface according to the image pattern; 14 is a lamp that performs static electricity removal with a variable key when the drum surface is not exposed to image; 11 A developing device for developing the Lm image; 16 a lamp for exposing the drum to an electrostatic latent image; 17 a corona charger for transferring the developed image to transfer paper from the cassette 18; 19
2 is a roller for fixing the transferred image; 20 is a tray for discharging and storing sheets with fixation defects; and 21 is a cleaner/greaser for cleaning the drum surface after transfer. 22
is the first central control unit OPU that controls the reading unit and the oversight unit 23;
, 24 is a second central control unit that controls copy process means such as a drum motor, charger, lamp, etc.

In Fig. 1-2, 60 is a copy start key, 62 is a numeric keypad for presetting the number of copies from one original, 63 is a slide lever for setting the shading of the copy image,
Reference numeral 64 is a memory key for writing the original image into the image memory, 65 is a monitor key for reading the image from the memory, and 61 is a select key for presetting the position, orientation, conflict relationship, etc. of the copy image. It has a self-illuminating lamp. Modes A to H are selected by 61a to 61h. Regarding modes A to H, a key 66, which will be described later, is a clear key for canceling the select mode by the mode key 61. A %67 is a select input pull switch that enables operation by the mode key 61.

In Fig. 1-3, 14-1 and 14-2 are self-scanning image sensors in which light-receiving parts are arranged in the slit direction.
Two ODs are provided serially, which improves the resolution of original reading. In other words, if an attempt is made to read the entire original image of size A3 width using a COD having a bit discrimination power in the light receiving direction 2, the resolution will deteriorate. Therefore, two pits were used serially to double the number of pits. 37-1~37
-4 is a buffer memory that temporarily stores the read signal from each 00D, 39-1, 39-2 is a switch element for selecting 37-1 to 37-4, and 36 is a semiconductor memory IJILAM that stores image data. The first control unit 22 is a control unit (described later) that performs address scanning control of the image memory 36, and includes an OPU that controls input to the image memory 36 and controls output of the image memory 36.

The operation will be explained with reference to all of FIGS. 1-1 to 1-4.

The surface of the drum 11 is made of a three-layer photoconductor using an OdS photoconductor, is rotatably supported on a shaft, and starts rotating in the direction of the arrow in response to a copy command when the copy key 60 is turned on. do.

When the memory key 64 is turned on, the document placed on the document table glass 1 is illuminated by the illumination lamp 2 integrated with the first scanning mirror 3, and the reflected light is transmitted to the first scanning mirror 3 and the second scanning mirror. Scanned by mirror 4. The first scanning mirror 3 and the second scanning mirror 4 move at a speed ratio of 1:1, so that the original is scanned until the optical path length in front of the lens 5 is always kept constant.

After passing through the lens 5, the reflected light image is formed on the light receiving section of the image sensor 6 (optical path 102).

The image is converted into a smoke signal by the self-scanning function of the COD for each slit line, and is sent to four buffer memories 37.
-1 to 37-4.

Data for one slit line from this buffer memory is inputted as serial data to the image memory 36 and stored sequentially from the initial address of the memory 36.

That is, the buffer 3 is
Select 7-1.37-3, 0OD14-1.14-2
The image data is stored in the buffer 37-1 and 37-3. Next, 39-1 and 39-2 are switched to select buffers 37-2 and 37-4, and data is stored therein.

At this time, the buffer 37-1゜37-
3 serially outputs data in the order of 37-1.37-2. Next, when the switch is changed again to store data in 37-1.37-3, the data is serially output to the memory 36 in the order of 37-2.37-4.

The image memory 36 is divided into areas according to pixels as shown in FIG. 6, and the data from the buffer is sequentially divided from the uppermost leftmost column to the right, and from the right end to the left end below the row. Serial data is stored by address scanning for all areas. The above buffer 37-1.37-
3 and 37-2, and 37-4, one scan is the one slit line data, and this data is
It is stored in 601 lines.

The image data stored in the image memory 36 is data bus-written from the memory by addressing the memory from the address bus line AB and by scanning the address for all areas. The output data is input to the well-known OR, T2O (Fig. 1-4) on the one hand, and the G3RT
The image of the electronic card is displayed on the cathode ray tube surface.

OR'rFi#6 is configured to display all the pixel data in the memory 36 in the figure, and the 081 plane is square accordingly.

The signal on the address bus line AB is set such that, for example, the pixel data is read out from the memory 36 in the order in which it was stored and the image is reproduced as is, or the data is read out in the reverse order from the stored order to reproduce a 180 reversed image. Conversion control is performed as shown in FIGS. 4 and 5. The conversion control and conversion mode selection are executed by a manual command from the mode key 61 of the operation unit 102 or by an internal command 61' of the OPU.

C! The RT 40 is provided to facilitate this manual selection control, and allows the selection operation of the mode key 61 by observing an image of the same mode as that on the grating on the CRT surface. It is possible to perform mode modification by displaying nine images by converting the image as shown below. The mode key 61 also presets and mode-latches the device to copy with the selected conversion speed.

In Figs. m4 and 5, the monitor state 201 is an image displayed on a CRT in a mode in which the position, direction, and front and back sides are not converted. Among them, the a'4fJ area corresponds to the original image on the platen surface, and the b'tJ area corresponds to the blank space in the memory where there is no original image data.

When the copy key 60 is turned on with the conversion preset, the pixel data from the memory 36 is output to the laser oscillation control section 23 via the switch element 105 and the buffer 38-1, 38-2 (@2 diagram). First, buffer 38-1
Pixel data is stored in buffer 3 by switching 105.
At the same time, the data stored in the buffer 38-1 is used to start the oscillation operation, deflection, and modulation of the laser beam of the laser oscillator 8.

The laser beam is swept in the horizontal direction by constant speed rotation of the polygon mirror 9, and is irradiated onto the photosensitive surface of the drum 11 in the horizontal direction via the f-θ lens 10.

The drum rotates at a constant speed to perform vertical scanning. This horizontal and vertical scanning is performed at a speed such that the electrostatic latent image formed on the drum matches the size of the original on the platen.

Simultaneously with the laser irradiation on the drum surface, the drum 1 is irradiated with an AC or a total static eliminator 13 with the opposite polarity (for example, -), and then further exposed with the entire surface exposure lamp 16.
1 to form a high-contrast electrostatic latent image. Stillness on the photosensitive drum 11 ii1. After infiltration, then by means of compensation device 15,
Visualized as a toner image. The cassette B8"o sheet is fed into the machine by the paper feed roller 25, and is sent to the transfer section with the timing set by the registration row 226 so that the leading edge of the sheet and the leading edge of the sheet coincide. The toner on the drum is transferred to the cassette by the transfer charger. The image is transferred to the sheet, fixed and discharged.
Complete the copy. This one image memory is 3
All pixel data related to the original stored in No. 6 has been reproduced. If multiple playback numbers are preset using the numeric keypad 62, when the beam scan for one copy is completed, readout of the memory 36 is restarted, the readout of the multiple copies is repeated, the beam scan is restarted, and the latent image is The desired number of copies is obtained by repeatedly forming the sheets as described above and continuously feeding the sheets by that number.

Incidentally, the cassette 18 stores a large number of sheets stacked in a certain direction. This direction is determined so that when the original is set at a predetermined position on the platen and when a copy is made without image conversion, the developed image is transferred to a predetermined position on the sheet in the cassette. That is, OR of 201 in FIG.
A sheet is set to copy area a on T.

In this way, copying in the same mode, which is frequently used, can be performed with a simple operation.

Also, the reproduced image selected with the mode key 61 etc. is 204°207
etc., the image may be only partially transferred to the sheet and a desired image may not be obtained. The present invention controls the reading of the image memory 36 so that even in such a conversion, the image can be copied and reproduced at an appropriate position on the sheet.

Next, image conversion control and conversion mode selection will be described in detail.

FIG. 2 shows an image conversion control circuit. In the figure, 32 is a bus conversion circuit that scans and controls the address bus AB.
The reference numeral 33 is an adder circuit that adds address bus data, and the reference numeral 34 is the bus conversion circuit 32, which is shown in detail in FIG. 8.
3 is a conversion control circuit for controlling the operation of the addition circuit 33, detailed in FIG.
7-1 to 37-4.38-1.38-2 are the aforementioned buffer memories, 41 is a shift register for converting the serial output of the data bus DB of the memory 36 into parallel output and sending it to the OPU, and 42 is the OPU QC! with a shift register to convert the parallel output from QC! into serial and send it to the memory 36. D14-1. Stored in memory via read line from 14-2. 43 is a switching circuit that switches whether or not to input data from the register 41 to the CPU or output it from the CPU to the register 42. The image memory 36 has a pixel area as shown in FIG.

Explain the operation. When an original is placed on the platen 1 and the memory key 64 is turned on, image data is stored in the image memory 36 as described above.

When the monitor key 65 is turned on, the memory 36 is
The stored data is output to the pass line DB and displayed on the 0RT 40 as a monitor image.

However, the data in the memory 36 can only be erased by turning on the original clear key OR or by the next memory operation using the memory key 641C.

Reading from the memory 36 will be described in detail.

Note that the monitor key 65 can also be omitted.

In this case, the memory key 64 is used to perform storage and monitoring functions. In other words, after the data is stored in the memory 36, the CRT is automatically monitored.

Now turn on the normal mode key 61h and press the monitor key 65
When turned on, the playback set is set in the same mode as the original. In this case, the address scan for reading from memory 36 is the same as the storage scan for memory 36 as described above.

Identify the memory area in Figure 6 (000000) 1g
is a code indicating the area of the top row, leftmost column (top left corner),
(00000n) Bl is the nth one on the right, (OOnOoo
) m is nth down, (OOloooF) we is 16th on the right in the 2nd line, (OOIFFF) ts is 16th in the 2nd line.
This is the x16 x 16th area. One byte of this code is shown as a 4-pit hex binary number. Therefore, this entire area can be specified using 24 bits (4×6). OP
U scans for reading from memory by adding 1 to the last 3 digits of the code and advancing by 000-+FFFK, then adding 1 to the top 3 digits, moving to the second line area, and again changing the lower 3 digits by 000-+FFFK.
Proceed to FFF, scan the second line, repeat this process, and output the pixel data of the entire area to the pass line DB at the beginning of scanning.

Note that writing to the memory 36 is also performed by repeating similar scanning.

The OPU sequentially outputs a group of 24-bit address signals for scanning. MIABO-MI that 24 pit signal
AB23 (Figure 3-1). The data is stored so that when the pixel data of the scanned address is 1, it indicates a sozu (dark area). Based on this data, the brightness of the laser beam is lowered to form a dark potential on the drum and cause toner to adhere to it.

By the way, the memory 36 is configured using a data bus 1.2147 made by Intel Corporation, for example. ``Bill'' semiconductor memory. Approximately 12 Mbits are required to store an original image of A4 size (296 x 210 m) when the desired resolution is approximately 14 images: A/-s. Above memo I
Since the J2147 has a storage capacity of 4KX4, or 16M bits, it can reproduce A4 size files with sufficient resolution. Furthermore, square images can be stored and copied and reproduced. This square area corresponds to the CRT. The margin when displaying A4 size is C.
Warnings when using a computer as a PU, etc.
It can be used as an area to display messages, comments, etc.

The pixels and memory addresses correspond as described above. Therefore, since the memory capacity is 16 Mbits, the address bus requires 24 bits as mentioned above.

Note that the image memory 36 can also be configured with a core memory, a wire memory, or the like.

When the monitor key 65 is turned on, the previous address data Ml is
, ABn are input from the CPU to the path conversion circuit 32, but the control latch signal SSO~88 from the conversion control circuit 34
Address bus conversion is controlled by 3K. control signal 5
8Q-ss3 is latched and input to 34 so that a specific mode can be converted by a mode key 61 or a mode signal 61' (FIG. 7) from the CPU as described later. The conversion control circuit 34 controls the multiplexer 5WO-8W23 in the conversion circuit 32 by using the control signal ss□-5s.
3, the connection of the address bus is switched by switching control.

The address data MI is sent via the switched line.
A B n is output from the conversion circuit 32 as M 2 A B n. The output is input to the adder 32, where it is added by the addition data % from the addition control circuit 35 and converted into an address bus.

The addition circuit is used, as will be described later, to correct the image converted by the conversion circuit 32) so as to return it to the copy area when it protrudes outside the reproduction area. The additional data % for this purpose is determined by Ol) U and output. In this way, the same operation as that for converting the pixel data in the memory is performed to convert the reproduced image.

The compensation conversion control circuit 34 shown in FIG. 7 will be explained.

In the figure, 61 is the conversion mode key, 100 is a 7-lip flop that latches input data from each key, and the clear key 66 cancels and resets the data. 10
1 converts latch data of 100 to 8-adjustment output A O-A I, for example, TI's 5N74. LSI4
This is an encoder such as 8N. Reference numeral 61' denotes a specific mode select signal from the CPU, which is determined within the copying machine when the copying machine is set in a specific state depending on, for example, the paper size and the magnification of the reproduced image. Normally (human size 4, life size), the same signal for normal mode as key 6th is output.

102 outputs either the mode signal from the key 61 or the mode signal 61' from the OPU. For example, it is a data selector such as 8N74, 157N manufactured by TI. 67
is a mode select switch that presets which of these signals is selected, and when it is turned on, that is, when the boat S is grounded, the latch signal from key 61 becomes IY.
Output as SSO~883 from boat ~4Y. This signal becomes the image conversion signal shown in FIG. 3-1.

When the select switch 67 is turned on and the key 61a is turned on, 880, 881, 882, 883 are all 1, when the key 61b is turned on, 0.1, 1, 1, and when the key 61c is turned on, 1.0, 1. O, key 61d is 0, 0, 1
, 0, and 1°1.0, 1 for key 61e. The key 61f is 0,1,0,1°, the key 61g is 1,0,0,0, the key 61h is o, o, o, o, 100,101.
°102 works.

(Shun Conversion Mode) The image conversion circuit shown in Figure K3-1 will be explained. swo~ in the figure
SW23 is a multiplexer, and the signal 8 in FIG.
Switch controlled by 80-883. This multiplexer is, for example, 5N74,515 shown in Figure 3-2.
This is possible with something like 3 (TI). 5WO-8W1
1,5WI2 to 5W23 move - each time. 3rd-
Twelve multiplexers in FIG. 2 are provided for two lines (ABn, ABn+1) of the 24 address bus lines in FIG. 3-1. Then, each line is connected to one output port 1 to 4 of SWn by control signals 880 to 883.

The following description will be made assuming that the addition data 0 to the addition circuit 33 is 0.

(1) 5SO=O, 5S1=O, 5S2=O, 5S
When 3=O (key 61h), the multiplexer is A B n in FIG. 3-2.

For ABn+1, each n0th boat 1, n+1
Output the group 0 boat 1. Therefore, the output data and input data of the address bus are M2ABO.

=MIABO,・・・・・・M2AB23=M1
The address bus is connected so that the address becomes 8B23, and no address conversion is performed. Therefore, no control is performed for image conversion, and after reproducing an unconverted image such as 201 in FIG. 4, the memory 36 is read out and the laser source 17 is modulated and deflected.

(2) 580=1.5S1=O, 5S2=0.8S
When 3=O (key 61g), the multiplexer 5WO-8W11 is output from boat 2 to ABn and ABn+1.

Also, 5W12 to 5W23 are ABn from boat 1.

Output to ABn+1. Therefore, the input data and output data of the address bus in the first half are M I A BP M 2AB
O......-MIAB11=M2AB11.
The second half is MI An 12=M2AB 12.
. . . m address buses are connected so that MIAB23=M2AB23, and the lower addresses are inverted. Therefore, copying is controlled to form a reproduced image such as 202 in FIG. 4, which is a horizontally reversed version of the original image.

(3) 5SO=0.5S1=0.8S2=1.5S
When 3=O (key 61d), in the multiplexer, 5WO-8WI 1 are all connected to the 1 position, and S to V12 to 5W23 are connected to the 2 position.

L7'c25Z is MIABO=M2ABO・-・・-
,・MIAB11=M2AB 11. MI AB 1
2=M2AB 12...MIAB23=M2A
B23 The upper address is inverted. Therefore, the image is upside down. The result will be as shown in FIG. 4 203.

f4) 8SO=1.881=O, 5S2=1.88
When 3=O (key 61C), the multiplexers SWO to 5W23 are all connected to the 2 position. Therefore, MIABO=M 2 A B
O・・・・・・・・・・・・MIAB23=M2AB
23, and all address buses are inverted. Therefore, the image becomes a vertically and horizontally inverted image #c4 as shown in FIG. 204.

(5) 880=0.8S1=1.5S2=O,5S
When 3=1 (key 61f), multiplexers 5WO-8W23 are all connected to the 3 position. Therefore, MIABO=M2AB12・
......MIAB 11=MIAB23. M
IAB12=M2ABO・・・・・・MIAB2
3=M2AB11, and the lower address and upper address of the address bus are swapped. Therefore, the image becomes as shown in FIG. 4 205.

(6) 5so=t, 5S1=1.5S2=O,5
When S3=1 (key 61e), multiplexers 5WO-8W11 are all in position 4, 8W
12-5W23 are all connected to position 3.

Therefore, MIABO=M2AB12...
・MlλBll=M2AB23. MIABl 2=M2
ABO...MlλB23=M2AB11 The lower address is inverted and the upper and lower addresses are switched. Therefore, the image is as shown in Figure 4 (12
It becomes 06.

(]) 880=O, 581=1,5S2=1,5S
When 3=1 (key 61b), multiplexers SWO to 5WII are all in the 3 position.

5W12 to 8W23 are all connected to position 4.

Therefore, MIABO=M2AB12...
・MIABII=M2AB23. MIAB12=M2A
BO・・・・・・Mt AB 23=M2AB
11, the upper addresses are inverted and the upper and lower addresses are switched. Therefore, the image becomes image 207 shown in FIG.

(8) 5SO=1.881=1.5S2=1.5S
When 3=1 (key 61a), multiplexers 8WO-8W23 are all connected to position 4, and MIAf3o=M2AB12...M
IABII=M2AB11, and both the upper and lower addresses are inverted. The upper and lower addresses are switched, so the image becomes 208.

Also, 5SO=O, 581=1.882=0.583=0°5SO=1, 5S1=1,582=0, 5S3=O.

5SO=0, 8S1=1, 5S2=1, 5S3=O.

5SO=1, 5S1=1, 5S2=1, 5S3=O.

5SO=O, 5S1=O, 582=O, 5S3=1゜5
SO=1,5S1=0,8S2=0.883=1°5S
O=0,581=0,582=1,5S3=1゜5SO
The combinations =1,581=O, 582=1,583=1 are prevented from being output by the control circuit 34.

(Protrusion Correction) FIG. 5 is a diagram in which the image conversion by the conversion circuit 32 is further corrected by an addition method.

For example, suppose that an A4 size image (7) is stored in the FLAM 36 by the above scanning. This is 201a in Figure 4.5. Even if the memory 36 is a square including the shaded area bK, the image of the shaded area bK is not stored. Therefore, even if a copying operation is attempted, the shaded portion of the image 201 will not be copied due to the direction of the paper. The copyable portion is hereinafter referred to as a playback area.

When this image area a is converted into an image, for example, by turning on the key 61c, 880, 881. SS2. S83 is 1.0,1
．． In the case of O, the image is reversed as shown in the image 204, but the image storage portion of the memory 36 extends beyond the reproduction area as shown in FIG.

In this example, the adder 33 adds the data 00-023 to the address bus data AB O-AB 23, thereby moving the image in parallel as shown in the image 209, and performing address correction conversion to move the image area to the reproduction area. do. By doing this, parts that are not copied and played back are eliminated. It is also possible to cancel and copy an unnecessary image that is intentionally made to protrude.

! In the adder circuit shown in FIG. 8, F'AO to FA3 are well-known 4-bit parallel binary adders, and there are six groups of them. statue 20
If we assume that the translation to 9 is to move it up m lines, we can do it by adding -m to all the row addresses. That is, input binary bits corresponding to -mK to CO~011, add them to address bus bits M2ABO-M2AB11,
This can be achieved by issuing a memory address command using the addition outputs M3 BO to M3AB23.

Also, 5SO=0, 5S1=1, 5S2=1, 5S3=1
In the case of , one image is converted vertically and horizontally, so 20 in Figure 5
A one-plane image of 1 is converted to 207. Therefore, about 3ON
The image area of will be moved outside by the playback area, and the image will be closer to the left edge. In this case as well, the non-image area can be moved to any position by adding an arbitrary number using the addition ``a'' 33. 210 in FIG. 5 shows a diagram when the image is moved to the center. That is, it is moved up j rows and lCp columns to the right, and the bit corresponding to -1 is input to CO~011, the bit corresponding to +pK is input to bits 4012~023, and each addition is performed to the pass bits M2ABO~M2AB23. Therefore, M3ABO to M3AB23 by addition
Addressing by the output of K can be achieved by K. 0
By arbitrarily setting data 0-011, 012 to 023 using the numeric keypad 62, the image can be moved to an arbitrary position.

Similarly, images 202 and 203 in FIG. 4 can be converted and corrected as shown in step 204, and images 205, 206, and 208 can be converted and corrected as shown in step 207, and can be copied and reproduced at appropriate positions on paper.

To copy, turn on the monitor key 65 and press C as described above.
After checking the converted image and turning on the copy key 60, the scan data from the initial address is sequentially stored in the buffers 38-1 and 38-2, and the printing operation is started.

In addition to small additions, it is also possible to prevent the conversion unit from protruding from the reproduction area by performing a reduction readout operation. As a reduction method, the drum rotation speed is lowered and laser scanning is synchronously controlled, and the address data M I AB from the CPU is
It is also possible to output a reproduced signal reduced to % by skipping 1 bit in each row direction (horizontal) data M I A B n and performing address scanning at the same scan speed. .

Addition and subtraction data 1'l necessary for conversion of these specified modifications
, m, p, etc. are preset in the CPU in correspondence with data 880-883.

And the control signal SSO~883 from the conversion control circuit 34
The data is taken into the CPU to determine the mode, and the CPU selects appropriate addition data suitable for the mode and outputs it to the addition control circuit 35.

This directly corresponds to the address bus output M 2 A of the circuit 32
This is also possible by checking B n and selecting a predetermined addition number.

The addition data G on the write path 23 from the CCD to the image memory 36 is set to OK. In both cases, the OPU determines the key 64 and sets it to 34.35 so that it becomes normal.

By the way, it is also possible to store an image converted in advance at the time of writing into the memory 36, by first latching the data using the mode key 61 and controlling the address, and then using the latch signal 8So-883 to calculate the addition amount of 35 as described above. Decided,
Next, the memory key 64 is turned on to cause the R and AM 36 to execute writing through the mode-specific address bus connection. Then, the mode key 65 is used to connect the address bus in the normal mode, and output pixel data.

In order to prevent malfunction of conversion during writing and conversion during reading, the control circuits 34 and 35 are configured so that image conversion is possible when the mode key 61 and write key 64 are activated in the former case, and when the key 64 and key 61 are activated in sequence in the latter case. It is desirable to prohibit control.

When the change switch 68 in Figure 1-2 is turned on to the left, only 61 → 64 is changed, and when it is turned on to the right, it is changed from 64 to 64.
Only 1 is allowed.

Powered.

The control signal 61' is transmitted to the memory key 64, monitor key 65,
It is output by one of the print keys 60 and is normally a normal control signal.

Further, in this example, by transferring data to reproduce an image in the same mode up to a certain intermediate address and then switching the address bus, it is also possible to make the image from that address onward into the above-mentioned conversion, such as image reversal.

Shift register 42FiOP in AW 21'gJ
The pixels of the message from U can be stored in the non-picture area b of R and AM36. In this case, when writing the original image, the register 42 is controlled to output according to the timing of scanning the area b.

Messages include CPU trouble status and the like. The message of this area b is as mentioned above (72 hours C 几TKf
i is shown. When the mode key 61 is turned on to perform image conversion, this message is erased and is not printed.

Note that image data (numbers, etc.) for doubling or numbering is transferred from the CPU via the register 42 to the memory 3.
It is also possible to store K in an area (surrounding area A) that does not adversely affect the original image of No. 6 and cause no trouble, and to reproduce the data at the time of image conversion. This problem-free location is where the monitor data from the shift register 41 is transferred to the CP.
U can also read and decide.

In Figure 0!9, a part of the document image or converted image in the row direction (horizontal direction) is completely copied in white (a) and in black (b). Also, part of the column (vertical) direction was similarly pressed (C).

(d) oSoreK allows you to cancel and copy the anxious and secret parts. Therefore, confidentiality can be maintained and an area for writing notes can be used as a copy sheet.

FIG. 10 is a control circuit diagram for copying a and b. In the figure, 200 is an AND gate provided with a data bus DBK in order to prevent the serial image data from passing through the )-I level (1) from the memory 36 to the CR, T 40 and buffer 38-1, 38-2, and 201 is an AND gate for the image data. Outputs high level regardless of data (data bus DB)
K set up or gate, 202 is goo) 200.201
This is the signal source that controls the

The high level of the image data represents black, and the low level represents white.

To explain the operation, normally the output α1 of the control signal source 202 is set to 1. Let α2 be O. Therefore, only the image data on the data bus DB passes through the gates 200, 201, and a copy of the normal image or the transformed image is obtained as described above. However, α1. When 0 is generated in both α2 for a predetermined time during the output scan of the memory 66, the gate 200 prevents the serial image data O from passing during that time. Therefore, in the meantime, white is partially copied as shown in FIG. This predetermined time is determined in synchronization with serial address data (MIABn) from the CPU. In other words, the predetermined serial address x1 is the starting point of image data blocking.
The signal source 202 is synchronously controlled so that signal source 202 becomes the end point. In order to sense these xi and x2, use dedicated keys 0 to F or the numeric keypad 42. Using mode keys 61 (A-F),
Row data x'l, x'2 at address xi, x2
(First 3 digits) K corresponding numerical value (000 to FFF) to CP
U or signal source 202. yl by the first key operation three times is preset to XI 1, and y2 by the latter three key operations is preset corresponding to x'2.

Then, when x' 1 and yl match, the CPU changes the signal α1 of 202 to 1 and outputs it, and outputs x' 2 and y2.
When K matches, the 0 is returned to 1, so that the space between addresses x1 and x2 becomes blank. In addition, on the left side of CR, T, corresponding to 0 to person in the first digit of the row address data, 0
~If you mark people, you can partially cancel them while monitoring them on the CRT. Furthermore, in order to carry out the above and subsequent operations using an image that has been transformed vertically, horizontally, etc. as described above, it is preferable to first store the transformed image in the memory 36.

Next, the signal source 2020α2 from address x1 to X2
When is set to 1, the high level is outputted as image data through the gate 201 and becomes a partial point as shown in Figure 9.
, a white key WT, and a black key BL are provided on the console 102. α1. The output of α2 is held until the desired number of identical copies from memory 66 have been made.

The launch circuit 100 in FIG. 7 is also reset at the end of the last beam scan until the copy is completed.

FIG. 11 is a control circuit diagram for copying c and d. In the figure, numeral 500 is a counter that checks and counts the second most significant bit of the column address of the 24-bit address data from the CPU. Kakunta can be reset using the 0 to F keys. In other words, Kakunta counts 16 VCs while sayayaning one line, and then resets them. Therefore, if the key is used to preset in the order of, for example, 4 → 8, the kakunta will increase by 4 and output a pulse to change α1 from 1 to 0. α2 is set to 0 as it is. After 8 more digits, a pulse is generated and α1 returns to 1.0
Combining this, 202 is α1. Output 1.0 to α2 and print the image data as is. Furthermore, the black key BL
By turning on, α2 can be set to 1 between 4 and 8, and a black copy can be made. Blank copying is performed using the white key WT.

FIG. 12 shows a copy of a document image in which a part of the document image is canceled in the row direction, and the front and back of that part are closed. This makes copies easier to read because blank areas of the document are not printed.

This is possible by activating the adder 33 (Fig. 2) when the memory address data from the CPU reaches XIK, and adding nl to the subsequent address data as addition data Ca-Czs (K8u). Become. This is because the address jumps to X2 at the point x 11 (n plus 1). These xl and x2 can be arbitrarily preset as KCPUK using the same keys as above (as shown in Figure 10). Calculate the desired Co
-Cx5 is determined and set in the adder 63 at the timing described above.

Even if a part of the image in the memory 36 is jumped, the scan may be repeated from the initial address after the first scan is completed.This is especially the case with repeat copying. Therefore, memory 36
You may read out the first part of the sheet and copy the second half of the sheet. In order to prevent this, the 1 of the OVF of the addition output shown in Fig. 8 is scanned in the memory of 1 way of the unbalance shown in Fig. 10, and after the output of MsAB 24 becomes all 1, the over 70 output OVF is output. Therefore, from this point onwards, the image data becomes blank due to 200. At the same time, the addition data Co to C21 are canceled, and the repeat copy temporary is automatically added and set again at the time point xl. Note that the OVF is reset every time one copy is completed.

In FIG. 10, if the CPU determines the intermediate position between addresses xi and x2 and causes α2 to output a serial pulse of 1 briefly and periodically, the broken line near the center of the blank area can be reproduced and copied.

・r-,-,J (Effect) As described above, different data is partially added to the flow of image data from the memory in synchronization with the output of the image data, so the original data via the memory is The operation of forming an image by adding another image to the image or the converted image can be quickly achieved, and the throughput of image formation can be increased.

[Brief explanation of the drawing]

Figure 1-1 is a sectional view of a copying machine to which the present invention can be applied;
Figure-2 is a plan view of the operation section of the copying machine in Figure 1-1, and Figure 1-3.
The figure is a partial perspective view of the copying machine shown in Fig. 1-1, Fig. 1-4 is a perspective view of the outer unit of the copying machine shown in Fig. 1-1, and Fig. 2 is an image conversion in the copying machine shown in Fig. 1-1. Block diagram, Figure 3-1, Figure 3-
IA diagram, Figure 3-18, Figure 3-2, Figure 7, and Figure 8 are the circuit diagrams in Figure 2, Figures 4 and 5 are diagrams showing image conversion, and Figure 6 is the circuit diagram in Figure 2. Figure 9A showing the memory map in Figure 2.
Figures 9B, 9C, 9D. FIG. 12 is a diagram showing another image conversion, and FIGS. 10 and 11 are circuit diagrams for performing the image conversion of FIG. 9. In the figure, 14-1 and 14-2 are original image reading means;
36 is a memory, 200 and 201 are output data control gate circuits, 33 is an adder circuit, and 34 is an address bus conversion control circuit.

Claims (1)

[Scope of Claims] Means for outputting image data from a memory storing image information; forming an image to which different image information is added based on the image data added by the data adding means and the image data in the memory; An image forming apparatus having an editing function.