JPS63156261A - Decision system for memory access condition - Google Patents

Abstract

PURPOSE:To decide whether the operation of a memory is possible or not at each time of access by storing information classification data correspondingly to addresses and reading out this data at the time of memory access from a processor to compare it with operation classification information from the processor. CONSTITUTION:Information classification data indicating address area information of the memory is read out from an information classification storage part 4b and is stored in an information classification register 6. Meanwhile, a processor 1 sends operation classification data indicating the classification of instruction read or data read/write together with an address and data information at the time of accessing the memory and stores this operation classification data in an operation classification register 5. A deciding circuit 7 compares stored data of registers 5 and 6 to decide whether the access operation is possible or not. Consequently, the erroneous access to an unused area or the memory access to destroy the contents of an instruction area or a read-only data area is immediately detected. Thus, the safety of the system is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for determining memory access conditions, and particularly to a method for determining whether or not memory access is possible in a storage program method.

[Conventional technology]

As a conventional method for determining memory access conditions, a memory access method shown in FIG. 2 (final diagram) is known.

In FIG. 2, 15 is a storage unit, 16 is a central control unit 2, and key information sent from the central control unit 16 during a write operation is stored in a key register 17.

On the other hand, in order to prevent the contents of the storage section 15 from being destroyed due to an erroneous write operation, a lock register 18 is provided in the storage section 2 of the storage section 15 to store write operation conditions in units of words.

The key comparison circuit 19 compares the key information from the key register 17 and the write operation conditions from the lock register 18, and determines whether writing is possible or not according to the table below.

The control circuit 20 performs a write operation to the storage unit 15 only when the determination result of one key comparison circuit is that writing is possible, and notifies the central control unit 16 of an error when the conditions do not match and writing is not possible.

The memory contents are protected by the memory key only during a write operation, and in other cases it is always treated as a condition match.

[Problem that the invention seeks to solve]

However, since the above-mentioned memory key system determines the conditions only during the write operation to the storage unit 15 and prevents memory destruction, it is not possible to detect mismatch of conditions when reading instructions or reading data.

Also, the setting range of the memory key is set in a certain area (for example, 2
Because it is specified in word units), it is necessary to consider memory allocation when creating a file, and there is also the problem that conditions cannot be set for each address.

The present invention was created in view of the above points, and an object of the present invention is to provide a method for determining memory access conditions that solves the above problems.

[Means for solving problems]

The memory access condition determination method of the present invention includes an information type storage section in which information type data is stored in advance for each address of the memory, a processor that sends out operation type data at the time of memory access, and a processor that stores the operation type data. Compare the storage section &, the information type data and the operation type data,
and determining means for determining whether or not a memory access operation is possible.

[Effect]

Information type data indicating the type of area information of the memory address, that is, unused area, instruction area, read-only data area, or read/write data area, is stored based on the address information from the processor. The data is read out from the section and supplied to the determination means.

On the other hand, when accessing the memory, the processor sends out operation type data indicating whether it is instruction reading, data reading, or data writing, together with address information and data information, and stores it in the storage means.

The determining means compares and refers to the information type data and the operation type data, and determines whether the conditions match or do not match. Only the instruction area can be used when reading an instruction from the processor (1-fetch). Furthermore, for operand reading (P-fetch) from the processor, both the read-only data area and the read/write data area can be used in the case of load-related instructions. Historically, for P-fetch store instructions, only the read/write data area can be used, and for jump instructions, only the instruction area can be used.

According to this condition, the determining means constantly determines whether or not a memory access operation is possible for each type of memory access.

〔Example〕

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In the figure, a processor 1 and a memory device 2 are connected via a bidirectional bus 3 (consisting of a data bus and an address bus).

The memory device 2 is, for example, a random access memory (
It consists of a memory 4 (RAM), an operation type register 5, an information type register 6, a determination circuit 7, latches 8 and 10, and gates 9 and 11.

The memory 4 includes, in addition to a program storage section 4a that stores program information, an information type storage section 4b in which information type data indicating the type of area information of that address is stored in advance for each address of the program storage section 4a. Consisting of

The above information type data is 'oo' when the corresponding address of the program storage unit 4a is an unused area;
Information is stored by branch as a value of '01' if it is an instruction area where instructions are stored, '10' if it is an output-only data area, and 7117 if it is a read/write data area where both reading and writing of data is possible. It is stored in the section 4b.

The unused area is an area in which neither command reading nor data writing or reading is possible, but it can be changed to another area by rewriting the program in the future.

When accessing the memory, the processor 1 sends operation type data to the memory device N2 side in addition to address information and data information. This operation type data has a value of, for example, '01' for a read instruction, 'io' for a load type instruction, and 7117 for a store type instruction.

Next, the operation of this embodiment having the above configuration will be explained.

When processor 1 accesses memory, address information and operation type data from processor 1 are sent to bus 3,
Of these, address information is supplied to the memory 4 via the address bus 12, and operation type data is supplied to the operation type register 5 via the address bus 12, where it is temporarily stored. Further, data information sent from the processor 1 in the case of a store-related instruction is held in the latch 8 via the bus 3 and the data bus 13.

Based on the address information input to the memory 4, the information type data of that address is read out from the information type storage section 4b and supplied to the information type register 6, where it is temporarily stored.

The determination circuit 7 is supplied with operation type data from the operation type register 5 and information type data from the information type register 6, and determines whether or not a memory access operation is possible according to the following table.

As can be seen from the above table, since only the instruction area can be used in the case of instruction reading, the determination circuit 7 determines that access to the read-only data area, read/write data area, and unused area is an error. Similarly, in the case of a store-related instruction, only access to the read/write data area is possible, and in this case, the determination circuit 7 opens the gate 9 and transfers the stored data information of the latch 8 to the designated address of the program storage section 4a. However, access to other unused areas, instruction areas, and read-only data areas is determined to be an error, gate 9 is closed, and writing of data information is prohibited.

In addition, in the case of a load type instruction, as shown in the table above, it is possible to access both the read-only data area and the read/write data area, so the determination circuit 7 determines that the instruction is normal in these cases. The gate 11 is opened, and the data information read from the specified address in the program storage section 4a is sent to the bus 3 through the latch 10 and the gate 11.

However, even though the instruction is a load type instruction, if the access is to an unused area or an instruction area, the determination circuit 7 determines that there is an error and closes the gate 11.

In this way, according to this embodiment, whereas conventionally only store-related instructions could be determined, the memory access conditions for instruction read and load-related instructions can also be determined. , access to unused areas, destruction of instruction areas, read-only data areas, etc. can be immediately detected in units of one word.

Note that the determination circuit 7 may be provided with a function that determines that only the instruction area is normal in the case of a jump instruction, and that access to other areas is determined to be an error.

〔Effect of the invention〕

As described above, according to the present invention, the type of accessible area is constantly determined for each type of memory access, which prevents erroneous access to unused areas and destruction of instruction areas and read-only data areas. Such memory accesses can be immediately detected, thereby preventing runaway programs and destruction of memory contents, and improving system stability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional memory key system. In the figure, 1 is a processor, 2 is a memory device, 3 is a bus, 4 is a memory, 4a is a program storage unit, 4b is an information type storage unit, 5 is an operation type register, 6 is an information type register, and 7 is a determination circuit. be. Kikuyaku 0 - Soukukuka 1ri structure diagram 1st figure
figure

Claims (1)

[Claims] An information type storage unit (4b) in which information type data indicating the type of area information of the address is stored in advance for each address of the memory (4), and at least the address information at the time of memory access. , a processor (1) that sends out operation type data indicating whether it is an instruction read, a data read, or a data write; a storage means (5) that stores the operation type data; and an address from the processor (1). determining means (for determining whether or not a memory access operation is possible by comparing the information type data read from the information type storage section (4b) based on the information with the operation type data from the storage means (5); 6, 7)
A memory access condition determination method characterized by comprising the following steps.