JPS63153963A - Synchronization separating device - Google Patents

Abstract

PURPOSE:To obtain a synchronizing signal with constant pulse width, by detecting the pulse width of the synchronizing signal separated from a video signal by a counter circuit, correcting the pulse width, and eliminating an erroneous synchronizing signal. CONSTITUTION:The leading edge of the synchronizing signal S2 separated at a synchronizing separator circuit 20 is detected by an FF41, and a counter circuit 42 starts count up. At this time, when the synchronizing signal S2 is the erroneous synchronizing signal, the synchronizing signal S2 falls before the counted value of the counter circuit 42 arrives at (t1), therefore, the output of an OR circuit 46 goes to an L, and the counter circuit 42 starts count down. When the counted value of the counter circuit 42 arrives at (t2) in the count down, the output of an AND circuit 43 goes to the L, then, the counter circuit 42 is cleared. As a result, an output signal stays at the L, and no errorneous synchronizing signal is outputted. Also, the pulse width of the synchronizing signal is corrected at a constant value (t2-t1), then it is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a synchronization separation circuit that detects only the correct synchronization signal among synchronization signals that have been incorrectly separated due to noise, etc., and that the width of the same signal is constant. This relates to a synchronization separation device that corrects so that

Conventional technology In television receivers, video tape recorders, and the like that perform signal processing based on synchronization signals, it is necessary to correctly separate the synchronization signals in order to perform the processing correctly. A conventional synchronous separation circuit will be described below with reference to the drawings.

FIG. 4 shows a conventional synchronous separation circuit. Fourth
In the figure, 1 is an input terminal for inputting a video signal, 2 is an output terminal for outputting a synchronization signal, 3 is a sync chip clamp circuit, 4 is a low-pass filter, and 5 is a comparison circuit. The operation of the separation circuit will be explained below. The video signal Sl is input to the sync tip clamp circuit 3 from the input terminal 1, and the sync tip is clamped at the sync tip voltage v3. Video signal S1 with sink chip 7 clamped at sink chip voltage v3
is input to a low-pass filter 4 to remove color signal components and noise. The video signal S2 from which the color signal component has been removed by the low-pass filter 4 is input to one input terminal 5a of the comparator 5. A voltage obtained by adding the power source Va to the power source Vr is applied to the other input terminal 5b of the comparator 5. Here, if the magnitude of this voltage fiVr is made smaller than the synchronization signal amplitude of the input video signal, input terminal 5a and input terminal 5b
The applied voltages are compared, and a synchronization signal shown in FIG. 5 is obtained at terminal 2. (For example, JP-A-58-187078
Problems to be Solved by the Invention However, with the above configuration, if an erroneous signal is separated as a synchronization signal due to noise etc. as shown in FIG. In addition, if the video signal is distorted due to noise, etc., there is a problem that the width of the separated sync signal may not be constant even if the erroneous signal is not separated. Was.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention provides a synchronization M device that correctly detects a synchronization signal even when noise or the like is mixed into a video signal, and corrects the width of the synchronization signal to be constant. be.

Means for Solving the Problems In order to solve the above problems, the synchronization separation device of the present invention includes means for separating the @ period signal contained in the input video signal from the input video signal, and means for separating the - period signal.

means for controlling a counting circuit that is controlled by a signal from the means and a first signal and that counts clock signals of a predetermined frequency; and a first gate that gates the output of the means for separating the synchronization signal and the second signal. and a first detection circuit for detecting each time the count value of the counting circuit reaches a first predetermined value when the gate means and the counting circuit are controlled by the output signal of the first gate means. a second detection circuit that detects that the count value of the circuit has reached a second predetermined value;
a detection circuit, a circuit that determines and outputs a second signal based on the signal from the second detection circuit, and a circuit that determines and outputs a second signal based on the signal from the second detection circuit, and a circuit that outputs a signal from the counting circuit that indicates that the counted value of the counting circuit satisfies a certain condition. a second gate means for gating a determination output signal and a signal from the second detection circuit, wherein the first signal is an output signal of the gate means of the IJ2;
The second signal is also configured to be obtained as a synchronization signal.

Effect of the present invention With the above configuration, the pulse width of the synchronization signal separated from the video signal is detected by a counting circuit, and by correcting the pulse width, an incorrect synchronization signal is eliminated, and a correct synchronization signal is detected. If so, the pulse width is corrected to a constant pulse width and output.

Embodiment Hereinafter, a synchronization separation device according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a synchronization separation device in one embodiment of the present invention, and FIG. 2 is a waveform diagram of each part thereof.

In FIG. 1, reference numeral 10 has an input terminal 30 for a video signal, an output terminal for a synchronization signal from which noise has been removed and has been corrected to a constant pulse width, 41 has a clear input terminal, and a data input terminal 50 has a high level (hereinafter referred to as Low level is “L1” High level is “1”
D-Flympflovb, 60
The clock input terminal 20 has a conventionally known predetermined threshold value V.
Synchronization separation circuit that separates synchronization signals by comparing amplitudes with r, 4
3 is an AND circuit, 46 is an OR circuit, 42 is an amplifier/down counter that has a clear signal input terminal and a ripple carry output terminal, 47. 48 compares the count value of the counter with a predetermined set value, and A detection circuit 45 outputs a detection pulse when the count value of 45 is less than a predetermined set value. Reference numeral 45 is a circuit that changes its output state depending on the input state of an input signal, and is, for example, an RS flip-flop.

Video signal 31 input from terminal 10 (Fig. 2(a))
is input to the synchronization separation circuit 20, which compares it with a predetermined dark value voltage Vr and outputs a synchronization signal 32 (the peak in FIG. 2). The synchronization signal S2 is input as a clock signal to the clock input of the D-Flisobfromp circuit 41. The data input terminal 50 of the D-flip-flop circuit 41 is always 1H''
Therefore, "H" is latched at the rising edge of the synchronization information, and the output signal CLR2 becomes "H", and the output signal CLR2 is connected to the clear input terminal of the up/down counter. S2 is an OR circuit 46
As a result, the output of the OR circuit 46 becomes H1 at the rising edge of the synchronizing signal, and the output signal is connected to the up/down control signal input terminal of the amplifier/down counter. When the up/down control signal input is in the "H" state, the up/down counter 42 starts counting up in response to a clock signal of a predetermined frequency applied to the input terminal 60.

If the synchronization signal separated by the synchronization separation circuit 20 is correct as shown in FIG. When Fig. 2 (C1) reaches tl, the first detector 48 outputs a detection pulse 5T.
I (FIG. 2(d)) is output. This detection pulse ST
I is connected to the cent input terminal of the RSS flip-flop 4, and as a result, the output terminal of the RS flip-flop 42 becomes "H" (FIG. 2 1fl), and the output terminal of the RS flip-flop 42 becomes "H". It is connected to the other input terminal of the OR circuit 46, and as long as the output terminal of the RS flip-flop 42 is 1H'', the OR circuit 4
Since the output terminal of 6 is also "H" and the signal is connected to the up/down control input terminal of the amplifier/down counter 42, the up/down counter 4 continues to be output.
The up-count of 2 continues.

Next, when the count value 0LIT1 of the up/down counter 42 reaches t2, a detection pulse RT2 (FIG. 2(e)) is output from the second eating device 47.

This detection pulse RT2 is connected to the reset input terminal of the RS flip-flop 45, and as a result, the output signal SYN of the RS flip-flop 42 becomes "L" (Fig. 2 (fl)), and the second detection pulse RT2 is connected to the reset input terminal of the RS flip-flop 45. Output signal R of the device 47
T2 is connected to one input terminal of the AND circuit 43. The output of the AND circuit 43 is connected to the clear input terminal of the D-flip-flop 41, and as a result, the D-flip-flop 41 is cleared and at the same time the up/down counter 42 is cleared, and the next input It enters a state of waiting for the rising edge of the synchronization signal S2.

Next, between the above inputs! A case where the IJI signal S2 is an erroneously detected signal as shown in Fig. 3 will be explained.

As in the case where the correct synchronization signal is generated manually, the rising edge of the synchronization signal S2 is detected and the up/down counter 42
starts counting up (Figure 3 (C1), L
However, the count value of the amplifier/down counter 42 is 0UT.
Since the manual synchronization signal S2 falls before 1 reaches tl, the output terminal of the OR circuit 46 becomes L°. The output terminal of the OR circuit 46 is connected to the up/down counter 42.
Because it is connected to the up/down control input terminal of
The up/down counter 42 starts counting down. (FIG. 3 (C1), when the count value 0UTI of the up/down counter 42 becomes φ due to down counting, the ripple carry output RC (FIG. 3 (d)) of the up/down counter 42 becomes "Ll". The ripple carry output R of the up/down counter 42 is
C is connected to the other input terminal of the AND circuit 43, and the output of the AND circuit 43 becomes "Yes", and the 7 sub/down counter 42 is output in the same manner as described for the case where the correct synchronization signal is manually generated. is cleared, and the state returns to the state where the input synchronization information S2 is waiting for start-up/nozzle.

As a result, the output signal SYN (Fig. 3(e)) is “
If it remains at "L", an erroneous friend signal will not be output.

As a result of the above-described operation, in this embodiment, the synchronization separation circuit does not output as a synchronization signal a signal detected as a synchronization signal but whose pulse width is less than t1 due to noise, etc. The pulse width detected as a synchronization signal is 1. For the above correct synchronization signals, the pulse widths are all corrected to a constant value of (12-1,) and output.

Effects of the Invention As described above, the present invention adds a small number of circuits to the output of a sync separation circuit that separates sync signals by comparing their amplitudes using a known predetermined threshold value Vr, thereby eliminating erroneously detected sync signals. , and for correctly detected synchronization signals,
An excellent effect can be obtained in that the pulse width is corrected and outputted to a constant value.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a sync separation device in an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the operation of FIG. 1, and FIG. 4 shows a conventional sync separation circuit. The block diagram, FIG. 5, is a diagram of the input waveform of FIG. 4 and the corresponding output waveform. 10...Input terminal, 20...Conventional synchronous separation circuit, 30...Output terminal, 42...
...Counting circuit, 47°48...Detection circuit, 41
．． 45...Flymbuflovup, 43.46...
...Gate circuit. Name of agent: Patent attorney Atsuo Nakao (1 person) Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] means for separating a synchronization signal contained therein from an input video signal; and a control signal to a counting circuit that is controlled by the output signal of the means for separating the synchronization signal and a first signal and that counts clock signals of a predetermined frequency. a first gate means for gating the output signal of the means for separating the synchronization signal and a second signal;
a first detection circuit that is controlled by an output signal of the gate means and detects that the count value of the counting circuit has reached a first predetermined value; a second detection circuit that detects that the signal has been detected, the output signal of the first detection circuit and the output signal of the second detection circuit are input, and a second signal is determined based on the state of the two input signals. and a second gate means for gating an output signal from the counting circuit indicating that the counted value of the counting circuit satisfies a certain condition and an output signal from the second detection circuit. A synchronization separation device characterized in that the first signal is an output signal of the second gate means, and the second signal is obtained as a synchronization separation output.