JPS63153849A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS63153849A
JPS63153849A JP30252086A JP30252086A JPS63153849A JP S63153849 A JPS63153849 A JP S63153849A JP 30252086 A JP30252086 A JP 30252086A JP 30252086 A JP30252086 A JP 30252086A JP S63153849 A JPS63153849 A JP S63153849A
Authority
JP
Japan
Prior art keywords
package
semiconductor device
substrates
outer lead
mounting density
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30252086A
Other languages
Japanese (ja)
Inventor
Yuji Matsubara
松原　祐司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP30252086A priority Critical patent/JPS63153849A/en
Publication of JPS63153849A publication Critical patent/JPS63153849A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To increase the mounting density of substrates by a method wherein, within a semiconductor device with outer lead protruding from only one side of a package, the package is inclined in the direction of the tip of outer lead. CONSTITUTION:An outer lead 1 is bent so that the direction B of package 2 may make an oblique angle alpha with the direction A of the tip of outer lead 1. Thus, the mounting density of substrates 4 can be increased compared with conventional substrates 4 mounted with ZIP. Furthermore, when the taper angle betaon the surface of another package 3 is equalized with the oblique angle alpha, the mounting density of substrates can be further increased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、外部リードがパッケージの一方の側からのみ
出ている半導体装置に関し、特にこの種の半導体装置を
実装した複数の基板の実装密度の向上に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device in which external leads protrude only from one side of a package, and particularly relates to a mounting density of a plurality of boards on which this type of semiconductor device is mounted. Regarding the improvement of

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置、例えばジグザグインライン
パッケージ（以下ＺＩＰと称す）では、第４図の側面図
に示すように、外部リード１１の先端の方向Ａに対して
、パッケージ５の方向Ｂ′は平行になっている。Conventionally, in this type of semiconductor device, for example, a zigzag in-line package (hereinafter referred to as ZIP), as shown in the side view of FIG. 4, the direction B' of the package 5 is They are parallel.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ＺＩＰは基板に垂直に実装する半導体装置である。従っ
て、上述した従来のＺＩＰでは、同一基板内では非常に
高密実装できるが、第５図の側面図に示すように、基板
４同士を伺枚も並列に並べて装置に実装しようとすれば
、パッケージ５が垂直のためＺＩＰの高さが高い分だけ
、基板の実装密度は低くなる欠点がある。A ZIP is a semiconductor device that is mounted perpendicularly to a substrate. Therefore, with the conventional ZIP described above, extremely high-density packaging is possible within the same board, but if you try to mount the boards 4 in parallel in parallel, as shown in the side view of Fig. 5, the package Since ZIP 5 is vertical, there is a drawback that the mounting density of the board is low due to the high height of the ZIP.

〔問題点を解決す纂丸めの手段〕[Means of rounding up to solve problems]

本発明の半導体装置は、外部リードの先端方向に対して
パッケージを傾かせている。In the semiconductor device of the present invention, the package is tilted with respect to the direction of the tip of the external lead.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例の側面図である。第１図にお
いて、外部リード１の先端方向人に対して、パッケージ
２の方向Ｂは角度αだけ傾くように外部リードｌにおい
て曲げが行なわれている。FIG. 1 is a side view of one embodiment of the present invention. In FIG. 1, the external lead 1 is bent so that the direction B of the package 2 is inclined by an angle α with respect to the tip direction of the external lead 1.

このようにすると、第１図のＺＩＰを実装した基板を重
ねた状態を示す第３図の側面図のように、基板４の実装
密度は第４図に示す従来のＺＩＰを実装した基板４に比
べて高くなる。In this way, the mounting density of the board 4 is as shown in the side view of FIG. 3, which shows the state in which the boards mounted with the ZIP shown in FIG. It's more expensive than that.

第２図は本発明の他の実施例の側面図である。FIG. 2 is a side view of another embodiment of the invention.

第２図において、パッケージ３の上面のテーパー角度β
は、パッケージ３の傾きαと同じにしである。このよう
にすると、第１図に示した実施例を実装した基板よりも
更に基板の実装密度が高くなる利点がある。In FIG. 2, the taper angle β of the top surface of the package 3
is the same as the slope α of the package 3. This has the advantage that the mounting density of the board is higher than that of the board on which the embodiment shown in FIG. 1 is mounted.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、リードの先端の方向に対
してパッケージを傾けることによシ本発明の半導体装置
を実装した基板の実装密度を高くすることができる効果
があシ、シかして、パッケージの傾きの角度よシもバ、
ケージ上面のテーパ角度を大きくするか少なくとも同等
にすることによって、その効果を最大限に発揮させるこ
とができる。As explained above, the present invention has the effect of increasing the packaging density of a board on which the semiconductor device of the present invention is mounted by tilting the package with respect to the direction of the tip of the lead. Please check the angle of the package.
The effect can be maximized by increasing or at least equalizing the taper angle of the top surface of the cage.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例の側面図、第２図は本発明の
他の実施例の側面図、第３図は本発明のＺＩＰｔ−実装
した基板の実装密度を示すための側面図、第４図は従来
のＺＩＰを示す側面図、第５図は従来のＺＩＰｔ−実装
した基板の実装密度を示すための側面図である。 １．１１・・・・・・外部リード、２，３．５・・・・
・・パッケージ、４・・・・・・基板、Ａ・・・・・・
外部リード先端方向、Ｂ　’、　Ｂ／・・・・・・パッ
ケージ方向、α・・・・・・パッケージの傾き、β・・
・・・・パッケージの上面のテーパ角度。 箔１図　　　消２図 第３図FIG. 1 is a side view of one embodiment of the present invention, FIG. 2 is a side view of another embodiment of the present invention, and FIG. 3 is a side view showing the packaging density of the ZIPt-mounted board of the present invention. , FIG. 4 is a side view showing a conventional ZIP, and FIG. 5 is a side view showing the mounting density of a conventional ZIP-mounted board. 1.11...External lead, 2,3.5...
...Package, 4...Substrate, A...
External lead tip direction, B', B/...Package direction, α...Package inclination, β...
...Taper angle of the top surface of the package. Foil Figure 1 Eraser Figure 2 Figure 3

Claims (2)

【特許請求の範囲】[Claims] （１）外部リードがパッケージの一方の側からのみ出て
いる半導体装置において、前記外部リードの先端方向に
対してパッケージが傾いていることを特徴とする半導体
装置。(1) A semiconductor device in which an external lead protrudes from only one side of a package, wherein the package is inclined with respect to the direction of the tip of the external lead. （２）前記パッケージの傾きは、前記パッケージ上面の
テーパー角度に等しいかまたはそれ以下であることを特
徴とする特許請求の範囲第１項に記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the inclination of the package is equal to or less than the taper angle of the upper surface of the package.
JP30252086A 1986-12-17 1986-12-17 Semiconductor device Pending JPS63153849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30252086A JPS63153849A (en) 1986-12-17 1986-12-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30252086A JPS63153849A (en) 1986-12-17 1986-12-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS63153849A true JPS63153849A (en) 1988-06-27

Family

ID=17909952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30252086A Pending JPS63153849A (en) 1986-12-17 1986-12-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS63153849A (en)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992003035A1 (en) * 1990-08-01 1992-02-20 Staktek Corporation Ultra high density integrated circuit packages, method and apparatus
US5369058A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US5572065A (en) * 1992-06-26 1996-11-05 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
US6205654B1 (en) 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833862A (en) * 1981-08-24 1983-02-28 Sumitomo Electric Ind Ltd Mounting method and bending device for element lead wires

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833862A (en) * 1981-08-24 1983-02-28 Sumitomo Electric Ind Ltd Mounting method and bending device for element lead wires

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550711A (en) * 1990-08-01 1996-08-27 Staktek Corporation Ultra high density integrated circuit packages
WO1992003035A1 (en) * 1990-08-01 1992-02-20 Staktek Corporation Ultra high density integrated circuit packages, method and apparatus
US5367766A (en) * 1990-08-01 1994-11-29 Staktek Corporation Ultra high density integrated circuit packages method
US5377077A (en) * 1990-08-01 1994-12-27 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5420751A (en) * 1990-08-01 1995-05-30 Staktek Corporation Ultra high density modular integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
US5475920A (en) * 1990-08-01 1995-12-19 Burns; Carmen D. Method of assembling ultra high density integrated circuit packages
US5566051A (en) * 1990-08-01 1996-10-15 Staktek Corporation Ultra high density integrated circuit packages method and apparatus
US5448450A (en) * 1991-08-15 1995-09-05 Staktek Corporation Lead-on-chip integrated circuit apparatus
US5572065A (en) * 1992-06-26 1996-11-05 Staktek Corporation Hermetically sealed ceramic integrated circuit heat dissipating package
US5631193A (en) * 1992-12-11 1997-05-20 Staktek Corporation High density lead-on-package fabrication method
US5484959A (en) * 1992-12-11 1996-01-16 Staktek Corporation High density lead-on-package fabrication method and apparatus
US6205654B1 (en) 1992-12-11 2001-03-27 Staktek Group L.P. Method of manufacturing a surface mount package
US5864175A (en) * 1993-03-29 1999-01-26 Staktek Corporation Wrap-resistant ultra-thin integrated circuit package fabrication method
US5895232A (en) * 1993-03-29 1999-04-20 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5644161A (en) * 1993-03-29 1997-07-01 Staktek Corporation Ultra-high density warp-resistant memory module
US5801437A (en) * 1993-03-29 1998-09-01 Staktek Corporation Three-dimensional warp-resistant integrated circuit module method and apparatus
US5828125A (en) * 1993-03-29 1998-10-27 Staktek Corporation Ultra-high density warp-resistant memory module
US5843807A (en) * 1993-03-29 1998-12-01 Staktek Corporation Method of manufacturing an ultra-high density warp-resistant memory module
US5581121A (en) * 1993-03-29 1996-12-03 Staktek Corporation Warp-resistant ultra-thin integrated circuit package
US5369058A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US5369056A (en) * 1993-03-29 1994-11-29 Staktek Corporation Warp-resistent ultra-thin integrated circuit package fabrication method
US6194247B1 (en) 1993-03-29 2001-02-27 Staktek Group L.P. Warp-resistent ultra-thin integrated circuit package fabrication method
US6190939B1 (en) 1997-03-12 2001-02-20 Staktek Group L.P. Method of manufacturing a warp resistant thermally conductive circuit package
US5945732A (en) * 1997-03-12 1999-08-31 Staktek Corporation Apparatus and method of manufacturing a warp resistant thermally conductive integrated circuit package
US6572387B2 (en) 1999-09-24 2003-06-03 Staktek Group, L.P. Flexible circuit connector for stacked chip module
US6806120B2 (en) 2001-03-27 2004-10-19 Staktek Group, L.P. Contact member stacking system and method
US6576992B1 (en) 2001-10-26 2003-06-10 Staktek Group L.P. Chip scale stacking system and method

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