JPS63148350A - Control system for virtual storage of segment buffer memory - Google Patents

Abstract

PURPOSE:To put the whole of a graphic data base on a segment buffer, by making the capacity of a segment buffer memory look like larger than a mounted physical memory capacity. CONSTITUTION:A central arithmetic processing part 1 and a graphic drawing data processing part 3 are equipped with large logical address areas capable of storing the whole of the graphic data base, and when reference or write to the area is generated, an address is converted from a logical address to the physical address of a mounted segment buffer memory 2 by an address conversion mechanism 5. At this time, when no physical address exists, the content of the address with low priority is returned from the memory 2 to an auxiliary storage device 4 by a virtual storage control mechanism 6, and the content of an absent address is read out and written from the device 4 on the vacant area of the memory 2. Afterwards, interrupted reference or write operation is restarted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a segment buffer memory control method for a graphic figure ≠ data display processing device.

In particular, it relates to a virtual memory control method for segment buffer memory.

[Conventional technology]

Conventionally, regarding segment buffer memory control methods for graphic figure data display processing devices, "Hitachi Hyoron"
, Vol. 65, No. 3 (1985), pp. 51-56'
” and PA “Nikkei Electronics”, No. 374 (19
85), pages 145 to 154, a certain physical address area is allocated in advance to the segment buffer memory, and the central processing unit and the graphic processing unit can read, refer to, and write to the segment buffer memory. can be executed only at addresses within the address area.

[Problem that the invention seeks to solve]

According to the above-mentioned conventional technology, the capacity of the segment buffer memory is determined by the capacity of the installed physical memory. Therefore, in the case of an application field that requires a capacity of graphic figure data greater than the capacity of this physical memory, the entire graphic figure data is stored in the main memory or an auxiliary storage device such as a disk, and this graphic figure data is subdivided. This requires complicated control to store data in the segment buffer memory while converting data, which poses a problem of placing a heavy burden on programs in applied fields.

An object of the present invention is to make it appear as if the capacity of the segment buffer memory has a logically larger value than the installed physical memory capacity to an application program that requires a large graphic database capacity.
An object of the present invention is to provide a virtual storage control method for a segment buffer memory that allows the entire graphic database to be placed on a segment buffer with simple control.

Means for Solving Problem c] The present invention, which has achieved the above object, has a central processing unit 1. as shown in FIG. 1 (1). Main storage device 10° Auxiliary storage device W
14. Segment buffer memory for storing graphic figure data2. It is configured to include at least a graphic figure processing section 3 and a display device 8, and temporarily stores graphic figure data in the segment buffer memory 2, and the graphic figure processing section 3 reads out the graphic figure data in the segment buffer memory 2 and displays the In a device that performs display processing on the display device 8, the logical address of the segment buffer memory 2 is set to have a larger capacity range than the physical address of the segment buffer memory, and when the graphic figure processing unit 3 references or writes, the logical address is set to a physical address. An address translation mechanism 5 that converts the address into an address, and an auxiliary if the address translation mechanism 5 detects that the physical address corresponding to the reference or write logical address is absent in the segment buffer memory 2 when the address translation mechanism 5 converts the address. At the same time, the portion corresponding to the absent address is written from the storage device 4 to the segment buffer memory 2, and the contents of the address with a low priority are written from within the segment buffer memory 2 to the auxiliary memory table!
i! This is a virtual storage control system for a segment buffer memory characterized in that it is provided with a virtual storage control mechanism 6 for returning to the segment buffer memory.

[Effect]

As shown in FIG. 1 (II), the central processing unit 1 and the graphic figure data processing unit 3 have a large logical address area 12 that can store the entire figure database (logical address 12A of the central processing unit 1, graphic figure data processing unit 12
It has a logical address 12B of B. When a reference or write to this logical address area 12 occurs from either the processing unit 1 or 3, the address conversion mechanism 5 converts the logical address to the physical address B of the segment buffer memory 2 mounted (first (See Figure (II)C), if the physical address exists, the reference or write operation is performed as is, but if it does not exist, the address translation mechanism 5 detects this and notifies the virtual storage control mechanism 6 of this. Thereafter, the virtual memory control mechanism 6 returns the contents of addresses with lower priority than the segment buffer memory 2 to the auxiliary memory table @4, and transfers the contents of the addresses that were absent from the auxiliary memory to the empty area of the segment buffer memory. Read and write. After this, the suspended reference or write operation is resumed. In this way, the central processing unit 1
The graphic data processing unit 3 can handle a large graphic data area without being aware of the small actual capacity of the segment buffer memory 2.

〔Example〕

Hereinafter, one embodiment of the present invention will be briefly described with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

The graphic display processing device of the embodiment shown in FIG. 2 includes a central processing unit 1. Segment buffer memory 2. Graphic figure processing section 3. Magnetic disk device as auxiliary storage device @4. Address translation mechanism 5. Virtual memory control mechanism 6.
Logical address bus 7° Display 8 as display device
It is composed of: More specifically, the central processing unit 1 is connected to a graphic processing section 3, a magnetic disk device 4, and a virtual storage control mechanism 6 via a system bus 11, respectively. Further, the address translation mechanism 5 has an address translation table 14 and a valid bit V.
15, an area 16 for time data T, and an address selector 17. The physical address bus 9 of the segment buffer memory 2 is connected to the logical address bus 7 of the graphic graphic processing section 7 and the central processing section 1 via an address conversion table 14 and an address selector 17. Further, the segment buffer memory 2 and the graphic figure processing section 3 are connected by a data bus 20. The virtual memory control mechanism 6 and the address translation mechanism 5 including the address translation table 14 are connected by a valid bit V line 212, a time data T line 22, a physical page data line 18, and an address line 19. . The address selector 17 selects and outputs either the address from the logical address bus 7 or the address from the virtual storage control mechanism 6 as the address of the address conversion table 14. The virtual memory control mechanism 6 is composed of a microprocessor 23 and a bus control 24.

The operation of this embodiment configured as described above will be explained with reference to FIGS. 3 and 4.

When the central processing unit 1 and the graphics processing unit 3 access the segment buffer memory 2, the logical address is issued to the logical address bus 7. Normally, the address selector 17 selects the logical address bus 7 and outputs it. ing. The conversion operation from a logical address to a physical address by the address conversion table 14 is shown in FIGS. 3 and 4. As is clear from FIG. 4, the second half offset of the logical address (see FIG. 4(A)) becomes the second half of the physical address (see FIG. 4(C)).

The first half logical page of a logical address (see FIG. 4(A)) indicates one entry of the address translation table 14 corresponding to it (see FIG. 4 CB), and its contents are as follows:
As shown in FIG. 4 (CB), it consists of a physical page P, valid bits V1, and time data T. When the valid bit V is "1", it indicates that the value of the physical page P is valid, that is, the contents of the logical page L exist in the segment buffer memory 2, and when the valid bit V is at Opt, the value of the physical page P is valid. One time data T whose value is valid, that is, the contents of logical page L do not exist in the memory, is a valid physical page P.
When the valid bit V, which indicates the time when the value was written into the address translation table 14, is "1", the value of the physical page P in the address translation table 14 becomes the first half of the physical address as it is. When the valid bit V is "0", the virtual memory control mechanism 6 detects this, the microprocessor 23 and the bus control unit 24 operate, and perform the operations shown in the operation flow of the virtual memory control mechanism 6 in FIG. In other words, in FIG. 3, when the valid bit V is determined to be "0" in step 301 (step 301), the reference to the segment buffer memory 2 and the 2I inclusion process are temporarily interrupted and the process is executed in step 302.
), writes the contents of the corresponding logical page L from the magnetic disk to the segment buffer memory 2, and writes necessary information to the corresponding entry in the address conversion table 14, and then resumes processing. Specifically, before writing the contents of the necessary logical page L from the magnetic disk device 4 to the segment buffer memory 2, it is first checked whether there is an empty page in the segment buffer memory 2 (step 303).
, if so, select one of them (step 304).
, if there is no page, the page with low priority is transferred to magnetic disk device 4.
You need to make this a free page after expelling it to
Step 305). There are various processing methods for selecting pages with low priority, but here, pages with early time data T are used. After that, the contents of the corresponding logical page P are written from the magnetic disk device w14 to the empty page of the segment buffer memory 2 (step 306), and then the contents of the physical page P
and time data T to the address conversion table 14,
The valid bit V is set to "1" (step 307), and the post-processing is restarted (step 308).

According to this embodiment, access from the central processing unit 1 and the graphic figure processing unit 3 to the segment buffer memory 2 is possible regardless of the capacity of the installed segment buffer memory 2, which has a logically larger capacity. It can be treated as such.

Further, according to this embodiment, even in fields where it is necessary to handle large-capacity graphic data such as maps and LSIR meters, the graphic display processing device can exceed the capacity limit of the segment buffer memory 2 installed. The central processing unit 1 and the graphic figure processing unit 2 can handle this as if there is a segment buffer memory 2 with a logically large capacity, and therefore the application program does not have to carry out subdivision control of figure data, thereby reducing the burden. becomes lighter.

〔Effect of the invention〕

As described above, according to the present invention, the segment buffer memory capacity is made to appear to have a logically larger value than the installed physical memory capacity for an application program that requires a large graphics database capacity. This has the effect of significantly reducing the burden on application programs.

[Brief explanation of the drawing]

Figures 1 (1) and (II) are block diagrams shown for detailed explanation of the present invention, Figure 2 is a block diagram showing an embodiment of the present invention, and Figure 3 is a block diagram of an embodiment of the present invention. A flowchart is shown to explain the operation, and FIG. 4 is an explanatory diagram shown to explain the same operation. DESCRIPTION OF SYMBOLS 1... Central processing unit, 2... Segment buffer memory, 3... Graphic figure processing unit, 4... Magnetic disk device, 5... Address conversion mechanism, 6...
Virtual memory control mechanism, 7... logical address bus. Agent Patent Attorney Hashinuma'''Tatsu de 4, no-!! 2 eyes 4 solids

Claims (1)

[Claims] 1. Consisting of at least a central processing unit, a main storage device, an auxiliary storage device, a segment buffer memory for storing graphic figure data, a graphic figure processing unit, and a display device, and temporarily stores graphic figure data in the segment buffer memory. In the device in which the graphic figure processing unit reads graphic figure data in the segment buffer memory and displays it on the display device, the logical address of the segment buffer memory has a larger capacity range than the physical address of the segment buffer memory, an address translation mechanism that converts a logical address into a physical address when the graphic figure processing unit references or writes; and a physical address that corresponds to the referenced or written logical address when the address translation mechanism converts the address is stored in the segment buffer memory. If the address translation mechanism detects that the address is absent, the part corresponding to the absent address is written from the auxiliary storage device to the segment buffer memory, and the contents of the address with a lower priority from within the segment buffer memory are written to the auxiliary storage device instead. 1. A virtual memory control method for a segment buffer memory, comprising: a virtual memory control mechanism for returning data.