JPS6314522A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To attain the phase control with high accuracy by varying the amplitude of a pulse signal with a prescribed period in response to a control signal and comparing the phase between an input signal and an output signal being the conversion of the varied signal into a continuous signal. CONSTITUTION:The pulse signal of a prescribed period generated from a pulse generating circuit 5 is inputted to an amplitude control circuit 19, where the amplitude of the pulse signal is varied in response to the control signal from a loop filter 3. The output of the circuit 19 is inputted to an interpolation circuit 21, which converts the input signal into a timewise continuous signal and the result is outputted to a terminal 17. Simultaneously, the phase of the output signal of the circuit 21 and the phase of the input signal from the terminal 15 are compared by a phase comparator 23. The output of the circuit 23 is averaged by the loop filter 3, a minute variation is eliminated, the result is outputted to the circuit 19 from the filter 3 as a control signal to vary the amplitude of the pulse signal from the circuit 5. Thus, the phase control with high accuracy is attained without increasing the output frequency of the circuit 5.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a phase synchronization circuit used in a digital transmission device, and in particular, to a phase synchronization circuit used in a digital transmission device. This invention relates to a phase locked circuit that can perform control.

(Prior Art) Generally, in digital transmission devices, a phase synchronized circuit is widely used as a timing signal regeneration circuit of a receiving device. FIG. 9 is a block diagram showing the configuration of such a conventional phase synchronization circuit.

As shown in the figure, this phase synchronization circuit includes a binary quantization phase comparison circuit 1, a loop filter 3, a pulse generation circuit 5,
It consists of a pulse addition/removal circuit 7 and a frequency dividing circuit 9, and the loop filter 3 consists of a bidirectional counter 11 and an OR gate 13.

The input signal sent from the input terminal 15 and the output signal of the frequency dividing circuit 9 are panned to the binary quantization phase comparator circuit 1.
The phase difference between these signals is detected.

When the phase of the input signal is ahead of the phase of the output signal, the signal is input to the up terminal UP of the bidirectional counter 11, and when the phase of the input signal is behind the phase of the input signal or the phase of the output signal, the signal is input to the down terminal DOWN. A signal is input. This loop filter 3 averages the output signal of the binary quantization phase comparison circuit 1 and removes fine fluctuations in the output of the binary quantization phase comparison circuit 1 due to noise or the like.

In other words, the contents of the 2N+ stage bidirectional counter 11 constituting this loop filter 3 are set to N1 in the initial state, and each time a signal is input to the up terminal UP, the contents of the bidirectional counter 11 increases by 1 and continues counting. number is 2
When it becomes N+, one round of pulses is output from the advance terminal AD. This pulse signal is input to the pulse addition/removal circuit 7 and is also input to the reset terminal RE of the bidirectional counter 11 via the OR gate 13.
The content of is reset to N1. Also down terminal DOW
Each time a signal is input to N, the contents of the bidirectional counter 11 are decremented by 1, and when the count reaches 0, one pulse is output from the retard terminal RET. This pulse signal is input to the pulse addition/removal circuit 7 and is also input to the reset terminal RE via the OR gate 13 to reset the contents of the bidirectional counter 11 to N+.

The pulse generating circuit 5 generates a pulse signal with a constant period.

When a pulse is output from the retard terminal RET of the bidirectional counter 11, the pulse addition/removal circuit 7 removes one pulse from the pulse train generated from the pulse generation circuit 5 and outputs it to the frequency dividing circuit 9. , also advance terminal A
When a pulse is output from D, one pulse is added to the pulse train output from the pulse generating circuit 5 and output to the frequency dividing circuit 9. The frequency dividing circuit 9 divides the frequency of the input pulse train by 1/R. That is, when there is an output at the retard terminal RET of the bidirectional counter 11, one pulse is removed from the pulse train output from the pulse generation circuit 5, and the frequency is divided by 1/R by the frequency dividing circuit 9, so that the pulse is divided. The output of the circuit 9 is delayed in phase by 360'/R. On the contrary, when there is an output from the advance circuit AD, the phase of the output from the frequency dividing circuit 9 is advanced by 360°/R. The output of this frequency dividing circuit 9 is supplied to an output terminal 17 and a binary quantization phase comparison circuit 1. The signal output from the output terminal 17 becomes the output signal of this phase locked circuit.

(Problems to be Solved by the Invention) As described above, in the conventional phase-locked circuit, the frequency of the pulse generated by the pulse generation circuit 5 is R times the frequency of the input signal input from the input terminal 15. The amount of phase that is necessary and can be changed by one phase control is 360'/R. For example, when R=16, the phase control amount is 360°/16=22.5°, which is 2
In order to perform phase control with a viscosity of 2.5°, input signal 1
A pulse generating circuit 5 with six times the frequency is required.

Incidentally, in general, an identification circuit for digital signal transmission requires a highly accurate timing signal.

Therefore, the output of the phase synchronized circuit used for the timing signal is required to have a high precision b. If you need a high-precision output No. 18, increase the division ratio R,
The frequency of the pulse generating circuit 5 must be increased.

In other words, in the conventional phase-locked circuit, in order to obtain a highly accurate output signal, it is necessary to operate the circuit using a commercial pulse of a high frequency, which poses a problem in that the configuration of the circuit becomes extremely difficult.

The present invention has been made in view of these problems, and its purpose is to provide a phase synchronization circuit that can perform highly accurate phase control without increasing the frequency of the pulse generation circuit. be.

[Structure of the Invention] (Means for Solving the Problems) To achieve the above object, the present invention provides a pulse generation circuit that generates a pulse signal of a constant period, and a pulse generation circuit that varies the amplitude of the pulse signal in accordance with a control signal. an interpolation circuit that converts the output of the amplitude control circuit into a temporally continuous signal, and an interpolation circuit that outputs the output signal of the interpolation circuit from an output terminal and compares the phase of this output signal with an input signal. It is characterized by comprising a phase comparison circuit and a loop filter that outputs the control signal that suppresses fluctuations in the output of the phase comparison circuit.

(Function) In the phase locked circuit of the present invention, the pulse signal generated from the pulse generation circuit is varied by the amplitude control circuit, and by adjusting this variation, it is possible to perform adjustment control of a predetermined phase amount. .

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of a phase locked circuit according to an embodiment of the present invention. As shown in the figure, this phase synchronized circuit includes a pulse generation circuit 5 that generates a pulse signal of a constant period, an amplitude control circuit 19 that varies the amplitude of the pulse signal according to the output of the loop filter 3, and An interpolation circuit 2 that converts the output of the control circuit 19 into a temporally continuous signal.
1, a phase comparison circuit 23 that outputs the output signal of the interpolation circuit 21 from the output terminal 17 and compares the phase of this output signal with the input signal, and a loop filter 3 that suppresses fluctuations in the output of the phase comparison circuit 23. and.

FIG. 2 is a block diagram showing a more specific configuration of this phase synchronization circuit, and elements that perform the same functions as those of the conventional example shown in FIG. 9 are given the same numbers to avoid redundant explanation. As shown in the figure, this phase locked circuit includes a binary phase comparison circuit 1, a loop filter 3 consisting of a bidirectional counter 11 and an OR gate 13, and a pulse generation circuit 5.
, an amplitude control circuit 19, and an interpolation circuit 21. The amplitude control a11 circuit 19 includes an N2-stage bidirectional counter 23, an N2-stage counter 25, an adder circuit 27, and a lead-in ROM (SIN).
- Consists of ROM>29. The interpolation circuit 21 includes a digital-to-analog conversion circuit (DA conversion circuit) 31, an analog filter 33, and a slider 35.

The frequency of the pulse generating circuit 5 is four times the frequency of the input signal input from the input terminal 15.

As shown in Fig. 3, the signature ROM 29 has one period
The amplitude value at each point when divided into six is stored in binary numbers, and one cycle of this sine ROM corresponds to one cycle of the input signal.

Next, the operation of this embodiment will be explained.

FIG. 4 is a waveform diagram of signals at each part. Figure 4 (a
) indicates a pulse signal generated by the pulse generating circuit 5. The frequency of the pulses generated by this pulse generating circuit 5 is four times the frequency of the input signal. The pulses generated in the pulse generation I[path 5 are multiplied by 4 by the force 1 kunta 25. That is, each time a pulse arrives from the pulse generating circuit 5, the counter 25 increases its contents by 4, and O14, 8.
, 12, O14, . . . The initial value of the bidirectional counter 23 is ii O! It is set to l, and when there is an output from the retard terminal REV, it counts down, and when there is a horn coming from the advance terminal AD, it starts counting down.
Tsupu J゛ru. The outputs of the bidirectional counter 23 and the counter 25 are added together in a tightening circuit 27 and input to the rein ROM 29.

For example, if the content of the bidirectional counter 23 is O, the contents of the counter 25 are O14, 8, 12, O14, etc.
This value passes through the adder circuit 27 and is input to the sign ROM 29.

The value of this signature ROM 29 is then read. In other words, in this case, as shown in Fig. 4(b), υinrom2
Since the contents of O14, 8, and 12 of 9 are read, the output of the signature ROM 29 is as shown in FIG. 4(b).

When there is an output from the advance terminal AI') and the content of the bidirectional counter 23 becomes 1, the adder circuit 27 outputs the values 1, 5, 9, 13, . . . At 29, the contents corresponding to these values are read. In other words, in case 1, the value of the sign ROM 29 corresponding to 1.5.9.13 is read, so the output of the sign ROM 29 is as shown in FIG. 4(C).

Conversely, when there is an output from the retard terminal RET and the content of the bidirectional counter 23 is -1, the output of the adder circuit 27 becomes 15.3.7.11.15, etc., and the sign ROM 29 outputs these values. The content corresponding to is read. In this case, the output of the lead-in ROM 29 will be as shown in FIG. 4(d).

Roughly speaking, in the case of Fig. 4(C), the advance terminal A
When there is an output from D, the content of the bidirectional counter 23 becomes 2, and the output of the adder circuit 27 becomes 2.6.10.14.2, etc.
・The phase advances further. In the case of FIG. 4(d), when there is an output from the retard terminal RET, the content of the bidirectional counter 23 becomes -2, and the output of the Korean circuit 27 becomes '14.2.6.10114, . . . Zara(ko)
η phase is delayed.

The output of the Zine ROM 29 generated in this way is DA
The signal is input to the conversion circuit 31 and exchanged into an analog signal. In other words, signals such as those shown by the solid nine curves in FIGS. 4(b) to 4(d) are inputted.

This signal is input to an analog filter 33, and the signal having its amplitude fraction interpolated is also input to a slicer 35.

This slicer 35 performs the slicing operation at the slice levels shown in FIGS. 4(b) to 4(d), so the slice 1j35 generates rectangular waves shown by dotted lines in FIGS. 4(1) to 4(d). is obtained, and in the case of (C) and (d) of the same figure, 36
A J-shaped wave with a phase shift of 0'/16 = 22.5 degrees is obtained.

In this way, the pulse generation circuit 5 with a frequency four times that of the input signal
In the conventional example shown in Fig. 9, when using 360'/
Although phase control could only be performed with an accuracy of 4=90', in this embodiment, phase control can be performed with an accuracy of 360°/1B=22.5°.

This corresponds to the accuracy when a pulse generating circuit 5 having a frequency 16 times that of the input signal is used in a conventional circuit. Therefore, in the conventional circuit, the precision phase control obtained when using the high frequency pulse generation circuit 5 can be achieved by using the low frequency pulse generation circuit 5 in this circuit. It is possible. In other words, if the phase-locked circuit of this embodiment is used as a timing signal regeneration circuit of a receiving device of a digital transmission device, it becomes possible to identify high viscosity, and even when the input signal frequency is high, it is not necessary to use a pulse generation circuit of such a high frequency. Since this is not necessary, the circuit configuration becomes easy.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a block diagram of the configuration of the phase synchronization circuit of this embodiment. Elements that perform the same functions as those of the first embodiment described above are given the same numbers to avoid redundant explanation. In this embodiment, the output of the loop filter 3 is connected to the switch control circuit 3.
7, the switch control circuit 37 controls the attenuator 39, and the output of the attenuator 39 is input to the analog filter 41.

The switch control circuit 37 operates four switches SW1, SW2, SW3, and S of the attenuator 39 in response to a signal sent from the advance terminal AD or the retard terminal 〒RET.
Control W4)1.

Here, A, B, C, and D represent "011 or '1'°, and are designated as 1, and A or I II indicates that the switch SWI is connected to the pulse generation circuit 5, and A is "01".
1 indicates a state in which the switch SWI is connected to the ground side.

Similarly, 011 or 1 "1" of 13 and cJ D indicates the connection state of each switch S"A/2, SW3, SW4 to the pulse generation circuit 5 or the ground example. From the pulse generation circuit 5 to this attenuator 39 The input voltage ein is input to the amplifier circuit M, and the output voltage e Out is output to the amplifier circuit M.
Then e our-e *n (to/1G1B/8
+C/4-4-D/2) A-D is “1” or “O”
There is a relationship called ゛′.

The switch control circuit 37 controls each switch SWI, SW2,
Controls SW3 and SW4, and each switch SW1-S
Depending on whether W4 is turned on or off, the output voltages shown in the following table are obtained.

In this way, the switch SW1 is controlled by the switch control circuit 37.
~eout=o by controlling SW4.

1/16e 1n12/16e in,...15/1
16 outputs of 6 e in can be obtained. If the output of the switch control circuit 37 and the gain 17 of the attenuator 39 are determined as shown in FIG. 6, a discrete triangular wave having one cycle divided into 16 can be obtained.

Next, the operation of this embodiment will be explained.

FIG. 7 shows waveforms of signals at various parts in this embodiment.

FIG. 7(a) shows a pulse train generated from the pulse generating circuit 5. The switch control circuit 37 controls the switches SWI to SW.
4 and determines the gain of the attenuator 39 each time a pulse is output from the pulse generating circuit 5. For example, Figure 7 (
In b), the gain of the attenuator 39 at the time of outputting the first pulse is the same as 11011 in the figure, and the gain of the attenuator 39 is t at the time of outputting the next pulse.
This is exactly the same figure as the 4th page. In this way, 1
After the converted voltage is converted into a smooth continuous waveform by an analog filter 41, a rectangular wave as shown by a dotted line is obtained by a liner 35.

In FIG. 7(C), when the first pulse is output, the gain of the attenuator 39 is set to "1" in the figure, and when the next pulse is output, the gain of the attenuator 39 is set to "5°" in the figure. By performing such control, the position (eyes 2) can be reduced compared to Fig. 7(b).
The problem is that it advances by 2.5 degrees.

Furthermore, the present invention can be modified in various ways within the scope of its technical concept. For example, in the first embodiment, the pulse generating circuit 5 generates a pulse signal having a frequency four times that of the input signal, but it may generate pulses having a different frequency.

In addition, in the first embodiment, one period is one in the sign ROM 29.
The value when divided into 6 was memorized, but 32 division and 6
This is possible by storing the values when dividing into four. In the former case, it is possible to perform phase control with an accuracy of 360'/32=11.25°, and in the case of one multiplier, 360'/64=5.25°.

Furthermore, the attenuator 39 is provided with a larger number of switches than the four switches in the second embodiment, thereby making it possible to perform phase control with higher precision.

Further, in both embodiments, as the phase comparison circuit 23, a phase comparison circuit of a type that detects a phase advance product and a phase delay amount may be used instead of the binary encoding phase comparison circuit 1. Further, as the loop filter 3, the well-known N t shown in FIG.
A serore M filter can also be used.

[Effects of the Invention] As described above in detail, according to the present invention, highly accurate phase control can be performed without increasing the frequency of the pulse generation circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit (4 components) of the present invention;
The figure is a configuration block diagram of a phase synchronization circuit according to the first embodiment of the present invention, and FIG. 3 is an explanatory diagram showing the contents of the sign ROM 29.
FIG. 4 is a waveform diagram of signals at each part in the first embodiment, and FIG.
6 is an explanatory diagram showing the gain of the attenuator 39, FIG. 7 is a waveform diagram of signals at various parts of the second embodiment, and FIG. The figure is a circuit diagram showing another configuration of the loop filter, and FIG. 9 is a configuration block diagram of a conventional phase locked circuit. 3... Loop filter 5... One pulse generation circuit... (Width width control circuit 21... Intercepting circuit 23... Phase Comparative Circuit Applicant Toshiba Corporation Patent Attorney Satoshi Suyama - Figure 4 1 to Figure 5 Figure 6 Figure 5 Tube Figure 7 and Figure 8 Figure 3

Claims (1)

[Claims] A pulse generation circuit that generates a pulse signal with a constant period; an amplitude control circuit that varies the amplitude of the pulse signal according to a control signal; an interpolation circuit that converts the output signal into a signal; a phase comparison circuit that outputs the output signal of the interpolation circuit from an output terminal and compares the phase of the output signal with an input signal; and the phase comparison circuit that suppresses fluctuations in the output of the phase comparison circuit. A phase synchronized circuit comprising: a loop filter that outputs a control signal;