JPS6314391B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a video signal processing device suitable for information processing using an electronic computer.

In recent years, when developing various automatic devices, it has become essential to use devices that can recognize positions and shapes, so-called visual information input devices. Therefore, the industrial television camera (hereinafter abbreviated as ITV camera), which can easily obtain a large amount of information with high precision, has been used as the above-mentioned visual information input device.
is the most commonly used. However, the above
ITV cameras handle extremely large amounts of information and at very high speeds, so when processing the obtained information on an information processing device such as a computer, it must be processed via high-speed, large-capacity buffer memory, or multiple frames must be processed. In short, it took a relatively long time to enter information. This has resulted in inconveniences, such as the devices becoming expensive or unable to respond to rapidly changing information.

This invention was made with attention to the above circumstances, and its purpose is to be able to process large-capacity video signals obtained at high speed in real time, without damaging the original video signal. An object of the present invention is to realize and provide a video signal processing device which can be processed faithfully and input to a subsequent device, and which is simple in configuration and inexpensive.

In addition, the outline of the present invention is to first digitize a high-speed video signal to obtain video information of a predetermined number of pixels, and then digitize a plurality of adjacent pixels in the horizontal scanning direction and vertical scanning direction of the video. The features of the video information are extracted and the information is compressed. Then, the compressed video information obtained by the above compression is selectively converted by low-speed conversion in units of horizontal scanning lines, for example, for each scanning line, within a period until the next compressed video information is obtained. It is being input to an information processing device.

Therefore, by compressing and handling high-speed video signals as described above and inputting information at low speed during the blank period created by this compression, high-speed video signals can be stored in large-capacity buffer memory or It is possible to input information to an information processing device in real time without using a large-scale high-speed computer, thereby making it possible to realize and provide a video signal processing device with a simple configuration and low cost.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic configuration diagram of a video signal processing apparatus in the same embodiment, and numeral 1 in the figure indicates an ITV camera. This ITV camera 1 outputs a video signal ES obtained by performing main scanning in the horizontal direction and sub-scanning in the vertical direction with respect to an object to be imaged, and also outputs a vertical synchronization signal VD that controls the scanning timing of this video signal ES. and horizontal synchronization signal HD respectively.

The above video signal ES is binarized by comparator 2,
In other words, after being digitized, the data is serially supplied to a 3-bit shift register 3 and sequentially shifted. Shifted video information (binarized video signal)
are outputted in parallel and subjected to majority decision processing for every 3 bits by the first majority logic circuit 4. That is, the first majority logic circuit 4 divides the video information into three parts in the scanning line direction, that is, in the horizontal direction.
The video information is compressed by majority voting using bits as units. Therefore, if the density of the above video information is, for example, 400 pixels per scanning line, then
Video information AS1 compressed to 136 pixels is obtained. The compressed video information AS1 is then serially supplied to the shift register circuit 5 and sequentially shifted. This shift register circuit 5 consists of two 136-bit shift registers 5a and 5b connected in series, and shifts the video information AS1 and temporarily stores the video information AS1 for two scanning lines. Each of these stored video information AS1 is
Together with the video information AS1 obtained in the next scan, that is, the third scan, each bit is supplied to the second majority logic circuit 6 and subjected to majority decision processing.
That is, the second majority logic circuit 6 performs majority decision processing on each of the three scanning lines of video information AS1 bit by bit in the vertical scanning direction to obtain video information AS2 compressed in the vertical scanning direction. As a result, together with the compression in the scanning line direction (horizontal direction) mentioned above, compressed video information (136×166 pixels) AS2 in which 9 pixels are one unit is obtained. In this way, the obtained compressed video information AS2
are serially supplied to a 136-bit shift register 7 for shifting, and then output in parallel to a 136-bit buffer register 8 for temporary storage. The stored compressed video information AS2 is read out in accordance with the readout control signal WS generated by the input control circuit 9, and is input to an information processing device such as a microcomputer (not shown). The input control circuit 9 controls the input of the compressed video information AS3 read from the buffer register 8 to the information processing device, and receives an input synchronization signal IS having the same period as the readout control signal WS. Occur.

Next, the operation of the device will be explained with reference to FIG. Video signal obtained by ITV camera 1
The ES is binarized by the comparator 2 based on a sampling frequency of, for example, 7.16 MHz, which corresponds to the horizontal resolution of the ITV camera 1, resulting in video information of approximately 400 pixels per scanning line. This video information is serially input to a 3-bit shift register 3 and shifted in accordance with the sampling frequency. The shifted video information is output to the first majority logic circuit 4 in units of 3 bits for each scanning line,
This first majority logic circuit 4 performs majority decision processing. For example, the video information "011" is "1"
become. As a result, the above 400-pixel video information is converted to approximately 136-pixel compressed video information (Figure 2 AS1).
becomes. This video information AS1 is serially shifted into the shift register circuit 5, and 136
They are temporarily stored in bit shift registers 5a and 5b, respectively. The stored video information AS1 for two scanning lines is then output bit by bit in parallel to the second majority logic circuit 6 together with the compressed video information corresponding to the next third scanning line. Then, in the second majority logic circuit 6, majority decision processing is performed for each of the three bits,
The video information is compressed to 1/3 times the video signal in the vertical scanning direction (AS2 in FIG. 3). Therefore,
This compressed video information AS2 becomes video information in which nine pixels worth of video information is compressed into one pixel by the compression in the scanning line direction by the first majority logic circuit 4 described above. Compressed video information obtained in this way
AS2 is serially shifted into the 136-bit shift register 7, and outputted in parallel to the buffer register 8 when the input of information corresponding to one scanning line (136 bits) is completed. This 136-bit compressed video information AS2 is stored in the buffer register 8.
After being temporarily stored in FIG. 2 AS3, it is read out during a period T during which the video signal ES corresponding to the next three scanning line segments is being compressed, and is input to an information processing device (not shown). . Therefore,
The frequency of the read control signal WS and the input control signal IS that control the read operation of the compressed video information AS3 and the input operation to the information processing device is 1/9 of the sampling frequency (7.16 MHz) of the video signal ES. It's going to be a good thing.
As a result, the frequency of the readout control signal WS and input control signal IS is 0.79MHz (per pixel).
It can be set to about 1.27μsec). This value is fast enough to input data even to an information processing device that requires a long input time, such as a microcomputer, so the high-speed video signal ES obtained by ITV camera 1 is is input into the information processing device. Furthermore, the above video signal ES
Since the input operation to the information processing device is performed using the majority logic circuits 4 and 6 and a group of shift registers, there is no need for expensive elements such as large-capacity buffer memories as in conventional devices, and the device can be constructed at a low cost. It will be a simple one.

That is, according to the present invention, video information (digitized video signal) is compressed into one pixel by performing majority voting processing in units of three pixels in each of the scanning line direction and the vertical scanning direction,
By inputting this compressed video information to the information processing device within the scanning time of three scanning lines, the time is approximately 1/9th that of inputting the digitized video signal directly to the information processing device. The input operation of video information can be performed, and as a result, high-speed video information can be input in real time to an information processing device that requires a long input time. Moreover, since the majority decision process is used, the original video signal can be compressed without much damage, and the above operation is realized by a simple circuit group consisting of a majority logic circuit, a shift register, etc. It is possible to provide an apparatus that is extremely simple in configuration and handling, and is inexpensive, compared to the case where a large-capacity, high-speed buffer memory or a large-scale computer is used.

By the way, in the above embodiment, the compressed video information AS
3 into the information input device, information corresponding to the entire screen area is inputted unconditionally. However, in general, information corresponding to the entire area of the screen is not necessarily required, but only information corresponding to a predetermined area is often required. Therefore, a method can be considered in which a required area on the screen is designated and the compressed video information AS3 is input to the information processing apparatus based on this area. By using such a method, the memory area of the information processing device can be used effectively, thereby achieving great effects such as increasing the information processing capacity.

Hereinafter, one means for specifying the area will be described with reference to the drawings. FIG. 3 is a schematic diagram of the area designation circuit. In the figure, 11 to 14 are the first to fourth
The counter circuits shown in FIG. Of these counter circuits 11 to 14, the first and second counter circuits 11 and 12 both designate an area in the vertical scanning direction, and as shown in FIG. and the vertical scanning direction component Sy of the specified area K are respectively set. That is, the first counter circuit 11
starts counting the horizontal synchronizing signal HD by supplying the vertical synchronizing signal VD to the preset input terminal Pr, and after counting the number corresponding to the blank area Y in FIG. 4 mentioned earlier, the first flip-flop ( The circuit 15 (hereinafter abbreviated as FF) is set. By setting the first FF circuit 15, the second counter circuit 12 starts counting the horizontal synchronizing signal HD, and after counting the number corresponding to Sy in FIG. Reset. Therefore, when the first FF circuit 15 is set,
In other words, the period indicated by TSy in FIG. 5F1 becomes the vertical scanning direction component Sy of the specified area K mentioned above.

On the other hand, the third and fourth counter circuits 13
and 14 are for setting the horizontal scanning direction component SX of the blank area X and designated area K in the scanning line direction (horizontal scanning direction) shown in FIG. It is now operational in TSy. That is, the third counter circuit 13 receives the count input signal SD during the set period TSy of the first FF circuit 15.
When the control pulse signal HDC is supplied to the preset input terminal Pr, counting of the count input signal SD is started. At this time, the counting input signal SD has the same frequency as the bit frequency of the compressed video information AS1 subjected to the majority voting process in the above embodiment, that is, the value obtained by dividing the digitization (sampling) frequency of the video signal ES by three. are doing. Therefore, the third counter circuit 13 counts the count input signal SD by the number of bits (the number of pixels compressed to 1/3) corresponding to X in FIG. 2 FF
Set the circuit 16. This second FF circuit 16
By setting , the fourth counter circuit 14 starts counting the count input signal SD, and
After counting the number corresponding to the horizontal scanning direction component Sx, the second FF circuit 16 is reset.
Therefore, the set period of the second FF circuit 16 (TSx shown in FIG. 5 F2) is within the specified area K.
is the horizontal scanning direction component Sx. By the way, the control pulse signal HDC for presetting the third and fourth counter circuits 13 and 14 is obtained by dividing the horizontal synchronizing signal HD by three by a frequency divider circuit 17 and a one-shot multivibrator (MM) 18. It has become a common thing. This is to synchronize the compressed video information AS2, which is compressed into one scanning line by majority voting every three scanning lines.
As a result, the second FF circuit 16 generates a "HIGH" level set output signal F2 once every three scans, as shown in FIG.

The set output signal F2 of the second FF circuit 16 is then given to an information processing device (not shown), thereby controlling the input of the compressed video information AS2 to the information processing device. At this time, the input of the compressed video information AS2 is the count input signal SD and the count input signal SD.
This is performed in synchronization with the synchronization signal SDC which is gate-controlled in accordance with the signal level of the set output signal F2 of the FF circuit 16. That is, the count input signal SD is applied to the buffer register 8 (FIG. 1) described in the embodiment, and the compressed video information AS2 is read out in synchronization with the count input signal SD. and,
This read compressed video information AS3 is input to the information processing device in accordance with the set output signal F2 and synchronization signal SDC mentioned above. Therefore, the information processing device receives the read compressed video information.
Of AS3, compressed video information corresponding to the "HIGH" level period of the set output signal F2
Only the video information corresponding to AS3, that is, the designated area K in FIG. 4, is input. In addition, to specify the area,
This can be done freely by setting count values for each of the counter circuits 11 to 14 in advance from the information processing device.

According to such a device, it is possible to selectively input only the video information of a necessary area out of the video information for one screen to the information processing device. As a result, the memory area of the information processing device can be used more efficiently, and the information processing ability can be improved. In addition, in this implementation, the input of video information to the information processing device was performed in synchronization with the count input signal SD, which had an input time of 1/3 of the digitization (sampling) synchronization of the video signal. Video information can be input to the information processing device at relatively low speed.

In addition, if you want to set the input time to be longer, input the video information read from the buffer register in series to the shift register and input it to the information processing device every 3 bits, for example, to increase the input speed. The video signal digitization period can be 1/9 times that of the video signal digitization period described above, and video information can be input in approximately the same input time as in the above embodiment.

Note that the compression of the video signal by the majority logic circuit is not limited to the 3×3 pixel unit as in the above embodiment, and other pixel units such as 5×5 pixel unit may be adopted.

As detailed above, according to the present invention, a high-speed video signal is digitized to obtain video information of a predetermined number of pixels, and this video information is compressed to selectively perform low-speed and By inputting information into the system, it is possible to realize and provide a video signal processing device that can process large-capacity video signals obtained at high speed in real time, and that is simple in configuration and inexpensive. .

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a video signal processing device according to an embodiment of the present invention, FIG. 2 is a timing diagram used to explain the operation of the embodiment, and FIG. 3 is a schematic diagram showing a modification of the above embodiment. , FIG. 4, and FIG. 5 are diagrams used to explain the modified example.
The figure is a schematic diagram of the screen, and FIG. 5 is a timing diagram. 1...ITV camera, 2...Comparator, 3,
5, 7...Shift register, 4,6...Majority logic circuit, 8...Buffer register, 9...Input control circuit, 11,12,13,14...Counter circuit, 15,16...Flip-flop circuit , 17
...Three frequency divider circuit, 18...One shot multivibrator, ES...Video signal, VD...Vertical synchronization signal, HD...Horizontal synchronization signal, AS1, AS2, AS
3...Compressed video information, IS...Input control signal,
WS...readout control signal, SD...counting input signal.

Claims (1)

[Claims] 1. A comparator that binarizes a video signal obtained by horizontal scanning and vertical scanning at regular time intervals and outputs a binarized video signal indicating binarized pixels, and a binarized video output from this comparator. A first unit in which a plurality of binarized pixels that are consecutive in the horizontal scanning direction and are an odd number are input as a unit.
a first shift register that outputs a register signal; and a first compression circuit that inputs the first register signal and performs majority voting processing for each unit of pixels to indicate binarized pixels compressed in the horizontal scanning direction. a first majority logic circuit that outputs a compressed video signal, and a horizontal circuit that inputs the first compressed video signal and stores the first compressed video signal for each horizontal scanning line; an even number of second shift registers having a number of stages equal to the number of pixels per scanning line, a second register signal output from the final stage of the even number of second shift registers, and the first compressed video Signals are input simultaneously, and a plurality of odd-numbered binarized pixels input at the same time are subjected to majority voting processing as one unit, and a second compressed video signal indicating the binarized pixels compressed in the vertical scanning direction is output. a second majority logic circuit, a buffer register for inputting the second compressed video signal, temporarily storing it for each horizontal scanning line, and outputting the same in series; A video signal processing device comprising: a control circuit that outputs an output control signal to the buffer register for sufficiently lengthening the output time of the second compressed video signal.