JPS63143851A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63143851A JPS63143851A JP29310286A JP29310286A JPS63143851A JP S63143851 A JPS63143851 A JP S63143851A JP 29310286 A JP29310286 A JP 29310286A JP 29310286 A JP29310286 A JP 29310286A JP S63143851 A JPS63143851 A JP S63143851A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- main surface
- insulating substrate
- parts
- sealing resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 239000011347 resin Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 238000007789 sealing Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229910000679 solder Inorganic materials 0.000 claims abstract description 10
- 230000002093 peripheral effect Effects 0.000 claims abstract description 7
- 230000001788 irregular Effects 0.000 abstract 3
- 230000008878 coupling Effects 0.000 abstract 2
- 238000010168 coupling process Methods 0.000 abstract 2
- 238000005859 coupling reaction Methods 0.000 abstract 2
- 230000006866 deterioration Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001290864 Schoenoplectus Species 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.
従来の半導体装置は厚さを薄くするため半導体素子（チ
ップ）の側面だけを樹脂封止したり（第３ａ図参照）、
また半導体装置の信頼性を増すために半導体素子全面を
樹脂で覆って封止をした（第３ｂ図参照）ものがある。In order to reduce the thickness of conventional semiconductor devices, only the sides of the semiconductor element (chip) are sealed with resin (see Figure 3a).
Furthermore, in order to increase the reliability of the semiconductor device, there is one in which the entire surface of the semiconductor element is covered with resin and sealed (see FIG. 3b).
上述した従来の半導体装置においては、厚さをはくしよ
うとすると樹脂が半導体素子の側面にしかかからないた
め半導体装置の信頼性が損われる問題がある。また、半
導体装置の信頼性を増すために半導体素子の全面を樹脂
で覆って封止すると厚さが厚くなる。In the above-mentioned conventional semiconductor device, there is a problem in that when an attempt is made to reduce the thickness, the resin only covers the side surfaces of the semiconductor element, which impairs the reliability of the semiconductor device. Furthermore, in order to increase the reliability of the semiconductor device, if the entire surface of the semiconductor element is covered with resin and sealed, the thickness will increase.
本発明の半導体装置は第１主表面の周縁部に段差部を有
する半導体チップと：この半導体チップの第２主表面に
ハンダバンプを介して結合される電極を有する絶縁基板
と；前記半導体チップの段差部および側面と前記絶縁基
板とに対して設けられる封止樹脂とを備える。A semiconductor device of the present invention includes: a semiconductor chip having a step portion on a peripheral edge of a first main surface; an insulating substrate having an electrode coupled to a second main surface of the semiconductor chip via a solder bump; and a step portion of the semiconductor chip. and a sealing resin provided to the portion, the side surface, and the insulating substrate.
「実施例：１
次に、本発明の実施例について図面を参照して説明する
。Embodiment 1 Next, an embodiment of the present invention will be described with reference to the drawings.
本発明の一実施例を示す第１図を参照すると、半導体チ
ップ１は絶縁基板４のＡｅ電極５との結合のためにハン
ダバンプ２を有し、この接続面（第２主表面）の裏側面
（第１主表面）の周縁部に段差部３を有している。半導
体チップ１のハンダバンプ２と直接結合するためのＡｅ
電極５を設けた絶縁基板４は封止樹脂７が付き易いよう
に凹凸部６を有する。封止樹脂７は半導体チップ１の第
１主表面上部にはかからず、半導体チップ１の段差部３
から半導体チップ１の側面を経て絶縁基板４上の凹凸部
６まで覆ったものである。凹凸部６は封止樹脂７の固着
力を増大する。Referring to FIG. 1 showing one embodiment of the present invention, a semiconductor chip 1 has solder bumps 2 for bonding with an Ae electrode 5 of an insulating substrate 4, and the back surface of this connection surface (second main surface). It has a stepped portion 3 at the peripheral edge (first main surface). Ae for direct bonding with solder bumps 2 of semiconductor chip 1
The insulating substrate 4 provided with the electrodes 5 has an uneven portion 6 so that the sealing resin 7 can easily adhere thereto. The sealing resin 7 does not cover the upper part of the first main surface of the semiconductor chip 1, but covers the stepped portion 3 of the semiconductor chip 1.
It covers from the side surface of the semiconductor chip 1 to the uneven portion 6 on the insulating substrate 4. The uneven portion 6 increases the adhesion force of the sealing resin 7.
続いて、同実施例の半導体装置を製造する工程を説明す
ると、第２ａ図はハンダバンプ２の付いた４００μｍ厚
のウェハーの両面にハンダバンプ２も隠れるようにマス
ク８をかぶせたところである。Next, to explain the process of manufacturing the semiconductor device of the same embodiment, FIG. 2a shows a 400 μm thick wafer having solder bumps 2 on both sides of which are covered with masks 8 so as to cover the solder bumps 2 as well.
第２ｂ図はエツチングするべき個所だけ穴をあけてウェ
ットエツチングで幅０．８■１．深さ １５０μｍの穴
をあけたところである。第２Ｃ図はマスク８を除いた後
、ウェハーを３龍角に分割して半導体＃体チップ１がで
きたところである。第２ｄ図および第２ｅ図は高粘度封
止樹脂７を型に入れて１００℃、４０分キュアした後、
型から取出した状態を示す。第２ｆ図は半導体チップ１
に上記封止樹脂７をかぶせて絶縁基板４に載せた状態を
示す。Figure 2b shows holes with a width of 0.8 mm and 1.0 mm by wet etching with holes drilled only in the areas to be etched. A hole with a depth of 150 μm was drilled. FIG. 2C shows the semiconductor chips 1 obtained by dividing the wafer into three squares after removing the mask 8. Figures 2d and 2e show that after putting the high viscosity sealing resin 7 into a mold and curing it at 100°C for 40 minutes,
Shown is the state taken out of the mold. Figure 2f shows the semiconductor chip 1.
The state where the above-mentioned sealing resin 7 is covered and placed on the insulating substrate 4 is shown.
第２ｇ図は第２ｆ図の製品を炉中に入れ、２００℃。Figure 2g shows the product shown in Figure 2f placed in a furnace at 200°C.
３０分間加熱している状態を示し、封止樹脂７が溶は始
めた所である。This shows a state in which the sealing resin 7 has been heated for 30 minutes, and the sealing resin 7 has just begun to melt.
なお、封止樹脂７が冷却かつ収縮することにより半導体
チップ１と絶縁基板４との結合はより強固なものになる
。Note that as the sealing resin 7 cools and contracts, the bond between the semiconductor chip 1 and the insulating substrate 4 becomes stronger.
また、ハンダバンプ２を低融点導電性物質で構成し、半
導体チップ１の電極（図示省略）と基板４の電極５との
位置合わせをし、半導体チ・ツブ１の段差部３に封止樹
脂７をかぶせて加熱することにより、同時にボンディン
グと封止どを行うことができる。Further, the solder bumps 2 are made of a low-melting point conductive material, and the electrodes of the semiconductor chip 1 (not shown) are aligned with the electrodes 5 of the substrate 4, and the sealing resin 7 is placed on the stepped portion 3 of the semiconductor chip 1. By covering and heating, bonding and sealing can be performed at the same time.
以上説明したように本発明によれば、半導体チップの第
１主表面の周縁部に段差部を設け、この周縁部の段差部
を除いた第１主表面上部に封止樹脂をかけない構成によ
り、厚さを薄くできるだけではなく、半導体装置の信頼
性が損われることを防止できる。As described above, according to the present invention, a stepped portion is provided at the peripheral edge of the first main surface of a semiconductor chip, and the sealing resin is not applied to the upper part of the first main surface other than the stepped portion of the peripheral edge. Not only can the thickness be reduced, but also the reliability of the semiconductor device can be prevented from being impaired.
第１図は本発明の一実施例を示す構成図、第２ａ図〜第
２ｇ図は同実施例の半導体装置を製造する工程を説明す
る図、第３ａ図および第３ｂ図は従来の半導体装置を示
す構成図である。
１・・・半導体チップ、２・・・ハンダバンプ、３・・
・段差部、４・・・絶縁基板、５・・・ＡＩ！電極、６
・・・凹凸部、７・・・封止樹脂。FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2a to 2g are diagrams explaining the steps of manufacturing a semiconductor device of the same embodiment, and FIGS. 3a and 3b are diagrams of a conventional semiconductor device. FIG. 1... Semiconductor chip, 2... Solder bump, 3...
・Step part, 4...Insulating substrate, 5...AI! electrode, 6
... Uneven portion, 7... Sealing resin.
Claims (1)
結合される電極を有する絶縁基板と；前記半導体チップ
の段差部および側面と前記絶縁基板とに対して設けられ
る封止樹脂と； を備えることを特徴とする半導体装置。[Scope of Claims] A semiconductor chip having a stepped portion on a peripheral edge of a first main surface; an insulating substrate having an electrode bonded to a second main surface of the semiconductor chip via a solder bump; and a stepped portion of the semiconductor chip. A semiconductor device comprising: a sealing resin provided to a portion, a side surface, and the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29310286A JPS63143851A (en) | 1986-12-08 | 1986-12-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29310286A JPS63143851A (en) | 1986-12-08 | 1986-12-08 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143851A true JPS63143851A (en) | 1988-06-16 |
Family
ID=17790448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29310286A Pending JPS63143851A (en) | 1986-12-08 | 1986-12-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143851A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414928A (en) * | 1991-12-11 | 1995-05-16 | International Business Machines Corporation | Method of making an electronic package assembly with protective encapsulant material |
| WO2004082018A2 (en) * | 2003-03-11 | 2004-09-23 | Infineon Technologies Ag | Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same |
| EP1570524A2 (en) * | 2002-12-09 | 2005-09-07 | Advanced Interconnect Technologies Limited | Package having exposed integrated circuit device |
| KR100559649B1 (en) * | 2000-12-26 | 2006-03-10 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device |
| JP2009164206A (en) * | 2007-12-28 | 2009-07-23 | Spansion Llc | Semiconductor device and manufacturing method thereof |
-
1986
- 1986-12-08 JP JP29310286A patent/JPS63143851A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414928A (en) * | 1991-12-11 | 1995-05-16 | International Business Machines Corporation | Method of making an electronic package assembly with protective encapsulant material |
| KR100559649B1 (en) * | 2000-12-26 | 2006-03-10 | 마츠시타 덴끼 산교 가부시키가이샤 | Semiconductor device |
| EP1570524A2 (en) * | 2002-12-09 | 2005-09-07 | Advanced Interconnect Technologies Limited | Package having exposed integrated circuit device |
| EP1570524A4 (en) * | 2002-12-09 | 2007-07-04 | Advanced Interconnect Tech Ltd | Package having exposed integrated circuit device |
| US7554180B2 (en) | 2002-12-09 | 2009-06-30 | Unisem (Mauritius) Holdings Limited | Package having exposed integrated circuit device |
| WO2004082018A2 (en) * | 2003-03-11 | 2004-09-23 | Infineon Technologies Ag | Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same |
| WO2004082018A3 (en) * | 2003-03-11 | 2004-11-11 | Infineon Technologies Ag | Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same |
| US7508083B2 (en) | 2003-03-11 | 2009-03-24 | Infineon Technologies Ag | Electronic component comprising a semiconductor chip and a plastic housing, and method for producing the same |
| JP2009164206A (en) * | 2007-12-28 | 2009-07-23 | Spansion Llc | Semiconductor device and manufacturing method thereof |
| JP4696227B2 (en) * | 2007-12-28 | 2011-06-08 | スパンション エルエルシー | Manufacturing method of semiconductor device |
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