JPS63142832A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63142832A JPS63142832A JP29095486A JP29095486A JPS63142832A JP S63142832 A JPS63142832 A JP S63142832A JP 29095486 A JP29095486 A JP 29095486A JP 29095486 A JP29095486 A JP 29095486A JP S63142832 A JPS63142832 A JP S63142832A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- electrode wiring
- wiring layer
- metal layer
- barrier metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 230000004888 barrier function Effects 0.000 claims abstract description 29
- 229910000765 intermetallic Inorganic materials 0.000 claims abstract description 16
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 238000000605 extraction Methods 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 229920005591 polysilicon Polymers 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 5
- 150000001875 compounds Chemical class 0.000 abstract description 3
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 abstract description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 230000001788 irregular Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 4
- 239000010936 titanium Substances 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置のアルミニウム電極配線層（以下ＡＩ！電極
配線層と略称する）の厚みの不拘−或いは断線不良を防
止するために、電極取り出し窓及びシリコン酸化膜の表
面に設けたバリアメタル層の表面に第１回目のＭ電極配
線層を形成し、次いでアニールにより電極取り出し窓内
にバリアメタル層とＡｌ電極配線層との金属間化合物を
形成してバリアメタル層５の表面との段差をなくし、そ
の後バリアメタル層の表面に形成した第１回目のＡｌ電
極配線層を選択エツチングにより除去し、最後にバリア
メタル層及び金属間化合物の表面に第２回目のＡｔ電極
配線層を形成して、集積回路のアルミニウム電極配線を
平坦にするようにした半導体装置の製造方法。[Detailed Description of the Invention] [Summary] In order to prevent the thickness of the aluminum electrode wiring layer (hereinafter abbreviated as AI!electrode wiring layer) of a semiconductor device from being unrestricted or disconnection failure, electrode extraction windows and silicon oxide film A first M electrode wiring layer is formed on the surface of the barrier metal layer provided on the surface, and then an intermetallic compound of the barrier metal layer and the Al electrode wiring layer is formed in the electrode extraction window by annealing to form a barrier metal layer. After that, the first Al electrode wiring layer formed on the surface of the barrier metal layer was removed by selective etching, and finally the second Al electrode wiring layer formed on the surface of the barrier metal layer and the intermetallic compound was removed. A method of manufacturing a semiconductor device in which an electrode wiring layer is formed to flatten aluminum electrode wiring of an integrated circuit.
本発明は、半導体装置の製造方法における電極配線の形
成に係り、特に微細な電極取り出し窓における電極配線
形成方法の改良に関するものである。The present invention relates to the formation of electrode wiring in a method of manufacturing a semiconductor device, and particularly relates to an improvement in the method of forming electrode wiring in a fine electrode extraction window.
半導体装置の製造工程において、形成される電極配線の
厚みの不拘−或いは断線不良の防止のためには、電極形
成面の平坦化が必要であり、それを可能にする半導体装
置の製造方法が要望されている。In the manufacturing process of semiconductor devices, it is necessary to flatten the electrode formation surface in order to prevent the thickness of the formed electrode wiring from being restricted or disconnection defects, and there is a demand for a semiconductor device manufacturing method that makes this possible. has been done.
従来の半導体装置のＡｔ電極配線層の形成方法は、第２
図（ａ）に示すように半導体基板１の上に形成したシリ
コン酸化膜２に、電極取り出し窓１７を形成する場合に
垂直の壁面を有する電極取り出し窓にすると、その後に
形成するＡｔ’＠極配線層の水平面と垂直面の交差部分
で層の厚みが薄くなり、Ｍ電極配線層の断線不良発生の
恐れがあるため、図示のようにテーパー状にして、その
表面にポリシリコン層１３を形成している。The conventional method for forming an At electrode wiring layer of a semiconductor device is the second method.
As shown in Figure (a), when an electrode extraction window 17 is formed in the silicon oxide film 2 formed on the semiconductor substrate 1, if the electrode extraction window 17 is made to have a vertical wall surface, the At'@ electrode formed thereafter The thickness of the layer becomes thinner at the intersection of the horizontal and vertical planes of the wiring layer, and there is a risk of disconnection failure in the M electrode wiring layer, so the polysilicon layer 13 is formed on the tapered shape as shown in the figure. are doing.
その後Ａｔ蒸着により、Ａｌををポリシリコン層１３の
上に蒸着してＭ電極配線層１９を形成している。Thereafter, Al is deposited on the polysilicon layer 13 by At vapor deposition to form an M electrode wiring layer 19.
以上説明の従来の半導体装置のＡｔ電極配線層の形成で
問題となるのは、シリコン酸化膜の電極取り出し窓の形
状をテーパー状にして、Ｍ電極配線層の厚みの不拘−或
いは断線不良の防止を図ったり、又、Ａｔ蒸着を行う際
にバイアス・スパッタを行って水平面とテーパー面での
Ｍ電極配線層の厚みの差を減少させるようにしているが
、電極取り出し窓の形状のテーパー化は技術的に難しく
、又Ａｌ蒸着を行う際のバイアス・スパッタ実施にも限
度があり、平坦なＭ電極配線層の形成が困難なことであ
る。The problem in forming the At electrode wiring layer of the conventional semiconductor device described above is that the shape of the electrode extraction window of the silicon oxide film is tapered to prevent the thickness of the M electrode wiring layer from being restricted or disconnection defects. Also, bias sputtering is performed when performing At vapor deposition to reduce the difference in thickness of the M electrode wiring layer between the horizontal surface and the tapered surface, but the tapered shape of the electrode extraction window is This is technically difficult, and there are limits to bias sputtering when depositing Al, making it difficult to form a flat M electrode wiring layer.
更に電極取り出し窓７をテーパー状にするために、電極
取り出し窓７０間隔を広くすることが必要になり、高い
集積度が要求される集積回路装置の製造の可能性を狭め
ている。Furthermore, in order to make the electrode extraction windows 7 tapered, it is necessary to widen the interval between the electrode extraction windows 70, which narrows the possibility of manufacturing an integrated circuit device that requires a high degree of integration.
本発明は以上のような状況から、簡単に実施できるＡｔ
電極配線層の平坦化による電極取り出し窓の微細化技術
の提供を目的としたものである。In light of the above-mentioned circumstances, the present invention has been developed to provide an easy-to-implement At
The purpose is to provide a technology for miniaturizing electrode extraction windows by flattening the electrode wiring layer.
上記問題点は、電極取り出し窓及びシリコン酸化膜の表
面に設けたバリアメタル層の表面に第１のＭ電極配線層
を形成し、次いでアニールにより電極取り出し窓内のバ
リアメタル層とＡｔ電極配線層との金属間化合物を形成
してバリアメタル層の表面との段差をなくし、その後バ
リアメタル層の表面に形成した第１のＡｔ電極配線層を
選択エツチングにより除去し、最後にバリアメタル層及
び金属間化合物の表面に第２のＡｔ電極配線層を形成し
て、Ｍ電極配線層の厚みの不拘−或いは断線不良の防止
が可能な、平坦な表面を形成するようにした本発明によ
る半導体装置の製造方法によって解決される。The above problem can be solved by forming the first M electrode wiring layer on the surface of the barrier metal layer provided on the electrode extraction window and the surface of the silicon oxide film, and then annealing the barrier metal layer in the electrode extraction window and the At electrode wiring layer. After that, the first At electrode wiring layer formed on the surface of the barrier metal layer is removed by selective etching, and finally the barrier metal layer and the metal In the semiconductor device according to the present invention, a second At electrode wiring layer is formed on the surface of the intermediate compound to form a flat surface that can prevent the thickness of the M electrode wiring layer from being restricted or disconnection defects. The problem is solved by the manufacturing method.
即ち本発明においては、半導体基板上に形成したシリコ
ン酸化膜に垂直に形成した電極取り出し窓及びシリコン
酸化膜上に、ポリシリコン層と金属層とバリアメタル層
を順次形成し、その上に第１回目のＡｔ電極配線層を形
成する。That is, in the present invention, a polysilicon layer, a metal layer, and a barrier metal layer are sequentially formed on an electrode extraction window and a silicon oxide film formed perpendicularly to a silicon oxide film formed on a semiconductor substrate, and a first A second At electrode wiring layer is formed.
アニール処理により、電極取り出し窓内にバリアメタル
層とＡｔ電極配線層との金属間化合物を形成させ、ポリ
シリコン層の側壁で囲まれた空間を金属間化合物によっ
て充満し、バリアメタル層の表面との段差をなくし、バ
リアメタル層の表面に形成した第１回目のアルミニウム
電極配線層を選択エツチングするので、第２回目のＡｔ
電極配線層はバリアメタル層と金属間化合物の連続した
平坦な表面上に形成可能となる。By annealing, an intermetallic compound between the barrier metal layer and the At electrode wiring layer is formed within the electrode extraction window, and the space surrounded by the side walls of the polysilicon layer is filled with the intermetallic compound, and the surface of the barrier metal layer and the At electrode wiring layer are filled with the intermetallic compound. Since the first aluminum electrode wiring layer formed on the surface of the barrier metal layer is selectively etched, the second At
The electrode wiring layer can be formed on the continuous, flat surface of the barrier metal layer and the intermetallic compound.
以下第１図について本発明の一実施例を説明する。 An embodiment of the present invention will be described below with reference to FIG.
第１図は本発明による一実施例を工程順に示す側断面図
である。FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.
第１図（ａ）に示すように、半導体基板ｌの上に形成さ
れたシリコン酸化膜２に設けた電極取り出し窓７には、
ポリシリコン層３、金属層４、バリアメタル層５が順次
積層して形成されている。As shown in FIG. 1(a), an electrode extraction window 7 provided in a silicon oxide film 2 formed on a semiconductor substrate l has a
A polysilicon layer 3, a metal layer 4, and a barrier metal layer 5 are sequentially stacked.
本実施例では金属層４はチタン（Ｔｉ）、バリアメタル
層５は窒化チタン（ＴｉＮ）である。In this embodiment, the metal layer 4 is made of titanium (Ti), and the barrier metal layer 5 is made of titanium nitride (TiN).
先ず、この表面に第１回目のＭ電極配線層６を形成する
。このＡｌ電極配線層６は図示のように電極取り出し窓
７の部分に窪みのある不均一な厚みの形状をしている。First, a first M electrode wiring layer 6 is formed on this surface. As shown in the figure, this Al electrode wiring layer 6 has a shape with a uneven thickness and a depression at the electrode extraction window 7.
次に、アニール処理を行うと、第１図（ｂ）に示すよう
に、ＴｉＮからなるバリアメタル層５の垂直面のみが質
的な変化を起こして、Ａｔ電極配線層６のＭと反応して
アルミニウムチタン（Ａｔ’Ｔｉ）からなる金属間化合
物８を形成し、電極取り出し窓７のポリシリコン層３の
側壁で囲まれた空間を充満する。Next, when annealing treatment is performed, only the vertical surface of the barrier metal layer 5 made of TiN undergoes a qualitative change and reacts with M of the At electrode wiring layer 6, as shown in FIG. 1(b). An intermetallic compound 8 made of aluminum titanium (At'Ti) is formed and fills the space surrounded by the side wall of the polysilicon layer 3 of the electrode extraction window 7.
この場合にバリアメタル層５の水平面は上記の質的な変
化が起こらないので、Ｍ電極配線層６と反応することな
く残存する。In this case, the above-mentioned qualitative change does not occur on the horizontal surface of the barrier metal layer 5, so that it remains without reacting with the M electrode wiring layer 6.
次いで、第１図（Ｃ）に示すように第１回目のＭ’電極
配線層６を選択エツチングによって除去し、バリアメタ
ル層５と金属間化合物８の連続した表面を形成する。Next, as shown in FIG. 1C, the first M' electrode wiring layer 6 is removed by selective etching to form a continuous surface of the barrier metal layer 5 and the intermetallic compound 8.
最後に、この平坦に形成されたパリアメクル層５と金属
間化合物８の上に第２回目のＡｔ電極配線層９を形成す
る。Finally, a second At electrode wiring layer 9 is formed on the parium metal layer 5 and the intermetallic compound 8 which have been formed flat.
このように、Ｍ電極配線層９とポリシリコン層３が直接
接触した場合に、反応を起こす障害防止のためのバリア
メタル層５と、第１回目のＡＩ電極配線！６のＡｔが金
属間化合物８を垂直面のみに形成することを利用して、
電極取り出し窓７の内部のポリシリコンＮ３で囲まれた
空間を金属間化合物８で完全に充満させることが可能と
なり、その後に形成する第２回目の＾ｌ電極配′ｆ！Ａ
層９を平坦な表面上に形成できるので、Ａｊ！電極配線
層９形成時に発生するＡｔ電極配線層９の厚みの不拘−
或いは断線不良の防止が可能となる。In this way, when the M electrode wiring layer 9 and the polysilicon layer 3 are in direct contact with each other, the barrier metal layer 5 is formed to prevent a reaction from occurring, and the first AI electrode wiring! Taking advantage of the fact that At of 6 forms intermetallic compound 8 only on the vertical plane,
It becomes possible to completely fill the space surrounded by polysilicon N3 inside the electrode extraction window 7 with the intermetallic compound 8, and the second electrode arrangement 'f! A
Since layer 9 can be formed on a flat surface, Aj! Inconsistency in the thickness of the At electrode wiring layer 9 that occurs when forming the electrode wiring layer 9
Alternatively, disconnection defects can be prevented.
以上説明したように本発明によれば、集積度が高くなっ
てパターンが微細化した集積回路装置におけるＡｔ電極
配線層を、極めて小さな間隔で形成することが可能にな
り、より一層集積度の高い半導体装置の製造が可能にな
る利点があり、著しい経済的及び、信頼性向上の効果が
期待でき工業的には極めて有用なものである。As explained above, according to the present invention, it is possible to form At electrode wiring layers at extremely small intervals in integrated circuit devices with a higher degree of integration and finer patterns. It has the advantage of making it possible to manufacture semiconductor devices, and can be expected to have significant economical and reliability improvement effects, making it extremely useful industrially.
第１図は本発明による一実施例の半導体装置の製造方法
を工程順に示す側断面図、
第２図は従来のＡｔ電極配線層の形成方法を示す側断面
図、
である。
図において、
１は半導体基板、 ２はシリコン酸化膜、３はポリシ
リコン層、４は金属層、
５はバリアメタル層、６はＡｔ電極配線層、７は電極取
り出し窓、８は金属間化合物、９はＡｔ電極配線層、
第１図FIG. 1 is a side cross-sectional view showing the process order of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a side cross-sectional view showing a conventional method for forming an At electrode wiring layer. In the figure, 1 is a semiconductor substrate, 2 is a silicon oxide film, 3 is a polysilicon layer, 4 is a metal layer, 5 is a barrier metal layer, 6 is an At electrode wiring layer, 7 is an electrode extraction window, 8 is an intermetallic compound, 9 is an At electrode wiring layer, Fig. 1
Claims (1)
に設けたバリアメタル層（５）の表面に第１のアルミニ
ウム電極配線層（６）を形成する工程と、アニールによ
り前記電極取り出し窓（７）内に前記バリアメタル層（
５）と前記アルミニウム電極配線層（６）との金属間化
合物（８）を形成する工程と、前記バリアメタル層（５
）の表面に形成した第１の前記アルミニウム電極配線層
（６）を選択エッチングして除去する工程と、 前記バリアメタル層（５）及び前記金属間化合物（８）
の表面に第２のアルミニウム電極配線層（９）を形成す
る工程と、 を含むことを特徴とする半導体装置の製造方法。[Claims] A step of forming a first aluminum electrode wiring layer (6) on the surface of the barrier metal layer (5) provided on the surface of the electrode extraction window (7) and the silicon oxide film (2), and annealing. The barrier metal layer (
5) and the aluminum electrode wiring layer (6) to form an intermetallic compound (8), and the barrier metal layer (5).
) selectively etching and removing the first aluminum electrode wiring layer (6) formed on the surface of the barrier metal layer (5) and the intermetallic compound (8).
A method for manufacturing a semiconductor device, comprising: forming a second aluminum electrode wiring layer (9) on the surface of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29095486A JPS63142832A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29095486A JPS63142832A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63142832A true JPS63142832A (en) | 1988-06-15 |
Family
ID=17762622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29095486A Pending JPS63142832A (en) | 1986-12-05 | 1986-12-05 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63142832A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2720856A1 (en) * | 1994-04-28 | 1995-12-08 | Nippon Denso Co | Wiring electrode for semiconductor device and its manufacturing process. |
| US5700718A (en) * | 1996-02-05 | 1997-12-23 | Micron Technology, Inc. | Method for increased metal interconnect reliability in situ formation of titanium aluminide |
| US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
| JP2002246607A (en) * | 2001-02-05 | 2002-08-30 | Samsung Electronics Co Ltd | Thin film transistor substrate and its fabricating method |
| US6617242B1 (en) | 1989-11-30 | 2003-09-09 | Stmicroelectronics, Inc. | Method for fabricating interlevel contacts of aluminum/refractory metal alloys |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
-
1986
- 1986-12-05 JP JP29095486A patent/JPS63142832A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6242811B1 (en) | 1989-11-30 | 2001-06-05 | Stmicroelectronics, Inc. | Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature |
| US6617242B1 (en) | 1989-11-30 | 2003-09-09 | Stmicroelectronics, Inc. | Method for fabricating interlevel contacts of aluminum/refractory metal alloys |
| FR2720856A1 (en) * | 1994-04-28 | 1995-12-08 | Nippon Denso Co | Wiring electrode for semiconductor device and its manufacturing process. |
| US6066891A (en) * | 1994-04-28 | 2000-05-23 | Nippondenso Co., Ltd | Electrode for semiconductor device including an alloy wiring layer for reducing defects in an aluminum layer and method for manufacturing the same |
| US6348735B1 (en) | 1994-04-28 | 2002-02-19 | Nippondenso Co., Lt. | Electrode for semiconductor device and method for manufacturing same |
| US5700718A (en) * | 1996-02-05 | 1997-12-23 | Micron Technology, Inc. | Method for increased metal interconnect reliability in situ formation of titanium aluminide |
| US6650017B1 (en) | 1999-08-20 | 2003-11-18 | Denso Corporation | Electrical wiring of semiconductor device enabling increase in electromigration (EM) lifetime |
| US6908857B2 (en) | 1999-08-20 | 2005-06-21 | Denso Corporation | Method of manufacturing semiconductor device |
| JP2002246607A (en) * | 2001-02-05 | 2002-08-30 | Samsung Electronics Co Ltd | Thin film transistor substrate and its fabricating method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100291284B1 (en) | Aluminum metal layer wiring method | |
| JPS63142832A (en) | Manufacture of semiconductor device | |
| JPH07193024A (en) | Semiconductor device and its manufacture | |
| JPH045823A (en) | Semiconductor device and its manufacture | |
| JPH0273652A (en) | Manufacture of semiconductor device | |
| JPS59141232A (en) | Manufacture of semiconductor device | |
| JPH06232074A (en) | Semiconductor device and its manufacture | |
| JPS61214449A (en) | Manufacture of semiconductor element | |
| JPH07326668A (en) | Manufacture of semiconductor device | |
| JPH02156537A (en) | Manufacture of semiconductor device | |
| JPS63161645A (en) | Manufacture of semiconductor device | |
| JPH0118582B2 (en) | ||
| JPS59232443A (en) | Manufacture of semiconductor device | |
| JPS62108542A (en) | Manufacture of semiconductor device | |
| JP2674654B2 (en) | Method for manufacturing semiconductor device | |
| JPH03125469A (en) | Structure for mim capacitor | |
| JPH06151415A (en) | Manufacturing method of semiconductor device | |
| JPS6249735B2 (en) | ||
| JPH01239941A (en) | Semiconductor device | |
| JPS63177445A (en) | Manufacture of semiconductor device | |
| JPH033382B2 (en) | ||
| JPH01115137A (en) | Formation of wiring | |
| JPH0376127A (en) | Manufacture of semiconductor device | |
| JPH0273651A (en) | Semiconductor device | |
| JPH0379031A (en) | Semiconductor device |