JPS6313582B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a matrix panel drive circuit,
A drive circuit that enables an XY matrix panel configured to suit the number of scanning lines of a certain television broadcast to be used without problems in other television broadcasting areas with a different number of scanning lines, and to display TV images. The purpose is to provide.

The number of scanning lines in NTSC color TV broadcasting is 525.
In a book, 42 lines are included in the vertical blanking period, so the remaining 483 lines are effective scanning lines. Therefore, it is common to configure the number of picture elements in the vertical direction in an XY matrix panel to be around 480 or approximately 480/N (N is an integer), and to configure the row electrodes X to have the same number as the number of picture elements. . Furthermore, in order to improve the quality of the displayed image, it is necessary to make the pitch of the X electrodes extremely small, which makes it difficult to connect the X electrodes to the X electrode drive circuit. Therefore, it is common to have a configuration in which every other input terminal for applying a scanning signal to the X electrode is distributed to the left and right. In this configuration, from the X electrode drive circuit to the
In order to shorten the length of the wires that are routed to the vicinity of the electrode input terminals and reduce the number of crossing points, it is necessary to place the X electrode drive circuits close to each other on the left and right sides of the panel as shown in FIG.

Next, according to Figure 1, XY matrix panel 1
(Here, a conventional scanning circuit will be described when N=2, that is, a panel with 240 X electrodes is taken as an example). The synchronization separation circuit 3 obtains a composite synchronization signal from the video signal of the terminal 2, and the V/H separation circuit 4 obtains a vertical synchronization signal V (Fig. 2a) and a horizontal synchronization signal H.
(Fig. 2b) is obtained. Next, the control signal generation circuit 5
A vertical scanning start pulse (Fig. 2 c) is obtained based on the vertical synchronization signal, which is used as serial input to the X electrode drive circuits 6 and 7 composed of shift registers, and the horizontal synchronization signal is used to drive the X electrode. If the clock signals of the circuits 6 and 7 are used, the 1st stage, 2nd stage, and 3rd stage of the shift registers of both the X electrode drive circuits 6 and 7 are used.
d ₁ , d ₂ , d ₃ , d ₄ in Figure 2 in order from each row...
A scanning pulse signal shown in d ₅ ... is obtained. And X
The first stage output of the electrode drive circuit 6 (Fig. 2 d ₁ ) is added to the first row X ₁ of the X electrode, and the second stage output of the X electrode drive circuit 7 (Fig. 2 d ₂ ) is added to the X electrode. Add to 2nd row X ₂ . Next, the output of the third stage of the X electrode drive circuit 6 (d ₃ in Fig. 2) is added to X ₃ , and so on. In the electrode drive circuit 7, if the outputs of the even-numbered stages are applied to the X electrodes of the even-numbered rows,
Sequential scanning pulses are added to X ₁ , X ₂ , X ₃ , X ₄ ...,
The panel is scanned.

On the other hand, Y consists of a sample and hold circuit.
In the electrode drive circuits 8 and 9, the serial video signal is converted into parallel video signals for a total of several Y electrodes, and each converted signal is simultaneously applied to the corresponding Y electrode. Then, pixels 10 are sequentially selected line at a time by scanning pulses applied to the X electrodes, and the panel 1 is driven. At this time, since the number of X electrodes is 240, interlacing is not performed.

Now, let's consider using this panel to receive a PAL color television broadcast with 625 scans and display the image. At this time, the number of scanning lines is 625
The book contains 50 lines in the vertical retrace period, so the remaining
575 is the effective number of scanning lines. Since no interlacing is performed, 575
The number of X electrodes is required: 287 pieces/2=287 pieces. Therefore X
If a panel with 240 electrodes is used, 287 - 240 = 47 images cannot be displayed, and the image will be displayed in a state with a large overscan in the vertical direction.

Next, contrary to what was mentioned above, like the PAL method,
Consider a panel configured for a 625-line television image broadcast area. In this case, since the number of effective scanning lines is 575, it is common for the XY matrix panel to have a vertical picture element number of around 560 (560/N) (N is an integer). As before, when N=2, the number of X electrodes is
Consider a 280-line XY matrix panel.
When this matrix panel receives NTSC television broadcasts and displays images, interlacing is not performed as explained earlier, so 241 scanning lines are effective to display one image. It becomes a scanning line. Therefore, there is no video information to be displayed on 280-241=39 X electrodes. Therefore, the displayed image is contracted in the vertical direction.

Regarding the means to solve the problems in the two cases mentioned above, we have previously discussed Japanese Patent Application No. 54-90595 and Japanese Patent Application No.
-90596, the present invention is particularly advantageous in that, as shown in FIG. 1, terminals for applying scanning signals to the The purpose of this invention is to propose a drive circuit suitable for scanning a panel in which the drive circuits are arranged close to each other on the left and right sides of the panel.

Now, we will discuss the particular problems that arise when the X electrode drive circuits 6 and 7 are arranged on the left and right sides of the panel 1 as shown in FIG. In particular, the X electrode drive circuit of the present invention is intended to be integrated into an IC. When displaying an image with 625 scanning lines on a panel configured to accommodate 525 scanning lines, horizontal scanning is omitted for one vertical scanning period to prevent unnaturalness from appearing in the displayed image. It is necessary to take care not to concentrate the positions in one place, or at least not to make them consecutive. Therefore, as proposed in patent application No. 54-90595,
It is necessary to add new FFs to the scanning shift register composed of flip-flop circuits FF of the X electrode drive circuit so as not to concentrate them in one place in the shift register. However, the same structure configured like this
When two X-electrode drive ICs in the IC pattern are placed on the left and right sides of the panel 1, the result is that horizontal scanning is not performed continuously.

Conversely, a similar problem occurs when displaying an image with 525 scanning lines on a panel configured to accommodate 625 scanning lines. In this case, as proposed in Japanese Patent Application No. 54-90596, by removing the FF constituting the scanning shift register at a predetermined location, two consecutive X electrodes can be connected for one vertical scanning period. Satisfactory display can be achieved by scanning simultaneously without concentrating, but if X electrode drive ICs with the same pattern are placed on the left and right sides of panel 1, four consecutive X electrodes will be selected at the same time. This will cause problems.

In order to solve such problems, it is necessary to create two types of X electrode drive ICs for left and right, but the present invention provides the left and right switching terminals in the X electrode drive IC, so that the It solves problems.

An embodiment of the present invention will be described below based on the drawings. FIG. 3 shows details of an X electrode drive circuit as a first embodiment of the present invention. This circuit is shown in an IC configuration, and the IC is inside the dash-dotted line. Terminal 11
is a serial signal input terminal, terminal 12 is a clock signal input terminal, terminal 13 is a left/right switching terminal, terminal 1
4 is a switching terminal for 525/625 scanning lines, terminal 15
is a first gate signal input terminal, terminal 16 is a second gate signal input terminal, and terminal 17 is a serial signal output terminal.

The arrangement of the X electrode drive IC shown in FIG. 3 with respect to the panel will be explained using FIG. 6. Now, as an example, let us assume that the total number of X electrodes is 240, and _the X electrodes in odd-numbered rows
Panel 1 is configured such that scanning pulse signals are applied to X _{3 ,} X _{5 . .} . from the left side of panel 1, and scan pulse signals are applied to even-numbered row X electrodes X ₂ , The target is The drive IC shown in Figure 3 is 30
Since this is for channel output, four drive ICs as shown in FIG. 3 are arranged on each side of the panel 1, as shown in FIG. And the four Xs in Figure 3 placed on the left side
The electrode drive ICs, I ₁ , I ₂ , I ₃ , and I ₄ are wired by applying a serial signal of a scan start pulse to the serial input terminal 11 of I ₁ , and by applying a serial signal obtained from the serial output terminal 17 of I ₁ . I ₂ serial input terminal 11
It has been added to Similarly, I ₂
Terminal 17 of I ₃ and terminal 11 of I 3 are connected, and terminal 17 of I ₃ and terminal 11 of I ₄ are connected. And I ₁ , I ₂ ,
The left/right switching terminals 13 of the X electrode drive ICs shown in FIG. 3 for I ₃ and I ₄ are set to "H".

Next, the wiring for the four X electrode drive ICs, I ₅ , I ₆ , I ₇ , and I ₈ placed on the right side of panel 1, is connected to the same scan start pulse that was applied to I ₁ to the serial input terminal 11 of I ₅ . A serial signal of I ₅ is applied.
The serial output terminal 17 of _I6 and the serial input terminal 11 of I6, the terminal 11 of _I6 and the terminal 17 of _I7 , and the terminal 17 of _I7 and the terminal ₁₁ of I8 are connected, respectively. Then, set the left/right switching terminals 13 of I ₅ , I ₆ , I ₇ , and I ₈ to “L”.
Make it.

And I ₁ , I ₂ ... I ₈ clock signal input terminal 12
are wired so that the same clock signal is applied to them, and the 525/625 switching terminals 14 of _I1 , _I2 ... _I8 are wired in common, and 525 scanning lines are connected according to the scanning lines of the television signal to be received. When there are 625 scanning lines, it is set to "L", and when there are 625 scanning lines, it is set to "H".

Next, the X electrode drive IC shown in FIG. 3 will be explained.
F ₁ , F ₂ , F ₃ ...F ₃₀ are flip-flops FF, which constitute a shift register, and the output of each stage is sent to the output terminal ch1 of each corresponding channel via a NAND circuit A1, A2, A3...A30. ,ch2,
Added to ch3-ch30. Also, one out of three FF circuits F has three NAND circuits B,
C, D, one inverter circuit E, and one inverter circuit E.
An FF circuit F' is provided and wired as shown in FIG.

Next, the signals applied to the X electrode drive IC shown in FIG. 3 will be explained using FIGS. 4 and 5. Vertical synchronizing signal V (5th
Figure a) is the programmable counter 18 (Figure 4).
Added as a reset signal. Next, the horizontal synchronizing signal H (Fig. 5b) obtained by the V/H separation circuit 4 is used as a clock signal, and this is applied to the V/H separation circuit 4 as shown in Fig. 5a.
The signal is frequency-divided as a reset signal to obtain a Q output as shown in FIG. 5c and an output as shown in FIG. 5d. This Q
The output (Fig. 5c) is transferred to the programmable counter 18.
For example, when the number of scanning lines of the television image to be displayed is 525, the program terminal 2 is set as the clock signal.
0 to "L" on the side of 525 scanning lines, the programmable counter 18 is set to an octal counter (M = 8) and operated, and the pulse width is 2H, which is delayed by 16H from the V signal in Figure 5a, as shown in Figure 5. The output shown in e is obtained, and this is inverted by the inverter 21 to obtain the signal shown in FIG. 5f. This signal (FIG. 5f) is applied as a serial input signal to terminal 11 in FIG. Also FF circuit 19
The Q output (FIG. 5c) is applied to the terminal 12 in FIG. 3, and this is used as a clock signal. The FF in FIG. 3 operates in synchronization with the falling edge. When the X electrode drive IC in Figure 3 is placed on the left side of the panel 1 as shown in 6 in Figure 1, the Q output of the FF circuit 19 in Figure 4 (c in Figure 5, hereinafter referred to as the G ₂ signal) ) is applied to terminal 16 and the output (FIG. 5d, hereinafter referred to as the G ₁ signal) is applied to terminal 15. On the other hand, when the X electrode drive IC of FIG _. 3 is placed on the right side of the panel 1 as shown in 7 of FIG. Add G ₁ signal respectively.

Now, we will explain the first condition when displaying a television image with 525 scanning lines, and when the X electrode drive IC of FIG. 3 is placed on the left side of panel 1 as shown in 6 of FIG. 1. . At this time, terminal 1 in Figure 3
3 is wired to “H” as shown in Figure 6,
The 525/625 switching terminal 14 is set to "L" by a switch 28 shown in FIG. Therefore, the outputs of the NAND circuits 22 and 23 become "H". Therefore, the outputs of the inverter circuits E1, E2...E10 become "L", and the outputs of the NAND circuits _D1 , _D2 ... _D10 always become "H". Therefore, the output of FF circuit F3 is
Inverted twice by NAND circuits B1 and C1, F3
The same signal as the output of is input to F4. Similarly F
The output of F6 is inverted twice by B2 and C2, and the same signal as the output of F6 is applied to F7. Similarly, F1, F2, F3, F4, . . . , F30 constitute a cascade-connected shift register. Then, the pulse signal shown in FIG. 5 f with a pulse width of 2H period applied to the terminal 11 is sequentially shifted in synchronization with the falling edge of the pulse with a period of 2H period shown in FIG. 5 c as a serial input signal. and F
From F2, F3, _F4 ..., _the pulse signal of the period (T ₁ + T ₂ ) shown in FIG _.
g ₄ (T ₃ + T ₄ ), (T ₅ + T ₆ ), (T ₇
+T ₈ )... A pulse signal of the period is obtained. while 52
Since the 5/625 switching terminal 14 is "L", the "H" output of the inverter circuit 24 and the _G1 signal of the terminal 15 are applied to the NAND circuit 25, and the inverted ₁ signal of the ₁ signal that is the inverted version of the G ₁ signal is generated. can get. On the other hand, the _G2 signal at terminal 16 and the “L” signal at terminal 14
It joins the NAND circuit 26 and obtains an “H” output,
This is applied to the NAND circuit 27 together with the ₁ signal from the NAND circuit 25 to obtain the G ₁ signal. After all, the G ₁ signal
It is added to NAND circuits A1, A2, A3, A4...A30. In other words, the output of the FF circuit F1 (Fig. 5 g ₁ )
and G ₁ signal (Fig. 5d) are added to A1, and the 5th
A scanning pulse signal for the T ₁ period shown in FIG. h ₁ can be taken out from the terminal ch ₁ in FIG. 3. The output of this ch ₁ is applied to the X ₁ electrode of panel 1 shown in FIG. Next, the F2 output and _G1 signal are added to A2 in the same way, and the fifth
The scanning pulse signal for period _T3 shown in Figure _h2 can be taken out to terminal _ch2 . This ch ₂ output is then applied to the X3 electrode. In the same way, NAND circuits A3 and A
4..., select only the first half 1H pulse width of the 2H pulse width pulse output of FF circuits F3, F4... using _{the G1} signal (Fig. ₅ d),
The scanning pulse signals of the T ₅ and T ₇ periods shown in ... are ch ₃ ,
ch ₄ ...obtained from the terminal. And these are X ₅ and X ₇
It is sequentially added to the odd-numbered X electrodes of... Figure 5
As is clear from h ₁ , h ₂ , h ₃ , and h _4, the terminals in Figure 3
From ch ₁ , ch ₂ . . ., scanning pulse signals of odd-numbered periods T ₁ , T ₃ , T ₅ .

Next, in the second state, when displaying a television image with 525 scanning lines, the X electrode drive IC shown in Figure 3 is used.
A case will be explained in which the panel is placed on the right side of the panel 1 as shown in 7 in FIG. At this time, left/right switching terminal 1
Set 3 to “L”. And this time, there is a fifth terminal on terminal 15.
Wire the wires so that the G ₂ signal shown in FIG. c and the G ₁ signal shown in FIG. 5 d are added to the terminal 16. Set the 525/625 switching terminal 14 to "L" as before. Then, the same serial signal shown in FIG. 5f as before is applied to the terminal 11, and the _G2 signal shown in FIG. 5c, the same as before, is applied to the terminal 12 as a clock signal. serial signal,
Since the clock signal is the same as in the first state, F1,
From F2, F3, F4..., Figure 5 g ₁ , g ₂ , g ₃ , g ₄ ...
You will get the output shown below. However, now on terminal 15
G ₂ signal (Fig. 5c) is applied, 525/625
Since the switching terminal 14 is in the same state as in the first state, the G ₂ signal from the terminal 15 and the NAND circuit 27 is applied to the NAND circuits A1, A2, A3, A4, A5 . . . A30. That is, the output of FF circuit F1 (Fig. 5 g ₁ ) and
The G ₂ signal (FIG. 5c) is applied to the NAND circuit A1, and the scanning pulse signal for the T ₂ period shown in FIG. 5 _i1 is taken out from the ch ₁ terminal in FIG. FF circuit F in NAND circuits A2, A3...
Select only the latter half 1H pulse width using the G ₂ signal (Fig. 5 c) to output the 2H pulse width of ₂ , F3..., and output T ₄ as shown in Fig. 5 i 2 , i ₃ , i ₄ ... , T ₆ , T ₈ periods are obtained from terminals ch ₂ , ch ₃ , ch ₄ . . . . Then, according to the arrangement shown in Fig. 6, the terminals ch ₁ ,
The scanning pulse signals of ch ₂ , ch ₃ , ch ₄ ... are X ₂ , X ₄ ,
It is sequentially applied to even-numbered X electrodes of X ₆ , X ₈ .

As explained above, the scanning line is
All you have to do is display 525 television images.

Next, we will explain how to display a television image with 625 scanning lines. First, the third state is when displaying a television image with 625 scanning lines.
The case where the X electrode drive IC shown in FIG. 3 is arranged on the left side of the panel 1 as shown in FIG. 3 will be explained. At this time the third
The left/right switching terminal 13 in the figure is "H" due to the wiring shown in FIG. 6, and the 525/625 switching terminal 14 is the
Set the switch 28 in the figure to "H". Therefore
The output of NAND22 is "H" and the output of NAND23 is "L". Therefore, inverter circuit E1,
The outputs of E3, E5, E7, and E9 become “L”,
The outputs of NAND circuits D1, D3, D5, D7, and D9 are always "H". Therefore, FF circuits F3, F9,
The outputs of F15, F21, and F27 are respectively
It is inverted by NAND circuits B1, B3, B5, B7, and B9, and further NAND circuits C1, C3, and
Invert at C5, C7, C9, F3, F9, F1
The same outputs as those of 5, F21, and F27 are input to F4, F10, F16, F22, and F28, respectively. On the other hand, since the output of the NAND circuit 23 is "L", the NAND circuits B2, B4, B6, B8, B1
The output of 0 is always "H". Therefore, FF circuit F6,
The outputs of F12, F18, F24, and F30 are input to FF circuits F'2, F'4, F'8, and F'10, respectively.
The outputs of F'2, F'4, F'6, F'8, and F'10 are NAND circuits D2, D4, D6, D8, and D10, respectively.
is inverted, and further NAND circuits C2, C4, C6,
Re-invert at C8 and C10 and change to F'2, F'4, F'6,
The same outputs as F'8 and F'10 are input to FF circuits F7, F13, F19, F25 and serial signal output terminal 17, respectively. That is, FF circuits F1, F2, F3, F4, F5, F6, F'2,
F7, F8...F12, F'4, F13...F18,
F'6, F19...F24, F'8, F25...F30,
F'10 are connected in cascade one after another to form a shift register.

Next, the signals applied to the X electrode drive IC shown in FIG. 3 are basically the same as those explained previously using FIGS. When the program terminal 20 is set to "H" for 625 scanning lines, the count number of the programmable counter 18 is changed to a decimal counter (M=8) different from the octal counter (M=8) when 525 scanning lines are received. 10) and operate with a pulse width delayed by 20H from the vertical synchronization signal shown in Figure 5a.
Obtain the output shown in Fig. 5 e (M = 10) of 2H, invert it with the inverter 21 of Fig. 4 to obtain Fig. 5 f, and use this pulse signal as the serial input signal in the third Add to terminal 11 in the figure. Same as before
The _G2 signal of the Q output (Fig. 5c) of the FF circuit 19 is used as a clock signal to the terminal 12 of Fig. 3, and further
In addition to the terminal 16 as the G ₂ signal, the output of the FF circuit 19 (FIG. 5d) is applied as the G ₁ signal to the terminal 15. Then, the serial input signal shown in FIG.
The cycle shown in Figure c is synchronized with the falling edge of the clock signal pulse in the 2H period, and as explained earlier, the cascade-connected FF circuit F1 is selected by the left/right switching terminal 13 and the 525/625 switching terminal 14.
Shift in the order of F2...F6, F'2, F7, F8... And from F1, it is shown in Figure 5 g ₁ (T ₁ + T ₂ )
The pulse signal of the period (T ₃ + T ₄ ) shown in Fig. 5 g ₂ is obtained from F2, and then sequentially from F6.
From this, a pulse for a period of (T ₁₁ +T ₁₂ ) is obtained, a pulse for a period of (T ₁₃ +T ₁₄ ) is obtained from the next stage F'2, and a pulse for a period (T ₁₅ +T ₁₆ ) is obtained from the next stage F7. while 5
Since the 25/625 switching terminal 14 is "H", the output of the inverter circuit 24 is "L", and the output of the NAND circuit 25 is always "H". and terminal 1
The G ₂ signal of 6 is inverted by the NAND circuit 26 to become ₂ signals, and further inverted again by the NAND circuit 27 to become the G ₂ signal.
I get a signal. Therefore, the _G1 signal is connected to the NAND circuit A1,
A2, A3 and A7, A8, A9 and A13, A14
..., and the G ₂ signal is added to A4 of the NAND circuit,
A5, A6 and A10, A11, A12 and A16,
Join A17... And the output of F1 (Fig. 5
g ₁ ) and G ₁ signal are added to A1, and a scanning pulse signal for period T ₁ shown in FIG. 5 h ₁ is obtained from terminal ch ₁ in FIG. 3. In the same way, ch ₂ , ch ₃ then T ₃ ,
A scanning pulse signal of T ₅ period is obtained. next
NAND circuit A4 has the output of F4 (Fig. 5 g ₄ ) and
G ₂ signal (Fig. 5 c) is added, as shown in Fig. 5 i ₄ .
A scanning pulse of period _T8 is obtained from terminal _ch4 . Next, scan pulses for periods T ₁₀ and T ₁₂ are obtained from ch ₅ and ch ₆ in the same manner. Then, the pulse signal of the output of F7 for the period (T ₁₅ +T ₁₆ ) and the G ₁ signal are applied to the NAND circuit A7 again, and the scanning pulse signal for the period T ₁₅ is obtained from the terminal ch ₇ . Next, scan pulse signals for periods T ₁₇ and T ₁₉ are obtained from ch ₈ and ch ₉ in the same manner. Thereafter, similarly, three scanning pulse signal output terminals are grouped into one group, and the period of the output scanning pulse between adjacent channels within the group is 2T, but between the groups, the period of the output scanning pulse is 3T. Finally, the output of F30 becomes a pulse with a period of (T ₆₇ + T ₆₈ ), and the NAND circuit A
30 along with the G ₂ signal to obtain an even number of T ₆₈ period scan pulses. The output of the NAND circuit 23 is now “L” at the serial signal output terminal 17.
Therefore, the output pulse of F30 is F′10,D1
0, C10, and a pulse of period (T ₆₉ +T ₇₀ ) is obtained. This serial output signal is then applied to the serial input terminal 11 of the next-stage X electrode drive IC, _I2, as shown in FIG.

Next, we will explain the fourth condition, when displaying a television image with 625 scanning lines, and when the X electrode drive IC of FIG. 3 is placed on the right side of panel 1, as shown in 7 of FIG. 1. do. At this time, the left/right switching terminal 13 in Fig. 3 is set to "L" by the wiring shown in Fig. 6.
The 525/625 switching terminal 14 is at "H" as in the third state. Therefore, the output of NAND22 becomes "L" and the output of NAND23 becomes "H". Therefore, contrary to the third state described above, the outputs of inverter circuits E2, E4, E6, E8, and E10 become "L", and the outputs of NAND circuits D2, D4, D6, D8, and D
10 output is always "H". Therefore, FF circuit F6,
The outputs of F12, F18, F24, and F30 are NAND circuits B2, B4, B6, B8, and B10, respectively.
and further invert the NAND circuits C2 and C, respectively.
4, C6, C8, and C10, and the same outputs as F6, F12, F18, F24, and F30 are outputted to the next stage F7, F13, and F1, respectively.
9, F25 and the serial signal output terminal 17. On the other hand, now the output of the NAND circuit 22 is “L”
Therefore, NAND circuits B1, B3, B5, B7,
The output of B9 is always "H". Therefore, FF circuit F
The outputs of 3, F9, F15, F21, and F27 are respectively applied to FF circuits F'1, F'3, F'5, F'7, and F'9, and these outputs are respectively applied to NAND circuit D.
Invert at 1, D3, D5, D7, D9, and then
The same outputs as those of F'1, F'3, F'5, F'7, and F'9 are re-inverted by the NAND circuits C1, C3, C5, C7, and C9, respectively, and the outputs of the next-stage FF circuits F4 and F1
0, F16, F22, F28, and eventually FF circuits F1, F2, F3, F'1, F4, F
5,...F9,F'3,F10,F11...F15,
F'5, F16, F17...F21, F'7, F22,
F23...F27, F'9, F29, and F30 are connected in cascade in order to form a shift register. Then, the same G ₂ signal as in the third state is applied to the serial input terminal 11 and the clock signal input terminal 12, and the G ₂ signal is applied to the terminal 15 and 16, contrary to the third state. 16 is applied with the G ₁ signal. Since the serial input signal and clock signal are the same as in the third state, a pulse signal for the period ( _{T 1 +} T ₂ ) shown in Fig. 5 g ₁ is obtained from F 1, and then sequentially F 2 , F 3 , F′ 1 , F′4... from (T ₃ +
Pulses of periods T ₄ ), (T ₅ +T ₆ ), (T ₇ +T ₈ ), (T ₉ +T ₁₀ )... are obtained. On the other hand, 525/625 switching terminal 1
4 is “H”, so the _G1 signal at terminal 16 is
NAND circuits A4 and A via NAND26 and 27
5, A6 and A10, A11, A12 and A16, A
17, joins A18 and... Also, G ₂ of terminal 15
The signals are A1, A2, A3 and A7, A8, A9 and A
13, A14, A15 and so on. And F1
The output of (g ₁ in Fig. 5) and the G ₂ signal (c in Fig. 5) are added to A1, and the scanning pulse signal for period T ₂ shown in Fig. 5 i ₁ is obtained from terminal ch ₁ in Fig. 3. . Scanning pulse signals for periods T ₄ and T ₆ are obtained from ch ₂ and ch ₃ in the same manner. Next, the output of F4 (T ₉ + T ₁₀ )
The period pulse signal and signal _G1 signal are added to A4,
The scanning pulse signal for period _T9 is obtained from _ch4 . Then, scan pulse signals for periods T ₁₁ and T ₁₃ are obtained from ch ₅ and ch ₆ in the same manner. and then
The output pulse signal of F7 (T ₁₅ +T ₁₆ ) period and the G ₂ signal are added to the NAND circuit A7, and a scanning pulse signal of the T ₁₆ period is obtained from ch ₇ . In addition, scanning pulse signals for periods T ₁₈ and T ₂₀ are obtained from ch ₈ and ch ₉ in the same manner. Thereafter, the three scanning pulse signal output terminals are grouped into one group and operate in the same manner as in the third state. And finally the output of F30 is (T ₆₉
+T ₇₀ ) period pulse, NAND circuit B1
The same signal as the output of F30 is output to the serial signal output terminal 17 via F30 and C10. This serial output signal is then transmitted to the next stage as shown in Figure 6.
It is applied to the serial input terminal 11 of the electrode drive IC, _I6 .

Let us now consider the case where the X electrode drive IC shown in FIG. 3, which is the first embodiment of the present invention, is arranged as shown in FIG. The configuration is placed on the left side of panel 1.
Set the left and right switching terminals 13 of I ₁ , I ₂ , I ₃ , and I ₄ to "H",
Terminals 13 of I ₅ , I ₆ , I ₇ , and I ₈ placed on the right side are set to “L”
Wire it so that it looks like this. Then, a serial input signal as shown in FIG. 5f obtained from the inverter 21 shown in FIG. 4 is commonly applied to the terminals 11 of I ₁ and I ₅ . In addition _, the _G2 signal as shown in FIG _. 5c obtained from the Q output of the FF circuit 19 in _FIG . (not shown). Furthermore, each terminal 15 of I ₁ , I ₂ , I ₃ , and I ₄
and the respective terminals 16 of I ₅ , I ₆ , I ₇ , and I ₈ are commonly wired to apply the G ₁ signal. Also I ₁ , I ₂ , I ₃ , I ₄
The terminals 16 of each of the terminals 16 and the terminals 15 of each of the terminals I ₅ , I ₆ , I ₇ , and I ₈ are commonly wired to apply the G ₂ signal. Then, the 525/625 switching terminals 14 of I ₁ , I ₂ ... I ₈ shown in Fig. 6 are wired in common to switch 2.
8, when displaying a television image with 525 scanning lines, it is set to the "L" side, and when displaying a television image with 625 scanning lines, it is set to the "H" side. Further, the changeover switch 28 is linked to the program terminal 20 shown in FIG. With the arrangement, wiring, and control signal application shown in FIG. 6, television images with both 525 and 625 scanning lines can be displayed without any problem. The timing of this scanning is summarized in FIG. 7 as described in the above configuration. Figure 7 shows the output terminals _ch 1 of I ₁ and I ₅ for the X electrode drive IC, I ₁ and I ₅ in Figure 6.
~ch ₃₀ Wiring order and number of scanning lines for each X electrode
The timing using T shown in FIG. 5 is shown for 525 and 625 lines.

Other X electrode drive ICs, I ₂ , I ₃ , I ₄ , I ₆ , I ₇ , and I ₈ operate in the same way, and in the end, the ch ₃₀ output of I ₄ is wired to X 239, and the number of scanning lines is 525. When displaying the image of
A scanning pulse is output at T ₂₃₉ , and when the number of scanning lines is 625, a scanning pulse is output at T ₂₇₉ . on the other hand
The output of ch ₃₀ of I ₈ is wired to X ₂₄₀ and the number of scan lines is 525
When displaying an image of a book, a scanning pulse is output at T ₂₄₀ , and when the number of scanning lines is 625, a scanning pulse is output at T ₂₈₀ .

As explained above, by arranging the X electrode drive IC shown in FIG. 3, which is the first embodiment of the present invention, as shown in FIG. 6, a television image with 625 scanning lines can be displayed. It can be driven with only one type of IC shown in Fig. 3, without the need for continuous horizontal scanning or the use of two types of X-electrode drive ICs for left and right. In other words, switch 28 in FIG. 6 is set to "L".
to display an image with 525 scanning lines on the panel,
Next, when you want to display an image with 625 scanning lines on the panel, all you have to do is turn the switch 28 to "H".
Then, problems such as overscanning and distortion do not occur in the displayed image.

Next, as a second embodiment of the present invention, the number of scanning lines is 625.
A scanning circuit configured for this purpose and driving a panel having 288 X electrodes will be described.
Details of this X electrode drive circuit are shown in FIG. Third
The figure and FIG. 8 are compared, and corresponding parts are given the same numbers. The IC is inside the dashed line.
The IC in Figure 8 differs from the IC in Figure 3 in that it has 36 channels of output.
Also, the arrangement and wiring of the IC to the panel in Figure 8 are basically the same as in Figure 6, except that the total number of X electrodes is
The difference is that the number of lines is 288, and that the output of each of the X electrode drive ICs shown in I ₁ , I ₂ , . . . I ₈ is a 36-channel output. Serial input terminal 11, clock signal input terminal 12, left/right switching terminal 13,
And the control signals applied to terminals 15 and 16 are exactly the same as before, except that the signal applied to 525/625 switching terminal 14 is “H” when receiving 525 scanning lines, 625 Set to “L” when receiving a book.

Next, in the same four states as before,
The operation of the electrode drive IC will be explained. Assume that the first state is when a television image with 525 scanning lines is displayed and the IC shown in FIG. 8 is placed on the left side of the panel 1. At this time, as in the first embodiment, the terminal 13 is set to "H" and the terminal 14 is set to "H" by the switch 28 of FIG. 6 of the first embodiment. At this time NAND
The circuit 22 becomes "H" and the NAND circuit 24 becomes "L". Therefore, NAND circuits B1, B3, B5...B
11 is always “H”, NAND circuits D2, D4, D6
...D12 is also always "H". Then, the serial input signal shown in FIG. 5f at the terminal 11 is sequentially shifted by the clock signal shown in FIG. 5c at the terminal 12. That is, the output of F1 becomes g ₁ in FIG. 5, and the outputs of F2 and F3 become g ₂ and g ₃ in FIG. Then, the output of F3 is added to F4 via B1 and C1, and the output of F4 becomes the same as F3, g ₃ in Figure 5, and F
The outputs of 5 and F6 are g ₄ and g ₅ in Fig. 5. and F
The output of 6 is added to F7 via B2 and C2, and F
The output of 7 will be g ₆ . And the output of F8 and F9 is
g ₇ and g ₈ , and the output of F10 is g ₈ , which is the same as F9.

In this way, the output of F35 is sequentially shifted and outputted to the serial signal output terminal 17 via D12 and C12. Figure 5d of terminals 15 and 16,
The G ₁ and G ₂ signals shown in c are the same as in the previous third state,
G ₁ signal is NAND circuit A1, A2, A3, A7,
A8, A9, A13..., _G2 signal is A4, A5,
It is added to A6, A10, A11, A12, A16... Then, to ch ₁ , the pulse of the F1 output during the (T ₁ + T ₂ ) period shown in Fig. 5 g ₁ and the G ₁ signal shown in Fig. 5 d are applied to the NAND circuit A1, so the signal shown in Fig. 5 h ₁ is applied to channel 1. A scanning pulse signal of T ₁ period is obtained, and
Scanning pulses for periods T ₃ and T ₅ are obtained on ch ₂ and ch ₃ . In addition, to ch ₄ , the pulse of the F4 output during the (T ₅ + T ₆ ) period shown in Fig. 5 g ₃ and the G _{2 signal shown in Fig. 5 c are added to the NAND circuit A4, so the G 2} signal shown in Fig. 5 i ₃ is applied.
A scanning pulse of T ₆ duration is obtained. From then on, in the same way, ch ₅ , ch ₆ , ch ₇ , ch ₈ ... have T ₈ , T ₁₀ ,
Scanning pulses of periods T ₁₁ , T ₁₃ . . . are obtained. As shown in FIG. 6, the outputs of these channel terminals are sequentially applied to each X electrode, such as X ₁ for ch ₁ , X ₃ for ch ₂ , X ₄ for ch ₃ , and so on.

Next, consider a second situation in which a television image with 525 scanning lines is displayed and the IC shown in FIG. 8 is placed on the right side of the panel 1. At this time, the terminal 13 is set to "L", contrary to the first state. terminal 1
4 is "H" as before. Also terminals 15, 16
In contrast to the first state, the G ₂ signal is applied to terminal 15,
A G ₁ signal is applied to terminal 16. And NAND
Circuits D1, D3, D5...D11 and B2, B4,
The outputs of B6...B12 are always "H", contrary to the first state. Therefore, the outputs of F1, F2...F6 become the pulse signals shown in Fig. 5 g ₁ , g ₂ ... g ₆ , and the output of F7 becomes the same as the output of F6, g ₆ in Fig. 5, since the output of F5 is added to F7. . And in the output of ch ₁ ,
Since the pulse of the output of F1 in the period (T ₁ +T ₂ ) shown in FIG. 5 g ₁ and _the G ₂ signal shown in _FIG . A scanning pulse is obtained. After that, scanning pulses of T ₄ and T ₆ periods are obtained in ch ₂ and ch ₃ , and in ch ₄ , the output of F4 is sent to NAND circuit A4 as shown in Fig. 5 g ₄ (T ₇ + T ₈ ).
Since the period pulse and the G ₁ signal shown in FIG. 5d are added, a scanning pulse of period T ₇ is obtained. Thereafter, in the same way, ch ₅ , ch ₆ , ch ₇ , ch ₈ ... are set to T ₉ ,
Scanning pulses of periods T ₁₁ , T ₁₂ , T ₁₃ . . . are obtained.
As shown in FIG. 6, the outputs of these channels are sequentially applied to each X electrode, such as X ₂ for ch ₁ , X ₄ for ch ₂ , X ₆ for ch ₃ , and so on.

Next, consider a third state in which a television image with 625 scanning lines is displayed and the IC shown in FIG. 8 is placed on the left side of the panel. At this time, the left and right switching terminals 13 are wired so as to be at "H" as in the first state. Then, the 525/625 switching terminal 14 is set to "L" with the switch 28, contrary to when 525 is connected.
Make it. Also, since the signals applied to terminals 15 and 16 are the same as in the first state, the signals applied to terminal 15 are the same as in the first state.
G ₁ signal, G ₂ signal is applied to terminal 16. Also terminal 1
As explained in FIG. 3 of the first embodiment, the serial input signal applied to the programmable counter 18 in FIG. 4 is set to 625 scanning lines by setting the switch 28 to "H". At this time, the NAND circuits 22 and 23 become "H", and the NAND circuits D1 and
D2...D12 is always "H", so simply F
1, F2, F3, F4...F36 are connected in cascade. Since the NAND circuit 26 becomes "H" again, the output of the NAND circuit 27 becomes the _G1 signal applied to the terminal 15. Therefore ch ₁ , ch ₂ , ch ₃ , ch ₄
..., T ₁ , T 3 , h ₄ shown in Figure 5 h ₁ , h ₂ , h ₃ , h ₄ ...
Scanning pulses of periods T ₅ , T ₇ . . . are obtained.

Next, in the fourth state, when displaying a television image with 625 scanning lines, the IC shown in Figure 8 is connected to panel 1.
Consider placing it on the right side of . At this time, the left/right switching terminal 13 is wired to be in the second state, which is also "L", and the 525/625 switching terminal 14 is wired to be "L" at the switch 28, which is the same as in the third state. Set it to “L”. Also, since the signals applied to terminals 15 and 16 are the same as in the second state,
A G ₂ signal is applied to terminal 15 and a G ₁ signal is applied to terminal 16.
Furthermore, the serial input signal applied to terminal 11 is the same as in the third state. In this fourth state, the same operation as in the third state is performed, but the difference from the third state is that the G ₂ signal is applied to the terminal 15.
The outputs of ch ₁ , ch ₂ , ch ₃ , ch ₄ ... in Figure 5 i ₁ , i ₂ ,
Scanning pulses of periods T ₂ , T ₄ , T ₆ , T ₈ , etc. shown in i ₃ , i ₄ , and so on are obtained.

Next, the X electrode drive IC shown in FIG. 8, which is the second embodiment, is arranged in the same manner as the arrangement shown in FIG. 6 in the first embodiment. At this time, the difference from the one shown in Fig. 6 is that, as mentioned above, the total number of X electrodes is 288,
The output of each of the electrode drive ICs, I ₁ , I ₂ ... I ₈ is 36 channel output, and contrary to the first embodiment, the output of each of I ₁ , I ₂ ... I ₈ is 525/625. Switching terminal 1
4, when displaying a television image with 525 scanning lines using the switch 28, set the number of scanning lines to the "H" side.
“L” to display 625 television images
to the side.

With the above arrangement and wiring, the number of X electrodes is configured to display a television image with 625 scanning lines.
Even with 288 panels, television images with 525 scanning lines can be displayed without any problems with a single switch. The scanning timing at this time is shown in FIG. 9, similar to FIG. 7 in the first embodiment.

Other X electrode drive ICs shown in FIG. 8, I ₂ , I ₃ , I ₄ ,
I ₆ , I ₇ , and I ₈ operate in the same way, and finally I ₄ and I ₈
The ch36 output is wired to X ₂₈₇ and X ₂₈₈ respectively, and when the number of scanning lines is 625, the scanning pulse is output at T ₂₈₇ and T ₂₈₈ , and when the number of scanning lines is 525, the scanning pulse is output at T ₂₄₁ and T ₂₄₂ . .

In this way, the second embodiment of the present invention, the X-electrode drive IC shown in FIG. This is possible in the same way as in the first embodiment without using two types of X-electrode drive ICs dedicated to the left and right sides. By simply changing the switch 28, television images with both 525 and 625 scanning lines can be displayed without underscanning or image distortion.

The effects of the circuit of the present invention described above are as follows. In other words, one effect is that although every other input terminal that applies a scanning signal to the X electrodes is distributed to the left and right to drive a panel, the X electrode drive IC of the present invention can be placed on either the left or right side of the panel. For example, when placing the drive IC on the left side of the panel, set the left/right switching terminal to "H".
On the other hand, when placed on the right side, the effect can be achieved by simply setting it to "L". This allows left and right drive
There is no need to create an IC.

Also, as is clear from FIGS. 7 and 9, the number of scanning lines is 625 in the first embodiment and 525 in the second embodiment.
At this time, the order of the scanning pulses may be skipped by one, or the order of the scanning pulses may be delayed by one, but the entire display screen is scanned evenly without being concentrated in one place, so there is no unnaturalness on the display screen.

In the first embodiment of the invention, the number of scanning lines is
The explanation was given using an example of an X-electrode drive IC that can display television images with 625 scanning lines on a panel configured for 525 lines, but it is also possible to display images with other different numbers of scanning lines, such as in France. It is clear that when doing so, all you need to do is to use the same idea and change the number and position of the FF circuits F' to be added in FIG. It is also clear that the same thing as above holds true in the second embodiment of the present invention.

_Yet another effect of _the present invention is that X
When driving a panel, every other input terminal that applies scanning signals to the electrodes is distributed to the left and right.
The number of FF circuits F1, F2, . . . can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an XY matrix panel to which the present invention is applied, in which input terminals for applying scanning signals to row electrodes X are provided separately on the left and right, and the circuitry necessary to display an image on this panel. , FIG. 2 is a diagram showing signal waveforms of various parts to explain a conventional drive circuit that drives a panel that is the subject of the present invention, and FIG. 3 is a diagram showing an X electrode drive IC according to an embodiment of the present invention. Figure 4 shows a circuit for generating a signal to be applied to the IC in Figure 3, Figure 5 shows the circuit shown in Figure 3,
Figure 4 shows the signal waveforms of each part to explain the operation of the circuit shown in Figure 6. 7 is a diagram showing the timing of scanning at that time; FIG. 8 is a diagram showing an X electrode drive IC according to another embodiment of the present invention; Figure 9 is the 8th
FIG. 3 is a diagram showing scan timing when using the X electrode drive IC shown in the figure. 1...XY matrix panel, 11...serial signal input terminal, 12...clock signal input terminal, 1
3...Left and right switching terminal, 14...525/625 switching terminal,
15, 16...First and second gate signal input terminals, 17...Serial signal output terminal, 18...Programmable counter, 19...FF, 28...Switch,
I ₁ ~ _{I 8} ...X electrode drive IC, F1 ~ F36, F' ~ F'1
0...FF circuit, A1-A36...NAND circuit.

Claims (1)

[Claims] 1. An input terminal for applying a scanning signal to the row electrode
In a circuit for driving an XY matrix panel configured to be distributed to the left and right sides, the first circuit constitutes a shift register for sequentially generating scanning pulses and is wired to the input terminals distributed to the left and right sides. a group of flip-flops, a group of gates for controlling respective outputs of the first group of flip-flops with a first control signal or a second control signal, and a circuit for changing the cascade connection order of the first group of flip-flops, A first switching terminal for switching depending on whether the first flip-flop group is placed on the left or right side of the panel, and a second switching terminal for switching depending on the number of scanning lines of an image to be displayed on the panel.
A matrix panel drive circuit characterized by having a switching terminal. 2. The first flip-flop group is composed of N second flip-flop array groups corresponding to the X electrodes, M third and M fourth flip-flops,
For every certain A number of second flip-flops, one third and one fourth flip-flop are arranged alternately after the second flip-flop, and the second and third flip-flops are controlled by the first switching terminal. flip-flops are cascaded in the order in which they are arranged to form a (N+M) stage shift register, or the second and fourth flip-flops are cascaded in the order in which they are arranged to form a (N+M) stage shift register.
By controlling the second switching terminal, regardless of the control of the first switching terminal, only the second flip-flops are cascaded in the order in which they are arranged to form a shift register of N stages. The matrix panel drive circuit according to claim 1, wherein the matrix panel drive circuit constitutes a register. 3. Each of the first flip-flop groups corresponds to the X electrodes of the panel, and the first flip-flop group is connected to the R fifth flip-flop array group, S sixth flip-flops, and S seventh flip-flops. For every certain B number of fifth flip-flops, one sixth and seventh flip-flops are arranged alternately after the fifth flip-flop, and the fifth and seventh flip-flops are controlled by the first switching terminal. 6
flip-flops are cascaded in the order in which they are arranged to form a (R+S) stage shift register, or fifth and seventh flip-flops are cascaded in the order in which they are arranged to form a (R+S) stage shift register.
S) Select whether to configure a stage shift register,
A claim characterized in that, under the control of the second switching terminal, regardless of the control of the first switching terminal, only the fifth flip-flops are cascade-connected in the order in which they are arranged to constitute an R-stage shift register. The matrix panel drive circuit according to item 1. 4. The matrix according to claim 1, further comprising means for controlling the time delay of the data signal applied to the first stage of the shift register with respect to the vertical synchronization signal in accordance with the selection of the second switching terminal. Panel drive circuit.