JPS63129325U - - Google Patents

Info

Publication number
JPS63129325U
JPS63129325U JP2161487U JP2161487U JPS63129325U JP S63129325 U JPS63129325 U JP S63129325U JP 2161487 U JP2161487 U JP 2161487U JP 2161487 U JP2161487 U JP 2161487U JP S63129325 U JPS63129325 U JP S63129325U
Authority
JP
Japan
Prior art keywords
display
frequency
clock
display device
preset data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2161487U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2161487U priority Critical patent/JPS63129325U/ja
Publication of JPS63129325U publication Critical patent/JPS63129325U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図は上記実施例におけるデイジタル表示器の
表示面を示す概略図、第3図は上記実施例におけ
るマイクロコンピユータの動作のフローチヤート
を示す図である。 1……チユーナ、2……マイクロコンピユータ
、3……デイジタル表示器、4……プリセツトメ
モリ、5……表示ドライバ、6……RAM、7…
…クロツク発振器、8……時計表示用ボタン、9
……周波数プリセツト用ボタン。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a schematic view showing the display surface of the digital display in the above embodiment, and FIG. 3 is a flowchart of the operation of the microcomputer in the above embodiment. 1... Tuner, 2... Microcomputer, 3... Digital display, 4... Preset memory, 5... Display driver, 6... RAM, 7...
...Clock oscillator, 8...Clock display button, 9
...Button for frequency preset.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マイクロコンピユータ等を内蔵した電子同調ラ
ジオ受信機における表示装置であつて、選択的に
周波数表示又は時計表示を行い、かつ周波数表示
の際プリセツトチヤンネル等のプリセツトデータ
を表示する構成の表示装置において、周波数表示
から時計表示への切換を検出して時計表示と共に
プリセツトデータを表示するように構成したこと
を特徴とする表示装置。
A display device in an electronically tuned radio receiver with a built-in microcomputer, etc., which selectively displays a frequency or a clock, and displays preset data such as a preset channel when displaying the frequency. A display device characterized in that it is configured to detect switching from frequency display to clock display and display preset data together with the clock display.
JP2161487U 1987-02-17 1987-02-17 Pending JPS63129325U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2161487U JPS63129325U (en) 1987-02-17 1987-02-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2161487U JPS63129325U (en) 1987-02-17 1987-02-17

Publications (1)

Publication Number Publication Date
JPS63129325U true JPS63129325U (en) 1988-08-24

Family

ID=30818216

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2161487U Pending JPS63129325U (en) 1987-02-17 1987-02-17

Country Status (1)

Country Link
JP (1) JPS63129325U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003107179A (en) * 2001-09-28 2003-04-09 Yamaha Corp Audio visual device with timer function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003107179A (en) * 2001-09-28 2003-04-09 Yamaha Corp Audio visual device with timer function

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