JPS63127379A - Bit map depicting device - Google Patents

Abstract

PURPOSE:To perform data transfer required for area swapping, etc., at high speed, by providing plural memory address generators provided with two data buses and which designate an area in a source or a destination plane to one of the two address buses. CONSTITUTION:Plural bit map memory planes 30-i are connected to a memory bus 50. The mutliplexer(MUX)32 of the plane 30-i selects address buses 52a and 52b, and the MUX33 selects control buses 53a and 53b. In a computing element ALU35, the data 51a or 51b and a memory block 31 are connected to the input side of the element, and whose output side is connected to a bus 51b or 51a. A control processor sets the address generators 62 and 63 so as to generate addresses setting a memory area that is a source area as an object, and the address generator 64 so as to generate the address setting the memory area that is a destination area as the object. Thus, it is possible to transfer data required for the area swapping, etc., at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a bitmap drawing device having a plurality of bitmap memory planes.

(Prior Art) In a bitmap drawing device using a bitmap memory, such as Bitmap Display II, the 10th
As shown in the figure, bitmap memory plane 11-1
~11-n memory bus 12 is one data bus 13
, one address bus 14 , and one control bus 15 . In a bitmap drawing device having such a configuration, a plurality of memory planes 11-1 to 11-n
Even if the
Typically, only one memory plane could operate. Furthermore, even if a plurality of memory planes were allowed to operate, all of these memory planes could only perform the same memory operation (memory write operation) within one memory cycle. That is, for example, while the memory plane 11-1 is performing a memory read operation, the memory plane 1
1-2 could not perform a memory write (read-modify-write) operation.

Therefore, assuming that memory plane 11-1 is a character font registration brain and memory plane 11-2 is a display brain, character fonts are copied from memory plane 11-1 to memory plane 11-2 (between brains). (copy), once (one word)
As shown in FIG.
A memory read cycle in which a memory read operation is performed using -1 as the source plane, and a memory plane 11-2.
This was a problem because it required two memory cycles for a memory write operation to be performed with the memory plane as the destination plane.

In addition, in recent years, bitmap drawing devices have been using ternary operations (
It often occurs that a logical sieve between memory existing content PO1, drawing image content P1, and drawing mask pattern 212 is performed. This ternary operation was performed in the conventional bitmap drawing device shown in FIG. 10 as follows. It is now assumed that the existing memory contents are stored in the memory plane 11-1, the drawing image contents are stored in the memory plane 11-2, and the drawing mask pattern is stored in the memory plane 11-n. In this case, as shown in FIG. 12, the memory plane 11-n is, for example, a source plane,
For example, a binary operation between branes with the memory plane 11-2 as the destination plane (in FIG. 12, AN
D operation) is performed first. Next, memory plane 1
A binary operation (OR operation in FIG. 12) is performed between the brains, with 1-2 as the source plane and memory plane 11-1 as the destination plane. In this way, in the conventional bitmap drawing 81, a ternary operation is realized by repeating a binary operation at least twice.
There was a problem with slow data transfer speed. Furthermore, in order to solve this problem, a method has been considered in which the drawing mask pattern is prepared as a fixed value in a register or the like, thereby making it unnecessary to read out the drawing mask pattern from the memory plane. However, this method has a problem in that the drawing mask pattern is limited.

(Problems to be Solved by the Invention) As mentioned above, in conventional bitmap drawing devices, the source brain and destination plane cannot operate in the same memory cycle, so data transfer between brains is required for copying between memory planes, etc. There was a problem that the speed could not be increased.

In addition, in conventional bitmap drawing devices, two source brains cannot operate in the same memory cycle, so
There was also the problem that data transfer between branes, which is necessary for term operations, could not be made faster.

The present invention has been made in view of the above circumstances, and its purpose is to enable at least one source brain and destination plane, and even two source brains, to operate in the same memory cycle, thereby allowing inter-brain data to be An object of the present invention is to provide a bitmap drawing device that can speed up transfer.

[Structure of the invention] (Means and effects for solving the problem) In this invention,
Two data buses, two address buses, and two control buses (two systems) of the memory bus are provided. Within the plurality of bitmap memory planes connected to this memory bus, there are a first multiplexer for switching between two address buses, a second multiplexer for switching between two control buses, and a second multiplexer for switching between two address buses. a first flip 70 for controlling two multiplexers; a memory block addressed in accordance with the outputs of the first and second multiplexers;
, data on one of the two data buses as the second input, and data on the other of the two data buses as the third input; A three-input arithmetic unit whose output is connected to the data input/output terminal of the memory block, a pipeline register that temporarily holds data read from the memory block, and a pipeline register that transfers the data held in the pipeline register to the two data buses mentioned above. a driver means for outputting to either one of the above, and a 27th lip flop for instructing the output destination of this driver means,
Each is provided. Further, in the present invention, there is provided a main control means for selecting and specifying a source and destination plane from the plurality of bitmap memory planes, and a memory data control means for controlling data transfer between the memory planes selected and specified by the main control means. The transfer burial circuit is provided with a memory data transfer control circuit having at least two address generators for generating a memory address specifying a source or destination plane area on one of the two address buses.

According to the above configuration, one of two address buses and two control buses is used to perform a memory read operation of one or two source planes, while the other is used to perform a memory write operation of a destination plane. can be done. Furthermore, memory read operations for two source brains can be performed using two data buses, two address buses, and two control buses.

(Embodiment) FIG. 1 shows a block configuration of a bitmap drawing device according to an embodiment of the present invention. In the figure, 21 is a control processor that controls the entire device, and 22 is a control processor 2.
1 is a system bus, and 23 is a host interface which is a communication interface with a host computer (not shown). 30-1.

30-2...30-n are bitmap memory planes (hereinafter simply referred to as memory planes) used for storing display images, kanji characters, symbols, etc., 41 is a display monitor, and 42 is a memory plane 30. -1~30-n
This is a display control circuit that performs display control to display the contents of on the display monitor 41.

50 is a memory bus for the memory planes 30-1 to 30-n; 60 is a memory bus for the control processor 21 to connect to the memory plane 30-1;
This is a memory data transfer control circuit that performs control for accessing the memory planes 30-1 to 30-n, data transfer control between the memory planes 30-1 to 30-0, and the like. The memory bus 50 includes two (two systems) data buses 51a and 51b used for transferring memory data, two address buses 52a and 52b used for transferring memory addresses, and a read request signal and a write signal. It consists of two control buses 53a and 53b used for transferring various memory control signals such as (read-modify-write) request signals.

FIG. 2 shows the memory plane 30-i (t −i
.

2...n), and 31 is a memory block having a RAM configuration, for example. A multiplexer 32 selects either the address bus 52a or 52b as the address bus for the memory block 31
33 is a MUX (multiplexer) that selects either one of the control buses 53a or 53b as the control bus for the memory block 31; 34 is a flip 70 tube (hereinafter referred to as MtJX) that outputs a selection control signal for MLJX 32, 33; , F/F). Also, M.L.
The outputs of IX32.33 are connected to the address input port (ADDRESS) and control signal input port (CONTROL) of the memory block 31, respectively. 35 is a three-input arithmetic unit which receives input data from the data bus 51a as a left input, input data from the data bus 51b as a center input, and receives read data from the memory block 31 (existing data in the memory block 31) as a right input. (Hereinafter, AL
36 is a vibe line register (R) that temporarily latches read data from the memory block 31. The output of the ALU 35 is connected to the data input/output port (DATA>) of the memory block 31.

37 is a driver circuit that outputs the data held in the register 36 to either data bus 51a or 51b in a memory read cycle; 38 is a driver circuit 37;
This is an F/F (flip-flop) that specifies the output destination. This F/F 38 and the above F/F 34
is operated (set/reset) by the control processor 21 via the system bus 22 in FIG.

FIG. 3 shows a block configuration of the memory data transfer control circuit 60 of FIG. 1. In the figure, 61 is a transfer control circuit that controls data transfer between memory planes 30-1 to 30-0, and 62 to 64 are memory planes 30-1 to 30-3.
This is an address generator that generates an address of an arbitrary rectangular area of a memory plane designated as a source or display plane among 0 to n. Address generators 62 to 64 can be connected to any of address buses 52a and 53b according to instructions from control processor 21. However, in FIG. 3, the address generator 62.
64 is shown connected to the address bus 52a, and an address generator 63 is connected to the address bus 52b.

Next, the operation of one embodiment of the present invention will be explained below.
Contents of memory area A consisting of 0-1, memory plane 3
Taking as an example the case where the contents of another memory area 0-2 [B and the contents of another memory area [C] are written to the memory plane 30-n,
This will be explained with reference to the operation diagram shown in FIG. 4 and the timing chart shown in FIG.

First, the control processor 21 instructs the address generators 62 and 63 of the memory data transfer control circuit 60 to generate a source address (memory read address) for the memory areas 1iiiA and B, which are source areas. A set-up operation is performed for each generator 64 via the system bus 22 so as to generate a destination address (memory write address) for the memory area C, which is the destination area. is the memory plane 30-
1.30-n, the address bus 52a and control bus 5 are used as the address bus and control bus for the memory block 31, respectively.
The same brane 30-1 is selected such that 3a is selected by MUXs 32 and 33.

Each F/F 34 in 30-n is operated (for example, set operation), and in memory plane 30-2, address bus 52b and control bus 53b are selected as the address bus and control bus of memory block 31 by MUX 32 and 33. F/F 3 in the same plane 30-2
4 (for example, a reset operation).

Next, the control processor 21 connects only the memory plane 30-1, 30-2, which is the source plane, to the data bus 51a among the memory planes 30-1, 30-2, . . . 30-n.
Alternatively, data output (data read output) to 51b is permitted, and all other memory planes are set to a data output prohibited state. At this time, the control processor 21 controls the data bus 51a for the memory plane 30-1.
The same plane 30-1 is used to output data to
Reset F/F 38 in memory plane 3
For 0-2, the F/F in the same plane 30-2 is connected so that data is output to the data bus 51t).
Set 38. The control processor 21 also controls the memory plane 30 which is the destination plane among the memory planes 30-1, 30-2...30-n.
Only -n is allowed to write to the memory block 31, and all other memory planes are set to a write-inhibited state. Furthermore, the control processor 21 uses a memory plane 3, which is a destination plane, for ternary operations.
A L tJ 35 calculation modes within 0-n (AND,
OR, EXOR, etc.) (7) Make settings.

Note that registers for specifying read output prohibition/enable, write prohibition/permission, and operation mode are omitted in FIG.
The control processor 21 sets the control processor 21 .

When the control processor 21 completes the above setting operation, it transfers a command instructing the above-mentioned ternary operation to the transfer control circuit 61 of the memory data transfer control circuit 60 via the system bus 22, and starts data transfer. . As a result, the transfer control circuit 61 performs the fifth transfer based on the above command.
Each part is controlled so that the data transfer shown in the timing chart in the figure is performed. That is, the transfer control circuit 61 outputs a read request signal to the unillustrated memory read request signal lines of the control buses 53a and 53b every other memory cycle, and outputs a read request signal to the unillustrated memory write request signal lines of the control buses 53a and 53b. outputs a memory write request signal during a memory cycle in which the read request signal is in an OFF state. Further, the transfer control circuit 61 receives the following information from the address generators 62 and 63.
The source address (memory read address) targeting memory areas A and B is updated and output every two memory cycles, and the destination address (memory write address) targeting memory area *C is output from the address generator 64.
is updated and output every two memory cycles.

Under the control of the transfer control circuit 61, the source address and destination address updated and outputted from the address generators 62 and 64 every two memory cycles are sent to the address bus 52a alternately every memory cycle as shown in FIG.
will be sent to. The address on this address bus 52a is led to the memory plane 30-1.
address input port. Furthermore, various memory control signals on the control bus 53a are guided via the MUX 33 to the control signal input ports of the memory blocks 31 in the memory planes 301.30-n. As a result, in the memory plane 30-1 where read output is permitted and writing is prohibited, a memory read operation targeting the memory block 31 is performed every other memory cycle.

In addition, in the memory plane 30-n where readout is prohibited and writing is permitted, the memory block 3
A memory write (read modify write) operation targeting 1 is performed during a period when memory plane 30-1 is not in a read cycle.

On the other hand, the source address updated and output from the address generator 63 every two memory cycles is sent to the address bus 52b. The source address on this address bus 52k) is guided to the memory plane 30-2, selected by the MuX 32 in the same plane, and supplied to the address input port of the memory block 31.

Further, various memory control signals on the control bus 53i) are guided to the control signal input port of the memory block 31 in the memory plane 30-2 via the MUX 33. As a result, in the memory plane 30-2 where read output is permitted and self-programming is prohibited, a memory read operation targeting the memory block 31 is performed on the memory plane 30-2.
It is performed every other memory cycle at the same timing as 0-1.

By the memory read operation in the memory plane 30-1.30-2, data is read from each memory block 31 in the memory plane 30-1.30-2, for example, in memory cycle T1 shown in the timing chart of FIG. is for each register 3 at the end of the same cycle T1.
6 and output onto data buses 51a and 5Ib during the next memory cycle T2.

The data on the data buses 51a and 5Ib (read data from the memory planes 30-1 and 30-2) is transferred to the A L of the memory plane 30-n during the memory cycle T2.
Supplied to the left and center inputs of LJ 35. In this memory plane 30-n, the read-modify-write operation is performed as described above. Details of this read-modify-write operation are shown below.

In the memory plane 30-n, for example, in the first half of the memory cycle T2, a memory read operation targeting the memory block 31 is performed, and the read data is latched by a latch circuit (not shown) and input to the right input of the ALU 35. Supplied. ALU in memory plane 30-n
35 is the read data in memory cycle 1 from the memory plane 30-1.3O-2 (memory block 31) supplied to its left input and right input, respectively, and the memory supplied to its right input. Plain 30
-n (memory block 31) in memory cycle T2 (the first half of), and performs a ternary operation specified in advance by the control processor 21. ALU 3 in memory plane 30-n
The output data from 5 (3 term'a calculation result) is the same brane 3.
0-n memory block 31 (data input/output port)
guided by. In this memory plane 30-n,
In the second half of the same memory cycle T2, memory block 31
A memory write operation is performed targeting . As a result, the output data from the ALLI 35 in the memory plane 30-n is written to the memory block 31 of the same plane 30-2.

As described above, according to this embodiment, the memory read cycle that targets the memory plane 30-1, 30-2 that is the source brain, and the memory write cycle that targets the memory plane 30-2 that is the destination plane.
A one-word ternary operation transfer can be performed in two memory cycles including a read-modify-write cycle.

Now, in the ternary operation transfer between the three brains mentioned above, the memory plane 30-1゜30-2 which is the source brain
If both can use a common source address, address generator 64 is not needed.

The ternary operation transfer in this case is explained in the operation explanatory diagram in Fig. 6 and in Fig. 7.
This will be explained with reference to the timing chart shown in the figure.

Note that when the memory planes 30-1 and 30-2, which are source planes, can use a common source address, for example, the memory plane 30-2 is used as a dedicated brain for storing drawing mask patterns, and the memory plane This is the case, for example, when a drawing mask pattern is read using only the lower few bits of the source address (on the address bus 52a) for 30-1. If the size of the image to be read from the memory plane 30-1 is 2n times as large as the drawing mask pattern, the above mask pattern read operation may be repeated 2n times.

Memory plane 30-1゜30- which is the source brain
In a ternary transfer where Ill 1m processor 21 can use a common source address, Ill 1m processor 21
The address generator 62 of the memory data transfer control circuit 60 generates a source address (memory read address) targeting the source area, and the address generator 63 generates a destination address targeting the destination area. A setup operation is performed to generate a nation address (memory write address). Further, the control processor 21 controls the memory plane 30-1.30-2 so that both the address bus 52a and the control bus 53a are selected in the memory plane 30-1.30-2.
/ F 34 respectively, and memory plane 30-
F/F3 in the same brain 30-n so that address bus 52b and control bus 53b are selected in
Operate 4. Other setting operations are the same as in the previous embodiment.

Memory plane 30-1゜30- which is the source plane
For ternary transfers when 2 can use a common source address, the memory plane 30-1.30-
2 repeats a memory read cycle in response to a read request signal output from the transfer control circuit 61 to the control bus 53a, and the memory plane 30-n repeats a memory read cycle in response to a write request signal output from the transfer control circuit 61 to the control bus 53b. Repeat the memory write cycle (repeat modify write cycle). For example, in memory cycle T1 shown in the timing chart of FIG. 7, each memory block 31 of memory plane 30-1, 30-2 (
The data read out (based on the source address indicated by the address generator 62 and the lower several bits of the same address) is read from the memory block 31 of the memory plane 30-n (based on the source address indicated by the address generator 63) in the first half of the next memory cycle T2. A ternary operation is performed with the read data (based on the destination address indicated), and in the second half of the same cycle T2,
It is written into the memory block 31 of the memory plane 30-n (based on the destination address indicated by the address generator 63). In addition, in this cycle T2, based on the next source address from the address generator 62 and the lower several bits of the same address, the memory plane 30-
1. The memory block 31 in 30-2 is read accessed, and the memory plane 30-2 is accessed in the next cycle T3.
The data supplied to n is read. That is, according to this embodiment, the memory plane 30- which is the source brain
1. Memory read operation targeting 30-2 and memory write (read modify write) targeting memory plane 30-0, which is the destination plane
Operations are executed simultaneously in a pipeline. For this reason,
In effect, only one memory cycle is required to transfer one word of data. In other words, the ternary operation transfer is
It can be executed in memory cycle/1 word.

Finally, regarding the swap operation between memory planes, we will explain the operation in FIG. 8, taking as an example a case where images of a memory area of the memory plane 30-1 and another memory area E of the memory plane 30-2 are exchanged. This will be explained with reference to the timing charts shown in FIGS. First, the control processor 21 performs a setup operation on the address generators 62 and 63 of the memory data transfer control circuit 60 to generate an address (source/destination address) for the memory area E. The control processor 21 also controls the memory plane 30-1 so that the address bus 52a and the control bus 53a are selected in the memory plane 30-1, and the address bus 52b and the control bus 53b are selected in the memory plane 30-2. ．．
Operate each F/F 34 in 30-2.

Next, the control processor 21 controls the memory planes 30-1, 30-n of the memory planes 30-1, 30-2, and 30-n.
2 is set to permit data read output and write, and to output read data from memory planes 30-1 and 30-2 to data buses 51b and 51a.

The control processor 21 also changes the operation mode of the ALU 35 in the memory plane 30-1 to the input pass-through mode (that is, the mode in which the data on the data bus 51a is output as is to the memory block 31).
The calculation mode of the ALU 35 in -2 is set to the central input through mode (that is, the mode in which the data on the data bus 51b is output as is to the memory block 31).

When the control processor 21 completes the above setting operation, it transfers a command instructing the above-described inter-memory plane swap operation to the transfer control circuit 61 of the memory data transfer control circuit 60, and starts data transfer. As a result, the transfer control circuit 61 controls each section based on the above command so that the data transfer shown in the timing chart of the ninth factor is performed. That is, the transfer control circuit 61
A read request signal is output to the unillustrated memory read request signal lines of the control buses 53a and 53b every other memory cycle, and the read request signal is turned off to the unillustrated memory write request signal lines of the control buses 53a and 53b. During the memory cycle in the state, a memory write request signal is output, and the memory plane 30-1, 30-2 is caused to perform a memory read operation and a memory write operation alternately every memory cycle. Further, the transfer control circuit 61 causes the address generators 62 and 63 to update and output the source/destination address for the memory area E every two memory cycles.

Now, due to the memory read operation in the memory plane 30-1, the data read from the memory block 31 of the memory plane 30-1 in the memory cycle T1 shown in the timing chart of FIG. 9, for example, is transferred during the next memory cycle T2. It is led to the central input of the ALU 35 in the memory plane 30-2 via the data bus 51b, passes through the ALU 35, is led to the memory block 31, and is written into the block 31. Conversely, data read from memory block 31 of memory plane 30-2 in memory cycle T1 is led to the left input of ALLJ35 in memory plane 30-1 via data bus 51a during the next memory cycle T2. , same AL
It passes through U 35 and is guided to memory block 31 and written into the same block 31. As a result, a swap operation between planes is executed in 2 memory cycles/1 word.

[Effects of the Invention] As detailed above, according to the present invention, at least one source plane and a destination plane can operate in the same memory cycle, and two source planes can operate in the same cycle. Therefore, it is possible to speed up inter-plane data transfer required for copying between memory planes, ternary operations between three planes, and swapping areas between memory planes.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bitmap drawing device according to an embodiment of the present invention, FIG. 2 is a block diagram of the memory plane of FIG. 1, and FIG. 3 is a block diagram of the memory data transfer control circuit of FIG. 1. Configuration diagram, Figure 4 is an explanatory diagram of operation of ternary operation when three address generators are used, Figure 5 is a timing chart for ternary operation when three address generators are used, Figure 6 is an explanatory diagram of the operation of a ternary operation when two address generators are used, Figure 7 is a timing chart for a ternary operation when two address generators are used, and Figure 8 is an illustration of swap between memory planes. Operation explanatory diagram, FIG. 9 is a timing chart 1-1 when swapping between memory planes, FIG. 10 is a block configuration diagram showing a conventional example, FIG. 11 is a timing chart explaining a conventional copy between memory planes, and FIG. 12 is a diagram explaining a conventional ternary operation. 21... Control processor, 22... System bus,
30-1 to 30-n...Memory plane (bitmap memory plane), 31...Memory block, 32
．． 33...Multiplexer (MUX), 34.38
... Flip 70 tube (F/F), 35 ... 3-input arithmetic unit (ALU), 36 ... Vibration line register (
R), 37... Driver circuit, 50... Memory bus, 51a, 51b... Data bus, 52a. 52b...address bus, 53a, 53b...control bus, 60...memory data transfer control circuit, 62~
64...Address generator. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Memory bus Figure 3 Figure 4 Figure 6 Figure 7 Figure 8 Figure 9 Figure 12

Claims (1)

[Claims] Two data buses for transferring memory data, two address buses for transferring memory addresses, and two control buses for transferring various memory control signals. a first multiplexer for switching between the two address buses, a second multiplexer for switching between the two control buses, and a first flip-flop for controlling the first and second multiplexers;
A memory block that is addressed according to the outputs of the first and second multiplexers; read data from this memory block is used as a first input, and data on one of the two data buses is used as a second input. and a three-input arithmetic unit whose third input is data on the other of the two data buses, the output of which is connected to the data input/output terminal of the memory block, and the memory A pipeline register that temporarily holds data read from a block, a driver unit that outputs the data held in the pipeline and register to one of the two data buses, and a second pipeline register that specifies the output destination of the driver unit. A plurality of bitmap memory planes each having a flip-flop, a main control means for selecting and specifying a source and a destination plane from these plurality of bitmap memory planes, and data transfer between the memory planes selected and specified by the main control means. A memory data transfer control circuit that performs control, the memory data transfer control circuit having at least two address generators that generate a memory address specifying a source or destination plane area on one of the two address buses. A bitmap drawing device comprising: and.