JPS63121975A - Information processor - Google Patents

Abstract

PURPOSE:To speedily terminate invalidating operation by replacing the number of vector storage elements and reducing the number of elements. CONSTITUTION:A distance D between the vector storage elements transmitted in response to a vector storage request is denoted as 2<n> (n: integer). The titled processor has a degeneracy function to reduce the number of vector storage elements to M/L where the relation between the storage capacities M and D of a buffer storage means 5 and the number L meets M/D<L. Where the distance D=2<n> holds with a block size 2<l>[B] and the buffer storage means 5 having 2<n> blocks provided, only 2<l+m-n> block addresses suffice for invalidating the buffer storage means 5. The number of elements L is compared with the number of invalidating times 2<l+m-n> where the inter-element distance is denoted as 2<n>. If L>2<l+m-n> holds, the number of elements L is replaced with 2<l+m-n> to reduce the number of elements L.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and more particularly to an information processing device that makes it possible to reduce the number of times invalidation processing is performed on valid data stored in a buffer storage means. .

[Conventional technology]

Conventionally, the invalidation processing of the buffer storage means in this type of information processing device involves rewriting data on the main storage means in response to a store request from the vector processing means, and copying the data in blocks. Since the data in the buffer storage means may become invalid, this is done to guarantee the data in the buffer storage means against subsequent scalar load requests.

In reality, invalidation processing involves a control method that invalidates all data in the buffer storage means when a vector store request is received, a vector store start address (at the time of a vector store request), a distance between vector store elements (D), etc. A vector store area (B-B+DL) is created and held from information such as the number of vector store elements (B, B+D,
B+2D...B+LD).

Use each to perform invalidation processing block by block,
Until the processing is completed, in order to guarantee the data for subsequent scalar loads, when accessing the retained vector store area, the request is processed as a direct request to the main storage means. I was doing a lot of things.

[Problems to be Solved by the Invention] In the conventional invalidation processing method described above, since the buffer storage means stores and controls data in block address units, it is necessary to store all address information in the invalidation control. is never used, and only a certain part of it is used. For example, in a buffer storage means of t bits of address in a block and m picts of block address, the distance between vector store elements (D
) is the value of 2n.

Contains 2t+rn-n store elements 2 L+m-n
The second invalidation process returns to the first block address again. This means that the larger the value of D and the larger the value of vector store storage (number of vector stores), the more the number of invalidation processes for the same block address increases.

In that case, even if you execute the invalidation process one by one using the invalidation address that you have taken the pains to create, the block addresses indicated by part of the invalidation address are the same, so the invalidation process for the same block is There are problems in that the invalidation process is repeated, resulting in wasted time and slowing down the processing of subsequent requests.

The present invention solves the serious problems of the conventional ones, and provides an information processing apparatus that can reduce the number of invalidation processes, quickly complete the invalidation process, and further speed up the processing of subsequent requests. This is what we provide.

[Means for solving problems]

The information processing apparatus of the present invention includes a scalar processing means for processing a scalar request, a vector processing means for processing a vector request, and a request issuing means for issuing a scalar request and a vector request to the scalar processing means and the vector processing means, respectively. , a main memory means for exchanging data with the scalar processing means and the vector processing means, and a copy of part of the data in the main memory means located between the main memory means and the scalar processing means in units of blocks. a buffer storage means having a storage capacity M having a valid bit for storing the block address and validity of the block; and a vector store element sent together with the vector store request in response to the vector store request from the request issuing means. address information holding means for holding vector store address information including a number 1 and a distance (D) between vector store elements; and vector store address information supplied from the address information holding means to be stored in the buffer storage means. an invalidation processing means for creating a plurality of invalidation addresses for invalidation processing to invalidate valid bits in the address information and performing invalidation processing based on the invalidation addresses; and a vector stored in the address information holding means. ) of the distance between store elements is D=2”
(D: an integer), a division circuit that divides the storage capacity M of the buffer storage means by the distance between vector store elements (D), and an output result (D) output from the division circuit. M/I)) and the number of vector store elements ℃
) and a request issuing means consisting of a selection circuit for determining the number of vector store elements to be sent to the invalidation processing means based on the comparison output result, and a request issuing means.

〔Example〕

Next, the present invention will be explained with reference to the drawings. Fig. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed diagram of a part thereof.

First, the outline of the operation will be explained using FIG. Normally, the scalar request issued by the request issuing means 6 is.

It is sent to the scalar processing means 7 via the scalar request information line 601, and via the control means 9 and the main memory control information line 901 when the scalar request is a store request.

A data store operation is performed on the main storage means 4. Further, if the scalar request is a load request, a load access is performed from the control means 9 to the buffer storage means 5 via the buffer storage control information line 902, and if data exists in the buffer storage means 5, the buffer storage means 5 is loaded. The load data is returned to the scalar processing means 7 via the storage data line 501, and if the data does not exist, a load access is performed from the control means 9 to the main memory means 4 via the main memory control information line 901. The load data is stored in the buffer memory means 5 via the main memory data line 401, and the buffer memory means 5 is loaded again, and the read data is scanned and written via the buffer memory data R50°1. It is returned to the processing means 7.

Furthermore, if the scalar load is to the main memory means 4, the load data is directly returned to the scalar processing means 7 via the main memory data line 403.

A vector request from one vector processing means 8 directly accesses the main memory means 4 via the control means 9, and load data is returned to the vector processing means via the main memory data line 402.

Next, the invalidation process of the second normal buffer storage means 5 will be explained. When a store request is made from the request issuing means 6 to the main memory means 4 in a state where a copy of a part of the data in the main memory means 4 exists in the buffer memory means 5 in block units, the vector request information line 602° A request to the control means 9 is issued via the vector processing means 8 and the vector request information line 802, and the request is executed via the main memory control information line 901.

This means that the data in the main storage means 4 has been rewritten, and it becomes necessary to ensure the contents of the data in the buffer storage means 5. Therefore, the vector store start address (B), the distance between vector store elements (D), and the number of vector store elements) are stored in the address information holding means 1 from the vector processing means 8 via the vector store information line 801. Vector store start address line 101.
Vector store element number lines 103, 201. By sending the information to the invalidation processing means 3 via the vector store inter-element distance line 102, the invalidation processing means 3 determines the invalidation addresses (B, B+D, B+2D, . . .
・B+LD) is created, and the buffer storage means 5 is invalidated via the invalidation processing line 301.

This is the basic operation, but the feature of the present invention is that the distance between vector store elements sent with a vector store request is expressed by zn (n is an integer).

In addition, if the relationship between the storage capacity M and D of the buffer storage means 5 and the number of store elements (6) is 5 (L), then L
This is achieved by having a degeneracy function that reduces the value to ■, which will be explained with reference to FIGS. 3 and 2.

As shown in FIG. 3, when there is a buffer storage means 5 with block size 2L[:B] and number of blocks 2n.

Assuming that the distance between vector store elements (6) is D=2n, the number of block addresses necessary for invalidation processing for this buffer storage means 5 is 2L-1-m-n. This is because data is registered in the means 5 using a part of the address.

When D is expressed as 2n as above, it is always (2Z+m-
The block address indicated by the n+1)th vector store address and the block address indicated by the first vector store address are the same.

The present invention focuses on this point and reduces (degenerates) the number of vector store elements.

For example, if the number of vector elements (width) is L (number of vector elements), then in normal invalidation processing, L (numbers) of invalidation addresses are created and invalidation processing is performed L times.

If the distance between vector store elements is represented by 2n and A, then the block 7 indicated by the vector store
'stri 2""-n (pieces) tear') + 2"
""-" O invalidation processing should be sufficient.

Therefore, the number of elements (width) and the distance between elements are expressed as 2n, t+
Compare the number of invalidation processing times 2 when m−n is reached.

If L > 27”m-n holds true, the number of elements (by replacing L with 2A+m-n,
The purpose of this is to realize degeneracy of the number of vector elements (width of the number of vector elements).

Next, the present invention will be described in detail with reference to FIG.

The contents of the B register 11 that holds the vector store start address in the address information holding means 1, the D register 12 that holds the distance between vector store elements, and the L register 13 that holds the number of vector store elements are invalidated. B register 31, D register 32 in means 3. Each is sent to the L register 33, where a vector store address is created and invalidation processing is performed.
The contents of the register 12 are sent to the 2n detection circuit 21 and the division circuit 22 in the element number reduction means 2 via the vector element distance line 102, and if the contents of the D register 2 are 2n, the information line 202 is sent from the 2n detection circuit 21. The division circuit 22 outputs the detection signal "1#" through the buffer storage means 5.
The storage capacity M (=2Z+machi) is divided by the contents of the D register, and the division result is outputted via the information line 203.

Next, the comparison circuit 23 compares the output result of the division circuit 22 and the contents of the L register 3, and outputs a result output "1" via the information line 204 if M<L holds true. The selection circuit 25 receives the contents of the L register 3 and the contents of the division circuit 22 via the vector store element count 103 and the information line 203, respectively.
The contents of the D register are 2n for each output result from 04.
If it shows that M < L holds true, the contents of the division circuit 22 are selected from the A wholesaler 24 via the selection signal line 206, and the value is assigned to the number of vector store elements. L through the vector store element number line 201 as
Send to register 33. Conversely, if the AND dart 24 fails to obtain an AND, the contents of the L register 13 are sent as they are to the L register 33. By doing this,
It becomes possible to reduce (degenerate) the number of vector store elements, and the invalidation processing means 3 stores the B register 31. D register 32
A vector store address is created based on the contents of the L register 33, and invalidation processing is performed.

Since the present invention is characterized by the degeneracy of the number of vector store elements, the above description has been made for the case where all blocks in the buffer storage means 5 indicated by the vector store address are invalidated as an invalidation processing method.

It is clear that the present invention is applicable to other invalidation processing methods.

〔Effect of the invention〕

As explained above, in the present invention, the distance between vector store elements () is 2n, and the relationship between the storage capacity M of the buffer storage means 5, the number of vector store elements (6), and D is the same as the number of vector store elements (6). By replacing it with a stone and reducing the number of elements, the number of invalidation processes can be reduced, the invalidation process can be completed quickly, and subsequent requests can be processed more quickly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a partially detailed diagram thereof, and FIG. 3 is an explanatory diagram of buffer storage means. Explanation of symbols: 1 is address information holding means, 2 is element number reduction means, 3 is invalidation processing means, 4 is main storage means, 5 is buffer storage means, 6 is request issuing means. 7 is a scalar processing means, 8 is a vector processing means, 9 is a control means, 21 is a 2n detection circuit, and 22 is a division circuit. 23 is a comparison circuit, 24 is an AND dart, and 25 is a selection circuit. Figure 1 Figure 3 M=2'x2! “-2” (BJ

Claims (1)

[Claims] 1. A scalar processing means for processing a scalar request, a vector processing means for processing a vector request, a request issuing means for issuing a scalar request and a vector request to the scalar processing means and the vector processing means, respectively, and the scalar processing means and a main memory means for exchanging data with the vector processing means, and a main memory means located between the main memory means and the scalar processing means, storing a copy of a part of the data in the main memory means in units of blocks, and a block of the block. a buffer storage means with a storage capacity M having a valid bit indicating an address and validity, and a vector store element number (L) and a vector sent together with the vector store request in response to the vector store request from the request issuing means. address information holding means for holding vector store address information including a distance (D) between store elements; and valid bits stored in the buffer storage means based on the vector store address information supplied from the address information holding means; an invalidation processing means that creates a plurality of invalidation addresses for invalidation processing to invalidate and performs invalidation processing based on the invalidation addresses; and a distance between vector store elements stored in the address information holding means. (D) is a 2^n detection circuit that detects that D=2^n (D: integer); a division circuit that divides the storage capacity M of the buffer storage means by the distance between vector store elements (D); A comparison circuit that compares the output result output from the division circuit with the number of vector store elements (L), and the output results of the 2^n detection circuit and the comparison circuit to determine the number of vector store elements to be sent to the invalidation processing means. An information processing device comprising: element number reduction means comprising a selection circuit for determining the number of elements.