JPS63114392A - Color split circuit for color television receiver - Google Patents

Abstract

PURPOSE:To reproduce an excellent picture even for a video signal having fluctuation in a time base reproduced from a VTR or the like while the titled circuit is reduced in scale by using a specific clock signal selectively. CONSTITUTION:A clock signal generating circuit 2 generates a 1st clock signal from a chrominance subcarrier extracted and shaped from a composite video signal and a signal synchronously with it and having frequencies of two times or four times, and a clock signal generating circuit 3 generates a 2nd clock signal from a signal synchronously with the chrominance subcarrier and having two time or four times of frequency, from one horizontal scanning reset signal and a hue flag signal. A color signal split circuit 1 is used in common for the interlace system and the non-interlace system, a clock selection circuit 4, according to the mode selection command II, selects the clock signal generated by the circuit 3 with respect to the reproduction signal from a VTR to give it to the color split circuit 1 thereby preventing deterioration in picture quality attended with the fluctuation of the time base.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a color division circuit used in a color television receiver having image quality improvement functions and additional functions.

2. Description of the Related Art At present, attempts are being made to apply the rapidly progressing digital signal processing technology to improving the image quality of home color television receivers.

In such color television receivers, the analog video signal is once converted to a digital video signal, and then subjected to image quality improvement processing such as adaptive Y/C separation, noise removal, and contour enhancement, and then converted back to the analog video signal. converted into a signal.

One of the ways to improve image quality is to convert interlaced (interlaced scanning) screens to non-interlaced (
Attempts have also been made to use scanning line interpolation processing to convert the screen to a progressive scanning (scanning) screen.

That is, as shown in FIG. 8, the analog video signal supplied to the input terminal 101 is first passed through the A/D conversion circuit 10
3, the digital video signal is converted into a digital video signal at a sampling frequency (4fsc) that is four times the color subcarrier frequency fsc, and then the luminance signal Y and the color signal C are converted into a digital video signal in the Y/C separation circuit 104.
separated into The separated and demodulated color signal C is time-division multiplexed (R-
It consists of a Y) signal and a CB-Y) signal.

The luminance signal Y undergoes processing such as luminance adjustment and contour correction in the luminance signal processing circuit 105 and then passes through the matrix circuit 110.
supplied to On the other hand, the color signal C is transmitted to the color signal processing circuit 10.
After undergoing processing such as color demodulation and color adjustment in step 6, the color division circuit 109 converts the (RY)' signal and (B
-Y) signal and supplied to the matrix circuit 110. The three primary color signals R, G, and B output from the matrix circuit 110 are sent to D/A conversion circuits 111 and 112.
．． Analog R, G with improved image quality for each of 113,
The signal is converted into a B signal and supplied to a subsequent color cathode ray tube (not shown).

On the other hand, switches 107 and 108 are switched in accordance with an interlace/non-interlace selection command supplied to input terminal 102, and scanning is performed between luminance signal processing circuit 105, color signal processing circuit 106, and D/A conversion circuits 111 to 113. A line interpolation processing system 120 and the like are inserted. The scanning line interpolation processing system 120 includes a scanning line interpolation processing system for luminance signals, which includes a luminance signal interpolation circuit 121 and a luminance signal time axis compression circuit 123, and a color signal interpolation processing system, which includes a color signal interpolation circuit 122 and a color signal time axis compression circuit 124. It consists of a signal scanning line interpolation processing system.

The luminance signal Y and color signal C subjected to scanning line interpolation are
As shown in the waveform diagram in the figure, the time axis is compressed to half compared to the video signal before processing. Luminance signal time axis compression circuit 123
The non-interlaced luminance signal output from the matrix circuit 110' is supplied as is to the matrix circuit 110'. On the other hand, the non-interlaced color signal C output from the color signal time axis compression circuit 124 is synchronized with the color subcarrier in the color division circuit 109 and is converted into a non-interlaced color signal ( R-Y)
It is separated into a signal and a (B-Y) signal and supplied to the matrix circuit 110°.

In order to create clock signals to be supplied to each of the above circuits,
A color subcarrier extraction/shaping circuit 114 and a clock signal generation circuit 115 are provided. That is, in the color subcarrier extraction/shaping circuit 114, the color subcarrier is extracted and shaped from the composite video signal on the input terminal 101, and in the phase lock loop in the clock signal generation circuit 115, it is synchronized with the color subcarrier and its frequency fsc. Clock signals having frequencies of 1, 2, 4 and 8 times are created and supplied to each section within the processing circuit.

Problems to be Solved by the Invention In the image quality improvement circuit shown in FIG. 8, since the clock signal frequencies are different between the interlaced processing system and the non-interlaced processing system, the color division circuit and matrix circuit are separately used. has been established. Therefore, there is a problem that the circuit scale becomes large, and the cost of parts, installation space, and manufacturing time increase.

In addition, since the color division circuit in the image quality improvement circuit shown in Figure 8 separates color signals using a clock signal created using only the color subcarrier as a reference, the playback signal of a video tape recorder (VTR) For video signals with fluctuations in the time axis, such as the above, there is a problem in that the image quality deteriorates.

Structure of the Invention Means for Solving Problems The color division circuit of the present invention is created from a color subcarrier extracted and shaped from a composite video signal and a signal synchronized therewith and having a frequency twice or four times that of the color subcarrier. a first clock signal synchronized with the color subcarrier and having a frequency twice or four times that of the color subcarrier;

By selectively using either one of the first horizontal scanning reset signal and the second clock signal generated from the hue flag signal, the color signal dividing circuit can be used in an interlaced processing system and a non-interlaced processing system. The circuit size is reduced by sharing the same, and the video signal is configured to effectively prevent deterioration in the image quality of a video signal reproduced from a VTR that has fluctuations in the time axis.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 shows a color division circuit 1 according to an embodiment of the present invention and a first . The first one creates the second clock signal. The second clock signal generation circuits 2 and 3 and the first clock signal generation circuits 2 and 3 created by these. A clock supply system comprising a clock signal selection circuit 4 that selects one of the champion clock signals created by the second clock signal and another clock signal creation system (not shown) and supplies it to the color signal division circuit 1. FIG. 2 is a block diagram showing the relationship between FIG.

As shown in the block diagram of FIG. 2, the color division circuit 1 is synchronized with the color subcarrier and has four times or eight times the color subcarrier depending on whether it is an interlaced system or a non-interlaced system.
Input terminal receiving double frequency clock signal 4fsc/8fsc 11% Clock signal 2fsc/8fsc synchronized with the color subcarrier and twice or four times the frequency depending on whether the interlaced or non-interlaced method is used.
Input terminal It receives 4fsc, input terminal ■3 receives interlaced or non-interlaced color signal C, and D flip-flops 21, 22, . . .
26 to separate the color signal C.

In other words, as shown in the waveform in Figure 3, in both the interlaced method and the non-interlaced method,
By holding the clock signal CK2 on the input terminal 2 in the D flip-flop 21 in synchronization with the clock signal CKI having twice its frequency, the clock signal CK3 which is synchronized in phase with the clock signal CKI and has a half frequency thereof is generated. create. This clock signal CK3 is supplied as it is to the clock input terminal of the D flip-flop 23, and the clock signal CK4 whose phase is inverted by an inverter is supplied to the clock input terminal of the D flip-flop 24.

As shown in the waveform diagram of Fig. 3, the color signal C supplied to the input terminal I has (R-Y)
and (BY) appear alternately.

Note that the lowercase number 0 on the right shoulder of the waveform diagram. l.

2... indicates the order of appearance of each signal. This color signal C is held in the D flip-flop 22 in synchronization with the clock signal CKI.
The color signal C1 is phase-synchronized with the color signal C1. This color signal CI is
D flip-flop 2 in synchronization with clock signal CK3
3 and becomes the color signal C2, and is also held in the D flip-flop 24 in synchronization with the clock signal CK4 to become the color signal C3. The color signals c2 and 03 are held in D flip-flops 25, 26, and 27 respectively in synchronization with the clock signal CK1, thereby becoming separated color signals (R-Y) and (B-Y), The signal is supplied from each of the output terminals 01 and 0□ to a subsequent matrix portion (not shown). Note that the D flip-flop 27 is provided for phase matching of the color signals (RY) and (BY).

In this way, the color division circuit shown in FIG. 2 is commonly used for both interlaced and non-interlaced systems.

The first clock signal generation circuit 2 in FIG. 1 includes D flip-flops 31 to 34 and exhaustive OR gates 35 and 36, as shown in the block diagram of FIG.
and a switch 37.

Clock input terminal 1. and I3, depending on whether it is interlaced or non-interlaced.
Clock signal 4f created using the conventional method of applying phase lock to the color subcarrier extracted and shaped from the composite video signal.
sc and 8fsc are supplied, and the clock input terminal I2 is supplied with the clock signal fsc in both cases. In addition, a mode selection signal I specifying whether the interlace method or the non-interlace method is used is supplied to the input terminal I4.

The clock signal fsc on the clock input terminal 2 is the clock signal fsc on the clock input terminal 2.
D flip-flop 31, 32 in stage configuration and exhaustive or gate 3 that requires two people to output these
5, the clock signal 2fsc is synchronized in phase with the color subcarrier and has twice its frequency, and is supplied to one input terminal of the switch 37 and the D flip-flop 33.

The clock signal supplied to the D flip-flop 33 is a two-stage D flip-flop 33, 34 which receives an 8 fsc clock signal at its clock input terminal, and an exhaustive OR gate 36 which outputs these two outputs. As a result, the clock signal 4fsc is synchronized in phase with the color subcarrier and has a frequency four times that of the color subcarrier, and is supplied to the other input terminal of the SIN 37. The switch 37 is
According to the mode selection signal of the input terminal I4, one of the clock signal 2fsc for the interlace method and the clock signal 4fsc for the non-interlace method is supplied to the output terminal 0.

The second clock signal generation circuit 3 in FIG. 1 includes a divide-by-2 circuit 41, D flip-flops 42 to 44, an AND gate 45, and a switch 46, as shown in the block diagram of FIG. It consists of

As shown in the waveform diagram of FIG. 6, the clock input terminal 11 receives a clock signal 4fsc or 8fsc depending on whether the system is an interlace system or a non-interlace system.
fsc is supplied. One horizontal scan reset signal synchronized with the horizontal synchronization signal is supplied to the input terminal (2).

This 1 horizontal scan reset signal is a clock signal 4fsc
A reset signal R synchronized with the clock signal and having a width of one period of the clock signal is generated by a two-stage D flip-flop 42, 43 and an AND gate 45 which receive /8fsc at the clock input terminal, and a frequency divider circuit 41 Supplied to the reset input terminal of

As shown in the waveform diagram of FIG. 6, the output A of the divide-by-2 circuit 41 falls to a low level in synchronization with the rise of the reset signal R, and immediately after this falls to the clock signal 4fsc/4fsc.
It rises in synchronization with the rise of 8fsc. The output A of the divide-by-2 circuit 44 is supplied to one input terminal of the switch 46, and the clock signal 4f is supplied to the clock input terminal.
It passes through a D flip-flop 44 receiving sc/8fsc to become signal B delayed by one clock period and is supplied to the other input terminal of switch 46. The switch 46 receives clock signals A which are in opposite phases to each other and which appear on both input terminals.
and B are selectively supplied to output terminal 0 according to the polarity of the hue flag signal supplied to input terminal I.

The above-mentioned hue flag signal indicates whether the color signal first written to the memory during time axis compression for each horizontal scanning line is (RY) or (B-Y) in the non-interlace method. It is a binary signal, and the clock input terminal receives a write reset signal to the time axis compression memory created from the horizontal synchronization signal, and the data input terminal receives a 2-value signal.
Created by a D flip-flop subjected to fsc.

FIG. 7 shows a circuit for generating the 1 horizontal scan reset signal supplied to the input terminal I2 in FIG.
, a synchronization separation circuit 72 , a mask signal generation circuit 73 ,
It is composed of an AND gate 34.

The input terminal ■ has 4fsc or 8fs depending on whether it is interlaced or non-interlaced.
A clock signal of c is supplied. This clock signal is
The signal is frequency-divided by the 910 frequency dividing circuit 71 and supplied to the output terminal O as a one-horizontal scan reset signal, and is also supplied to the mask signal generation circuit 73. The mask signal creation circuit creates a mask signal by adding time axis fluctuations (jitter) in the expected range before and after the horizontal synchronization signal created by the 910 frequency dividing circuit, and supplies it to one input terminal of the AND gate 34. do. If the horizontal synchronization signal contained in the composite video signal on the input terminal I2 and extracted by the synchronization separation circuit 72 appears within the appearance period of the mask signal, the horizontal synchronization signal is passed through the AND gate 3.
However, if the mask signal appears out of alignment with the mask signal due to channel switching, etc., it passes through the AND gate 34 and resets the 910 frequency divider circuit 71.

In accordance with the mode selection command H, the clock signal selection circuit 4 in FIG. This prevents deterioration of image quality due to fluctuations in the time axis.

Although the case where the color signal C is divided into the (R-Y) signal and the (B-Y) signal has been exemplified above, it may also be divided into the ■-axis signal, the Q-axis signal, etc.

Effects of the Invention As explained in detail above, the color division circuit of the present invention is created from a color subcarrier extracted and shaped from a composite video signal and a signal synchronized with this and having a frequency twice or four times that of the color subcarrier. A second clock signal generated from a first clock signal that is synchronized with the color subcarrier and has a frequency twice or four times that of the color subcarrier, a horizontal scan reset signal, and a hue flag signal. Since it is a selectively used configuration, the color signal division circuit is shared between the interlaced processing system and the non-interlaced processing system, reducing the circuit scale and eliminating fluctuations in the time axis reproduced from a VTR etc. Good screen reproduction is possible even for certain video signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a color division circuit according to an embodiment of the present invention together with related parts for creating and supplying the first and second clock signals, and FIG. 2 is a block diagram showing the color division circuit 1 in FIG. 1. 3 is a waveform diagram for explaining the operation of the color division circuit, and FIG. 4 is a block diagram showing the configuration of the first clock signal generation circuit 2 in FIG. Figure 5 is the first
A block diagram showing the configuration of the second clock signal generation circuit 3 in the figure, FIG. 6 is a waveform diagram for explaining the operation of the second clock signal generation circuit 3, and FIG. 7 is a block diagram showing the configuration of the second clock signal generation circuit 3. FIG. 8 is a block diagram showing the configuration of a circuit for generating one horizontal scanning reset signal to be supplied to the signal generating circuit 3; FIG. 8 is a block diagram showing the configuration of an image quality improvement circuit including a conventional color division circuit;
9 and 10 are waveform diagrams for explaining the operations of the interlaced color division circuit and the non-interlaced color division circuit included in FIG. 8, respectively. l...color division circuit, 2...first clock signal generation circuit, 3...second clock signal generation circuit, 4...
Clock signal selection circuit, 21-26.31-34.42
~44...D flip-flop, 41...2 frequency divider circuit, 71...910 frequency divider circuit, 72...synchronous separation circuit, 73...mask signal generation circuit. Patent applicant: NEC Home Electronics Co., Ltd.

Claims (1)

[Scope of Claims] A first clock signal created from a color subcarrier extracted and shaped from a composite video signal and a signal synchronized therewith and having a frequency twice or four times that of the color subcarrier; and the color subcarrier. Y/C separation is performed by selectively using either one of a signal synchronized with and having a frequency twice or four times that of the second clock signal, a horizontal scanning reset signal, and a second clock signal created from the hue flag signal. A color division circuit for a color television receiver, characterized in that it separates time-division multiplexed color signals.