JPS631046A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the realization of a desired logical circuit on demand without the fusing of an AND array and an OR array by providing a register which can be rewritten against logical means, etc. in a field programable logic array (FPLA). CONSTITUTION:Data are written in sequence from the logical formula input terminal 11 of external terminals under the control of data control means 10 in the first and the second FF-made registers 5, 6 of, an AND array 4, an OR array 7. A desired logical operation formula due to logical product operation means 6 and logical sum operation means 9 is determined and logical operation results are stored in memory means 15 and monitored. This constitution without fusing enables the realization of a desired logical circuit on demand and the monitoring of the logical operation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a half-horse integrated circuit (hereinafter abbreviated as LSI).

(Prior Art) When designing a logic circuit, logic simulation is performed to verify whether the designed circuit operates as desired.

Conventionally, logic simulation has generally been performed using simulation software on a computer. However, nowadays the scale of logic circuits that are subject to simulation is increasing.

(1) Simulation time becomes enormous and efficient design verification cannot be performed.

(2) The computer requires a large amount of memory.

Problems such as this are occurring. Therefore, it is desired to realize a means for implementing large logic circuits at high speed and economically.

One possible way to deal with the above problem is to simulate the logic circuit using hardware.

To this end, it is possible to realize various logic circuit specifications, and to check the operating state of each logic element in the simulation circuit! Requires hardware that can be used to detect

2. Description of the Related Art Conventionally, there is an LSI called a program logic array (hereinafter abbreviated as PLA) in which the logic specifications of a logic circuit are programmable. PLA is broadly divided into mask PLA and field PLA (hereinafter abbreviated as FPLA) depending on its programming method. is programmable by the LSI user.

FIG. 4 shows a configuration diagram of a conventional FPLA. In the figure, 101 is an AND array, 102 is an OR array, 103
is an input signal line, and 104 is a product term line.

The AND array 101 performs a logical AND operation on the input signals and outputs the result to the product term 1iA 104. Also, OR array 10
2, performs a logical sum operation between the outputs of the product term line 104,
The result is output to the output signal line 105. Here, AN
The content of the AND operation of the D array 101 is determined by the presence or absence of the diode 106 provided at the intersection of the input signal line and the product term line.

The FPLA shown in this example is of the fuse type, and is programmed by blowing an arbitrary fuse 107 connected in series with the diode 106. Further, the content of the logical sum operation in the OR array 102 is the product term line 10
4 and the output signal line 105, and is programmed by blowing any fuse 107 connected to the emitter of the transistor.

As described above, in the FPLA, by blowing out the fuses of the AND array and the OR array, a desired sum-of-products type logic formula, that is, a logic circuit can be realized.

(Problems to be Solved by the Invention) In the above-mentioned FPLA, it is not possible to reconnect the fuse once blown to obtain the desired logic circuit. The formula can only be changed by adding fuse blowing. Therefore, it is not possible to flexibly respond to changes in the specifications of the logic circuit to be simulated.

Furthermore, the conventional PLA has the disadvantage that it cannot be applied to logic simulations because it does not have a means for detecting the operating state of the internal circuit in mJ.

An object of the present invention is to eliminate the conventional drawbacks, to make it possible to flexibly change the logic specifications realized by a single LSI, and to create an LSI in which the operating state of the internal circuit can be observed based on the logic specifications at any given time. It is to provide.

(Means for Solving the Problems) The semiconductor device of the present invention includes a rewritable first register provided corresponding to each of a plurality of input signal lines, and a rewritable first register provided corresponding to each of a plurality of input signal lines, and a , a plurality of AND means for performing an AND operation on input signals, a rewritable second register provided corresponding to each of the plurality of AND means, and a second register that is rewritable to correspond to each of the plurality of AND means; Accordingly, an OR means for performing an OR operation on the outputs of the plurality of AND means; a first data transfer means for externally transferring data to a second register; a memory means for storing outputs of the AND means or the OR means; or both the AND means and the OR means; The device includes second data transfer means for transferring data stored in the means to an input signal line, and third data transfer means for transferring data stored in the memory means to an output terminal.

Also, 1st. The second or first and second registers are constructed of flip-flop circuits, the memory means is a random access memory, and the memory means is constructed of a shift register.

(Function) With the above configuration, the logical formula of the LSI is an AND array, ○R
It is possible to make it variable by rewriting the contents of the register of the array, and furthermore, the input signal can be the contents stored in the memory means or the result of processing the contents stored in the memory means, making it more complicated. It is possible to realize an LSI that can simulate logic circuits that perform various operations using hardware.

Further, by reading out the stored contents of the memory means to the outside, it is possible to observe the operating state of the internal gates of the simulation circuit, thereby making it possible to perform logic simulation of the logic circuit using hardware.

(Embodiment) An embodiment of the present invention will be explained with reference to FIGS. 1 to 3.

FIG. 1 shows a configuration diagram of a semiconductor device of the present invention.

In the figure, 1 is an input signal line, 2 is a product term line, and 3 is an output signal line. AND array 4 includes a first register 5.
A logical product calculation means 6 is configured.

- On the other hand, the OR array 7 has a second register 8. A logical sum operation means 9 is configured. Also, register 5°8 has the first
It is connected to a logical formula input terminal 11 via a data transfer means 10 .

The RAM 12 is for storing data on the product term line 2 and data on the output signal line 3. The memory contents of the RAM 12 are connected to the input signal line 1 via the second data transfer means 13 and the input signal switching means 14, and
RAM data output terminal 1 via data transfer means I5 of
6.

Next, the first register and the AND means used in this embodiment will be explained based on FIG. 2.

In the same figure, the first register 5 includes a flip-flop circuit 17 formed by a CMO'S circuit and an N-channel M○5F circuit.
Switch element 18.1 for address selection by ET
Consists of 9. The source terminals of the switch elements 18.19 are respectively connected to the complementary outputs 20.21 of the flip-flop circuit 17, and the drain terminals are connected to the bit lines 22.23.
are connected to each. Further, the gate terminal is connected to the word line 24.

With the following configuration, data on the bit line is written to the register selected by the word line.

The AND operation means 6 is a circuit for determining whether or not the data on the input signal line 1 is to be subjected to an AND operation, and performs an AND operation based on the determination result. An A N D element 25 that performs an AND operation between the output 20 of the circuit 17 and the input signal, an OR4 element 26 that performs a logical OR operation of the output of the ANDi element 25, and the output 21 of the flip-flop circuit 17, and judgment and operation using these elements. AND to perform a logical product operation of result 27 and the previous operation result
It is composed of an element 28. With this configuration, when the state of the flip-flop circuit 17 is logic II II II, that is, when the output 20 is logic II II II, the data on the input signal line is subject to the AND operation, and when the state of the flip-flop circuit 17 is "0" The output of the OR element 26 is always set to logic "1" so that the data on the input signal line "2" can be excluded from the object of the AND operation.

Next, the second register and OR means in this embodiment will be explained based on FIG. 3.

In the same figure, the second register 8 includes a flip-flop circuit 29 made up of a CMO3 circuit and an N-channel MO8FET.
It is composed of switch elements 30 and 31 for address selection. The source terminals of the switch elements 30, 31 are respectively connected to the complementary outputs 20, 21 of the flip-flop circuit 29, and the train terminals are respectively connected to the bit lines 22, 23. Also, the gate terminal is word line 2
The data on the pin 1- line is written into the register selected by the word line.

The logical sum means 'M' determines whether or not the data of the term line 2 is to be subjected to the logical sum operation, and performs the logical sum operation of the data of the product term line 2 which is the object. It is composed of an AND element 32 which performs a logical product operation between the output 20 of the flip-flop circuit 29 and the product term line signal, and an OR element 33 which performs a logical sum operation between the outputs of the AND elements 32. With this configuration, the state of the flip-flop circuit 29 is logic HI II, that is, the output 20 is logic LL I I
When I, the data on the product term line is subjected to the logical sum operation,
When the state of the flip-flop circuit 29 is logic 110'', the data on the product term line can be excluded from the object of the OR operation.

Next, an overview of the operation of the semiconductor device of this embodiment will be explained.

1st. The data applied to the external terminals are sequentially written into the second registers 5 and 8 under the control of the first data transfer means IO. This operation determines the logic expressions of the AND array and OR array, that is, the specifications of the logic circuit. In this state, the semiconductor device of this embodiment performs desired arithmetic processing on the input data on the input signal line 1 and outputs the result to the output signal line 3. At the same time, the product term line 2. The data on output signal line 3 is stored in memory means 15.

The data stored in the RAM 12 is transferred to the second data transfer means 13. as necessary. The signal is transferred to the input signal line 1 via the input signal switching means 14. As a result, a combinational circuit based on logical product-sum operations can be expanded to a sequential circuit. Further, the RAM 12 stores the results of signal processing on the signals sequentially input to the input signal line 1, or the progress of the processing, and the contents are transferred to the RAM data output terminal via the third data transfer means. 16.

The present invention is not limited to the first embodiment described above, but can be implemented in various ways.

For example, in the above embodiment, a static RAM is used as the memory means, but any memory means can be used, and each can be used depending on the purpose.

For example, if the memory means is configured with a dynamic RAM, higher density can be achieved than in the case of a static RAM.

It is also possible to construct the memory means by a shift register.

(Effects of the Invention) According to the present invention, a desired logic circuit can be easily realized without limiting the logic specifications of the LSI, and the operating state of the internal circuit of the LSI can be observed. Its practical effects are great.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a semiconductor device according to an embodiment of the present invention, FIGS. 2 and 3 are detailed explanatory diagrams of the same, and FIG. 4 is a conventional FP
It is a block diagram of LA. DESCRIPTION OF SYMBOLS 1... Input signal line, 2... Product term line, 3... Output signal line, 4... AND array, 5... First register, 6... AND operation means ,7...O
R array, 8... Second register, 9... OR operation means, 10.13.15... Data transfer means, 11... Logical formula input terminal, 12... RAM,
14... Input signal switching means, 16... RAM
Data output terminal, 17.29...Flip-flop circuit, 18,19,30.31...Switch element,
20.21... Complementary output, 22゜23... Pitch
- line, 24...word line, 25.28°32...
・AND element, 26.33...OR element, 27...
·Calculation result. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2') 41-

Claims (4)

[Claims] (1) A rewritable first register provided corresponding to each of a plurality of input signal lines, and a plurality of rewritable registers that perform an AND operation on the input signal according to the contents of the first register. an AND means; a rewritable second register provided corresponding to each of the plurality of AND means;
an OR means for performing an OR operation on the outputs of the plurality of AND means according to the contents of the second register; and a first register for transferring data from the outside to the first and second registers. a data transfer means, a memory means for storing the outputs of the AND means or the OR means, or both the AND means and the OR means, and the data stored in the memory means is transferred to the input signal line. A semiconductor device comprising: second data transfer means for transferring data to the memory means; and third data transfer means for transferring data stored in the memory means to an output terminal. (2) The semiconductor device according to claim (1), wherein the first or second register, or the first and second registers, are constructed of flip-flop circuits. (3) Memory means is random access memory (RAM)
A semiconductor device according to claim (1), characterized in that: (4) The semiconductor device according to claim (1), wherein the memory means is constituted by a shift register.