JPS63104529A - Equalizing amplifier - Google Patents
Equalizing amplifierInfo
- Publication number
- JPS63104529A JPS63104529A JP25154686A JP25154686A JPS63104529A JP S63104529 A JPS63104529 A JP S63104529A JP 25154686 A JP25154686 A JP 25154686A JP 25154686 A JP25154686 A JP 25154686A JP S63104529 A JPS63104529 A JP S63104529A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- analog
- output
- digital
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 18
- 238000006243 chemical reaction Methods 0.000 claims abstract description 14
- 238000001514 detection method Methods 0.000 abstract description 7
- 238000005070 sampling Methods 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000011982 device technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Landscapes
- Networks Using Active Elements (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ディジタル伝送方式で、伝送路信号を受信し
伝送路損失を補償すると共に波形等化を施す等化増幅器
の利得を調整する自動利得制御回路に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention is a digital transmission method that automatically adjusts the gain of an equalizing amplifier that receives a transmission line signal, compensates for transmission line loss, and performs waveform equalization. This invention relates to a gain control circuit.
本発明は、伝送路損失を受けたアナログ信号を等化増幅
する手段において、
アナログ信号をディジタル信号にいったん変換してこの
信号を処理し、再びアナログ信号に変換することにより
、
ディジタル素子による集積回路で構成することができる
ようにしたものである。The present invention provides means for equalizing and amplifying an analog signal that has suffered transmission path loss, by converting the analog signal into a digital signal, processing this signal, and converting it back into an analog signal. It is designed so that it can be configured with.
ディジタル伝送方式では、伝送路損失のばらつきを補償
するために伝送路信号受信部で等化増幅器の自動利得制
御を施している。従来は第２図に示すように、線型な可
変利得増幅器からなる等化増幅器ｌと、尖頭値検出回路
２と、差動増幅器３とで構成され、等化増幅器１の出力
信号より尖頭値を検出し、この検出した直流信号に基づ
き差動増幅器３で利得制御信号１３を得て等化増幅器ｌ
の利得制御を施している。In digital transmission systems, automatic gain control of an equalizing amplifier is performed in a transmission line signal receiving section in order to compensate for variations in transmission line loss. Conventionally, as shown in FIG. 2, it is composed of an equalizing amplifier l consisting of a linear variable gain amplifier, a peak value detection circuit 2, and a differential amplifier 3. Based on the detected DC signal, the differential amplifier 3 obtains a gain control signal 13, and the equalizing amplifier l
Gain control is applied.
近年ディジタルデバイス技術の急速な進歩により、各種
ディジタル回路は大規模な集積回路化が計られているが
、従来の自動利得制御回路は波形等化のための各種線型
フィルタ、線型な可変利得増幅器および直流増幅器など
で構成されているので、集積回路化から取り残され、大
きな実装規模かつ大きな消費電力などでディジタル伝送
方式では大きな問題点となっていた。本発明はこうした
問題点を解決するもので、集積回路化が容易な等化増幅
器を提供することを目的とする。In recent years, rapid advances in digital device technology have led to large-scale integration of various digital circuits, but conventional automatic gain control circuits have been limited to various linear filters for waveform equalization, linear variable gain amplifiers, and linear variable gain amplifiers. Since it consists of DC amplifiers, etc., it has been left behind in integrated circuits, and its large implementation scale and large power consumption have been major problems in digital transmission systems. The present invention solves these problems and aims to provide an equalization amplifier that can be easily integrated into an integrated circuit.
本発明は、伝送路を経由したアナログ入力信号が到来す
る入力端子と、所望のレベルのアナログ出力信号が通過
する出力端子と、このアナログ出力信号の尖頭値と上記
所望のレベルの尖頭値に対応する基準信号とを比較して
生成したアナログ帰還信号を入力する帰還端子とを備え
た等化増幅器において、アナログ入力信号をディジタル
信号に変換する第一変換手段と、アナログ帰還信号をデ
ィジタル信号に変換する第二変換手段と、上記第一およ
び第二変換手段の出力にディジタル演算を施して上記ア
ナログ出力信号に相当のディジタル信号を生成する演算
手段と、この演算手段の出力するディジタル信号をアナ
ログ信号に変換する第三変換手段とを備えたことを特徴
とする。The present invention provides an input terminal through which an analog input signal via a transmission path arrives, an output terminal through which an analog output signal of a desired level passes, a peak value of this analog output signal, and a peak value of the desired level. An equalizing amplifier comprising a feedback terminal for inputting an analog feedback signal generated by comparing the signal with a reference signal corresponding to the first converting means for converting the analog input signal into a digital signal, a second conversion means for converting the output of the first and second conversion means into a digital signal; a calculation means for performing digital calculation on the outputs of the first and second conversion means to generate a digital signal equivalent to the analog output signal; The present invention is characterized by comprising a third conversion means for converting into an analog signal.
演算手段は、第一変換手段の出力を入力とする乗算手段
と、この乗算手段に与えられる乗算係数があらかじめ記
憶され、第二変換手段の出力をアドレス入力とするＲＯ
Ｍとを備えたことを特徴とする。The arithmetic means includes a multiplication means which receives the output of the first conversion means as an input, and an RO in which a multiplication coefficient given to the multiplication means is stored in advance and which takes the output of the second conversion means as an address input.
It is characterized by having M.
伝送路損失を蒙ったアナログ入力信号はディジタル信号
に変換される。また、アナログ出力信号の尖頭値が検出
され、この尖頭値と基準値とが比較された結果のアナロ
グ信号もディジタル信号に変換される。この二つの信号
がディジタル演算されて生成されたディジタル信号はア
ナログ信号に変換され、所望の尖頭値レベルのアナログ
信号が出力される。Analog input signals that have suffered transmission line losses are converted to digital signals. Furthermore, the peak value of the analog output signal is detected, and the analog signal obtained by comparing this peak value with a reference value is also converted into a digital signal. The digital signal generated by digitally calculating these two signals is converted into an analog signal, and an analog signal having a desired peak value level is output.
以下、本発明実施例を図面に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は本発明実施例の構成を示すブロック構成図であ
る。FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention.
まず、この実施例装置の構成を第１図に基づき説明する
。この実施例は、尖頭値検出回路２と、差動増幅器３と
、サンプリング回路４および８と、Ａ−Ｄ変換器５およ
び９と、ディジタルフィルタ６と、Ｄ−Ａ変換器７とを
備え、ここで、ディジタルフィルタ６は、乗算器６０１
と、遅延回路６０２と、乗算器係数を記憶したＲＯＭ６
０３とで構成される。First, the configuration of this embodiment device will be explained based on FIG. 1. This embodiment includes a peak value detection circuit 2, a differential amplifier 3, sampling circuits 4 and 8, AD converters 5 and 9, a digital filter 6, and a DA converter 7. , where the digital filter 6 is a multiplier 601
, a delay circuit 602, and a ROM 6 that stores multiplier coefficients.
03.
次に、この実施例の動作を説明する。到来した伝送路信
号１１はサンプル回路４でサンプルされ、Ａ−Ｄ変換回
路５で２値符号化信号になる。この信号はディジタルフ
ィルタ６に入力される。このディジタルフィルタ６では
、乗算係数信号１４が自動的にコントロールされて与え
られ波形等化および利得調整が行われる。すなわち、尖
頭値検出回路２で等化信号１２の尖頭値を検出し、差動
増幅器３でこの検出信号と固定比較電圧Ｖ ｒ ｅ ｆ
との差分を増幅して出力し、この出力をサンプル回路８
でサンプルしてＡ−Ｄ変換器９で２値符号化信号に変換
した後に、ＲＯＭ２Ｏ３に入力する。ＲＯＭ２Ｏ３から
は入力に対応した一定の信号が出力される。Next, the operation of this embodiment will be explained. The arriving transmission line signal 11 is sampled by a sampling circuit 4, and converted into a binary encoded signal by an A/D conversion circuit 5. This signal is input to the digital filter 6. In this digital filter 6, the multiplication coefficient signal 14 is automatically controlled and applied, and waveform equalization and gain adjustment are performed. That is, the peak value detection circuit 2 detects the peak value of the equalized signal 12, and the differential amplifier 3 uses this detection signal and the fixed comparison voltage V r e f
Amplify and output the difference between the sample circuit 8 and
After sampling the signal and converting it into a binary coded signal by the A-D converter 9, the signal is input to the ROM 2O3. A constant signal corresponding to the input is output from the ROM2O3.
ここで、等化信号１２が大なる方向に変化するときには
、これに対応してＲＯＭ２Ｏ３に利得を減少させる乗算
係数をあらかじめ記憶させておくと、このときのＲＯＭ
６０３からの出力に基づきディジタルフィルタ６は利得
を減少させる方向に働く。また、等化信号１２が小なる
方向に変化するときには、ＲＯＭ２Ｏ３に利得を増大さ
せる乗算器係数を出力するようにあらかじめ記憶させて
おくと、ディジタルフィルタは利得を増大させる方向に
働く。このようにして、固定比較電圧ｖ、、。、に尖頭
値検出電圧が一致するように働き、等化出力波形レベル
を固定比較電圧Ｖ 、ｏｆで決められるレベル値に制御
するように自動利得制御が行われる。Here, when the equalized signal 12 changes in the direction of increasing, it is possible to store in advance a multiplication coefficient that reduces the gain in ROM2O3 in response to this change.
Based on the output from 603, digital filter 6 works to reduce the gain. Further, when the equalized signal 12 changes in the direction of decreasing, the digital filter works in the direction of increasing the gain by storing in advance in the ROM 2O3 so as to output a multiplier coefficient that increases the gain. In this way, the fixed comparison voltage v, . , and automatic gain control is performed to control the equalized output waveform level to a level value determined by the fixed comparison voltage V,of.
本発明は以上説明したように、従来の各種線型フィルタ
および線型増幅器を使って構成していた自動利得制御回
路を全てディジタル信号処理回路で実現しているので、
集積回路化が可能になり、実装規模の大幅な削減および
低消費電力化を達成することができる効果がある。As explained above, the present invention realizes the automatic gain control circuit, which was conventionally configured using various linear filters and linear amplifiers, entirely using a digital signal processing circuit.
This makes it possible to integrate circuits, and has the effect of significantly reducing the packaging scale and reducing power consumption.
なお自動利得制御で補償する範囲すなわち異種の伝送路
および伝送路長に対して補償すべき範囲がＲＯＭの記憶
内容を変更するだけで対処できるので、従来のように個
々の補償範囲に対応して何種類ものハード構成の異なる
自動利得制御回路を用意する必要がなくなり、広い補償
範囲の自動利得制御を実現できる効果がある。Note that the range to be compensated for by automatic gain control, that is, the range to be compensated for different types of transmission paths and transmission path lengths, can be handled by simply changing the memory contents of the ROM. This eliminates the need to prepare several types of automatic gain control circuits with different hardware configurations, and has the effect of realizing automatic gain control with a wide compensation range.
第１図は本発明実施例の構成を示すブロック構成図。
第２図は従来例の構成を示すブロック構成図。
１・・・等化増幅器、２・・・尖頭値検出回路、３・・
・差動増幅器、４．８・・・サンプル回路、５．９・・
・Ａ・Ｄ変換器、６・・・ディジタルフィルタ、７・・
・Ｄ−Ａ変換器、１１・・・伝送路信号、１２・・・等
化信号、１３・・・利得制御信号、１４・・・乗算係数
信号、６０１・・・乗算器、６０２・・・遅延回路、６
０３・・・ＲＯＭ。
特許出願人 日本電気株式会社７．、、□−１代理人
弁理士 井 出 直 孝′ 。
ｊ
実施例の構成
第１図
従来例の構成
第２図FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block configuration diagram showing the configuration of a conventional example. 1... Equalization amplifier, 2... Peak value detection circuit, 3...
・Differential amplifier, 4.8...Sample circuit, 5.9...
・A/D converter, 6...Digital filter, 7...
- D-A converter, 11... Transmission line signal, 12... Equalization signal, 13... Gain control signal, 14... Multiplication coefficient signal, 601... Multiplier, 602... delay circuit, 6
03...ROM. Patent applicant: NEC Corporation7. ,,□-1 agent
Patent attorney Naotaka Ide'. j Structure of the embodiment Fig. 1 Structure of the conventional example Fig. 2
Claims (2)
力端子（１１）と、 所望のレベルのアナログ出力信号が通過する出力端子（
１２）と、 このアナログ出力信号の尖頭値と上記所望のレベルの尖
頭値に対応する基準信号とを比較して生成したアナログ
帰還信号を入力する帰還端子（１３）と を備えた等化増幅器において、 アナログ入力信号をディジタル信号に変換する第一変換
手段（４、５）と、 アナログ帰還信号をディジタル信号に変換する第二変換
手段（８、９）と、 上記第一および第二変換手段の出力にディジタル演算を
施して上記アナログ出力信号に相当のディジタル信号を
生成する演算手段（６）と、この演算手段の出力するデ
ィジタル信号をアナログ信号に変換する第三変換手段（
７）と を備えたことを特徴とする等化増幅器。(1) An input terminal (11) through which an analog input signal via a transmission line arrives, and an output terminal (11) through which an analog output signal of a desired level passes.
12), and a feedback terminal (13) for inputting an analog feedback signal generated by comparing the peak value of this analog output signal with a reference signal corresponding to the peak value of the desired level. In the amplifier, first conversion means (4, 5) for converting an analog input signal into a digital signal, second conversion means (8, 9) for converting an analog feedback signal into a digital signal, and the above-mentioned first and second conversion means. a calculation means (6) for performing digital calculation on the output of the means to generate a digital signal equivalent to the analog output signal; and a third conversion means (6) for converting the digital signal output from the calculation means into an analog signal.
7) An equalizing amplifier comprising:
算手段と、この乗算手段に与えられる乗算係数があらか
じめ記憶され、第二変換手段の出力をアドレス入力とす
るＲＯＭとを備えた特許請求の範囲第（１）項に記載の
等化増幅器。(2) The calculation means includes a multiplication means which receives the output of the first conversion means as an input, and a ROM in which a multiplication coefficient given to the multiplication means is stored in advance and whose address input is the output of the second conversion means. An equalizing amplifier according to claim (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25154686A JPS63104529A (en) | 1986-10-21 | 1986-10-21 | Equalizing amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25154686A JPS63104529A (en) | 1986-10-21 | 1986-10-21 | Equalizing amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63104529A true JPS63104529A (en) | 1988-05-10 |
Family
ID=17224436
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25154686A Pending JPS63104529A (en) | 1986-10-21 | 1986-10-21 | Equalizing amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63104529A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7224053B2 (en) * | 2002-09-06 | 2007-05-29 | Ricoh Company, Ltd. | Semiconductor device responsive to different levels of input and output signals and signal processing system using the same |
| KR101162177B1 (en) | 2010-08-05 | 2012-07-04 | (주)이오시스템 | Device for compensating gain of avalanche photo diode in optic measuring device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6024737A (en) * | 1983-07-20 | 1985-02-07 | Nippon Telegr & Teleph Corp <Ntt> | Variable equalizer |
-
1986
- 1986-10-21 JP JP25154686A patent/JPS63104529A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6024737A (en) * | 1983-07-20 | 1985-02-07 | Nippon Telegr & Teleph Corp <Ntt> | Variable equalizer |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7224053B2 (en) * | 2002-09-06 | 2007-05-29 | Ricoh Company, Ltd. | Semiconductor device responsive to different levels of input and output signals and signal processing system using the same |
| KR101162177B1 (en) | 2010-08-05 | 2012-07-04 | (주)이오시스템 | Device for compensating gain of avalanche photo diode in optic measuring device |
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