JPS63104526A - Arithmetic circuit for finite body - Google Patents

Abstract

PURPOSE:To attain the scale-down of a circuit and to enable a high speed arithmetic by constituting an arithmetic circuit with a multiplier which is made to obtain multiplied result as (2n-1) bit of output expressed in an expanded vector and a divider which is made to convert the above-mentioned output into (n) bit of output. CONSTITUTION:A first input of (n) bit expressing the element P of a finite body GF(2<n>) in vector is multiplied by a second input of (n) bit expressing the element Q of the finite body GF(2<n>) in vector. And the multiplier 11, which is made to obtain the multiplied result R as the output of (2n-1) bit expressed in the expanded vector and the divider 12, which is made to set the output from the multiplier 11 as an input and converts the output into the output of (n) bit obtained by expressing in vector concerning the multiplied result R of (2n-1) bit expressed in the expanded vector after executing the division in a primitive polynomial, are provided in a titled circuit. Thus the arithmetic circuit for the finite body, whose scale of the circuit is small and where the high speed arithmetic is possible, can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a finite field arithmetic circuit used in an encoder and decoder for error correction codes.

2. Description of the Related Art When recording and reproducing digital data, error correction codes are used to correct code errors caused by defects, scratches, dust, etc. on the recording medium. In particular, in recent years, adjacent codes, Reed-Solomon codes, and the like have been put into practical use for recording and reproducing digital audio signals.

These error correction code encoders generate and add parity data. Furthermore, the decoder calculates a syndrome from received data including parity data, and performs error correction based on this syndrome. Finite field operations are essential for generating parity data, calculating syndromes, and correcting errors.

A finite field GF(2”) is a primitive polynomial g (X
) is a field with 2n elements derived from

This finite field GF (2n minus luminous is a cyclic group, and elements P and Q other than luminous are P-α゛.

It is expressed as Q=αj. Further, regarding their multiplication P×Q, PXQ=(αi)×(αj)=α1゛J holds true. However, α is the root of the primitive polynomial g (when xi = 0).

An example of a conventional finite field arithmetic circuit will be described below with reference to the drawings. FIG. 4 shows a block diagram of a conventional finite field arithmetic circuit.

In FIG. 4, 1 is an inverse exponential conversion table, αi
When input, it outputs i. 2 is also an inverse exponential conversion table, and when αJ is input, j is output.

3 is an adder which inputs i and j obtained from inverse index conversion tables 1 and 2 and outputs i+j.

4 is an exponent conversion table, i+ obtained by adder 3
When j is input, αi''j is output. Conventionally, finite field operations (multiplications) have been performed using such a configuration.

Problems to be Solved by the Invention However, the above configuration has the following problems. That is, among the constituent elements, the inverse index conversion tables 1 and 2 and the index conversion table 4 can be specifically implemented using ROM (read-only memory), etc., but the above configuration requires three ROMs and one adder. Therefore, there was a drawback that the circuit scale became large. Furthermore, since two ROMs and one adder are connected in cascade, high-speed calculation is difficult.

In view of the problem mentioned above, the present invention provides a finite field arithmetic circuit that is small in circuit scale and capable of high-speed operation.

Means for Solving the Problems In order to solve the above problems, the finite field arithmetic circuit of the present invention has an n-bit first input which is a vector representation of the element P of the finite field GF(2''). , the element Q of the finite field GF (2fi) is multiplied by the n-bit second input expressed as a vector, and the multiplication result R is expressed as an enlarged vector (2n-1).
A multiplier configured to obtain the bit output, and the output of the multiplier described above as input, are subjected to division by a primitive polynomial, and the multiplication result R of (2n-1) bits, which is expressed as an expanded vector, is expressed as a vector. and a divider adapted to convert into an n-bit output.

Operation In the above-described configuration of the present invention, the multiplier and divider can be configured with AND gates, exclusive OR gates, etc., and since ROM and adders are not required, the circuit scale can be reduced.

Furthermore, since AND gates and exclusive OR gates operate much faster than ROMs and adders, it is possible to realize a finite field arithmetic circuit capable of high-speed arithmetic operations.

EXAMPLE Below, in order to explain an example of the present invention, a finite field GF (
2') will be explained first. In addition,
In the following explanation, multiplication on a finite field is represented by ×, addition on a finite field is represented by +, logical product (AND) is represented by ・, and exclusive OR (exclusive OR) is represented by ■.

As an example, consider a finite field CF (2') derived from the primitive polynomial g(x)=x' +x+1. The above finite field G
The element of F (2') is (0, αO1α weight, α2゜α3
．． ..., α14), 16 (=24).

By the way, α is the root of g (X) = O, so α
4+α+1=0, and by transposing terms according to the operation rules on a finite field, α4=α+1. Similarly, α5=α×α
4=α×(α+1)=α2+αα6; α2×α4=α2
×(α+1)=α3+α2α7;α3 ×α4=α
3 × (α+1)=α4 +α3 = (α+1)+
α3=α3 +α+ l α8 =α4 ×α4 = (α+1)× (α+1)
=α2+1 α8 =α×α8 =α× (α”+1)=α3+1, so all the elements of the above finite field GF (2' ”) are α0. α1. α2. It can be expressed as a linear combination of α3. (1 = α'' = α0) The state of this linear combination expressed as a 4-bit number is called the vector representation of the elements of the 8 finite field. For example, starting from the highest 4 bits, α3.α2° Assuming that α1.α0 is assigned, α3α2α1 α0 O=(0000) α’=(0001) α’=(0010) α”=(0100) α’=(1000’) α’=(0011) α5 =( 0110) α6=(1100) α'=(1011) α''=(0101'') α9=(1010) α'=(0111) α''=(1110) α12=<1111>α''=(1101) α ”=(1001). This is the vector representation of the element on the finite field GF (2').

Also, addition of elements of a finite field expressed as a vector is
This is realized using a bitwise exclusive OR operation. For example, (0001)... α0+(1011)
・・・・・・・・・α7(1010)・・・・・・
... becomes α9, and α0+α7=α9.

An embodiment of the present invention will now be described with reference to the drawings.

FIG. 1 shows a block diagram of a finite field arithmetic circuit in an embodiment of the present invention. In FIG. 1, 11 is a multiplier that multiplies a first input P expressed as a vector and a second input Q expressed as a vector, and the multiplication result R
is output as an enlarged vector representation. A divider 12 divides the multiplication result R expressed as an enlarged vector by a primitive polynomial to convert it into an output S expressed as a vector.

2 and 3 are diagrams for explaining the principle of multiplication in the finite field arithmetic circuit in the embodiment of FIG. 1. FIG. FIG. 2 shows calculations in the multiplier 11. The vector representation of the first input P is (p3pz p+
po )r Also, the vector representation of the second input Q is (q
:l q2 (11(10). In the polynomial representation of α, P=1)3 ・α3+p2 ・α2 +p
l ・α1 +p0 ・α' + Q =q 3・
α 3 + q 2 ・ α 2 + q violet ・ α 1 + q 0 ・ α 0. Let the result of PXQ be R, R=r= ・α6+r
5 ・α5+r4・α4+r3 ゆα3+r2・α2+r
, ・α1 +r0 ・α0, then ro =
po' (l.

r+ =p+' qo epo゛q+ rz"pgoqo ■p2°qI ■I) o'qzr3
“pxoqo ■pz” q+ ■pI°qzep
O°q1r4 ””pz°q+ ■pz'CLz Φ
PI' q:1rs =1):l°q2■p2°q3
r 6 = p3 '(1+). Since the multiplication result R is not divided by a primitive polynomial, it is expressed as a linear combination of terms α0 to α6, and this is called an expanded vector representation. The multiplication result R based on the expanded vector representation has the same value regardless of the primitive polynomial.

FIG. 3 shows the operation in the divider 12. Let the primitive polynomial g(x) = x' +x+l, and the expanded vector representation of the input R is (r6 rs r4 r3 rz
rlre), the vector representation of the output S is (
s, , SZ 51 So ). The enlarged vector representation is α6.compared to the vector representation. α5゜α4
There are many sections. Therefore, in order to convert an element on a finite field represented by an expanded vector into a vector representation, α6. α5,
The term α4 may be expanded into terms α3 to α0. For example, considering expanding r6 of the term α6, α is the root of the primitive polynomial g (X) = 0, so α4+α
+α=0, from this r6 ・ (α6+α3+α2)=
It is O. Expressing this as an expanded vector, (r60
0 r6 r60 0). When adding elements on a finite field, adding 0 does not change the original value, so
By adding this to R, the term r6 of α6 is eliminated and expanded into terms α3 and α2. Similarly, rS
+r4 is also deleted and expanded. Figure 3 shows this situation. From Figure 3, the output S= (Sz sg
5! 30 > are respectively 53=r3 ■r4 5g = rg ■r6 ■r5 SL = rI ■r5 ■r4 SO=ro er4.

5 and 6 show examples of specific circuit configurations of the multiplier 11 and the divider 12, which are the constituent elements of the finite field arithmetic circuit in the embodiment of FIG. 1. FIG. 5 shows an example in which the multiplier 11 is configured to perform the operations shown in FIG. In FIG. 5, 500 is an AND gate, and p in FIG. A logical product operation qo is performed. 501 to 544 are also AND gates, and each of them, like 500, performs the logical AND operation in FIG. 511-599 are exclusive OR gates, which are used to perform the addition in FIG.

Further, FIG. 6 shows an example in which the divider 12 is configured to perform the calculation shown in FIG. In Figure 6, 6
02 is an exclusive OR gate, and r3■ in Fig. 3
A logical AND operation r6 is performed.

602 to 606 are also exclusive OR gates, and each of them, like 601, performs the exclusive OR operation in FIG. 3, that is, addition of elements of a finite field expressed as a vector.

In addition, in the explanation of the embodiment shown in FIG. 1, GF(24)
Although the case has been described, the present invention can be applied to any finite field GF(2'').

In this case, the primitive polynomial is g (x) = x' + k
,-.

The configuration can be the same as that of this embodiment except that the vector representation is (2n-1) bits.

Furthermore, since addition using exclusive OR gates yields the same result even if the order is switched, the calculation speed can be further increased by optimizing the order of addition so that the operation delay of the entire arithmetic circuit is minimized. It is also possible to do so.

Effects of the Invention As described above, the present invention provides an element P of a finite field GF (2″)
Multiply the n-bit first input, which is a vector representation of and a multiplier 11 configured to obtain an output of (2n-1) bits, and the output of the multiplier 11 as input,
A divider 12 configured to perform division by a primitive polynomial and convert the (2n-1) bit multiplication result R expressed as an enlarged vector into an n-bit output expressed as a vector.
By providing these, it is possible to configure a finite field arithmetic circuit that has a small circuit scale and is capable of high-speed arithmetic operations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a finite field arithmetic circuit in an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of the multiplier 11 in FIG. 1, and FIG. Operation explanatory diagram, 4th
The figure is a block diagram of a conventional finite field arithmetic circuit, and FIG. 5 is a circuit diagram of a specific example of a circuit that realizes the arithmetic operation shown in FIG.
FIG. 6 is a circuit diagram of a specific circuit example for realizing the calculation shown in FIG. 3. 11... Multiplier, 12... Divider. Name of agent Patent attorney Toshio Nakao 1 person Figure 1 Input P Input Q Figure 5 Figure 6 Figure J3Sz SIS.

Claims (1)

[Claims] Multiply the n-bit first input, which is a vector representation of the element P of the finite field GF (2^n), by the n-bit second input, which is the vector representation of the element Q of the finite field GF (2^n). Then, a multiplier configured to obtain the multiplication result R as an output of (2n-1) bits expressed as an enlarged vector, and the output of the above multiplier are input, and division by a primitive polynomial is performed to obtain an enlarged vector expression. (2n-1) bits multiplication result R
1. A finite field arithmetic circuit comprising: a divider configured to convert S into an n-bit output S expressed as a vector.